Topics for Project, Diploma, - FAU · Topics for Project, Diploma, Bachelor’s, ... a C++ based...

Topics for Project, Diploma, Bachelor’s, and Master’s Theses

This is only a selection of topics. Further up-to-date thesis offers are available on the following web page:

http://www12.cs.fau.de/edu/dasa/

Automatic Integration of Hardware Accelerators for MPSoCs

The increasing complexity of embedded systemsalso necessitates a rise in the level of abstraction ofthe design flow. To facilitate this, the SystemC lan-guage, a C++ based class library and de facto indus-trial standard, is used to model embedded systemsat the Electronic System Level (ESL).In this thesis, you will use SystemC to model a sim-ple fractal viewer as a test application at the elec-tronic system level (ESL). Based on this applica-tion, you will learn how to automatically transformthe SystemC description into running hardware us-ing an OpenRISC CPU with the eCos real time op-erating system. To speed up the fractal computation, you are required to integrate dedicated hardwareaccelerators into the automatically generated software solution.The goal of this thesis is the extension of the automatic design flow tools developed at the Chair forHardware/Software Co-Design, such that integration of the hardware accelerators can be performedautomatically, hence, increasing the design productivity of the ESL design flow significantly.

Prerequisites: Basic C++-knowledge requiredType of Work: Theory (10%), Conception (30%), Implementation (60%)Supervisor: Joachim Falk ([email protected]), Tobias Schwarzer ([email protected])

Lehrstuhl fur Informatik 12Hardware-Software-Co-Design

Cauerstraße 1191058 Erlangen

Uncertainties during Reliability Analysis of MPSoCs

Ever shrinking device structures are one of the main reasons for a gro-

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wing inherent unreliability of embedded system components. The smalldevice structures are susceptible to, e.g., environmental changes li-ke cosmic rays or to manufacturing tolerances. Besides these effects,further uncertainties are present: Varying input profiles and errors du-ring system analysis itself. The research project CRAU at the Chair forHardware/Software Co-Design aims at considering these uncertaintiesduring the reliability analysis of Multi-Processor Systems-on-Chip (MP-SoCs).

This work shall investigate basic technique required for modeling ofuncertainties. For the various kinds of uncertainties, models shall bederived and their impact on the system analysis evaluated. Based onthese results, the employed analysis techniques are to be extendedaccordingly. One of the fundamental question is when and how to use, for example, upper and lowerbounds, distributions, or quantiles to model the analysis results under the influence of uncertainties.

Prerequisites: Basic JAVA-knowledge helpfulType of Work: The work has theoretical (formal considerations of uncertainties) as well implemen-

tation aspects (implementation of the uncertainty models and extension of the ana-lysis techniques) and can be focussed based on personal preferences.

Supervisors: Michael Glaß ([email protected])



Modeling and Evaluation of Partial Networking

The electrical and electronic system architecture is in a rebuilding phase.The requirement to lower the energy consumption of the car leads to theintegration of new technologies. Beside possibilities at ECU-layer, moreand more cross-system approaches are used. One of these possibilitiesis partial networking. The specific disabling of functionality and shutdownof components leads to a reduction of the power consumption. However, itrequires additional methods for coordinating the overall systems.

To evaluate the expected system behavior and other parameters early inthe design process, the Chair for Hardware/Software Co-Design has deve-loped a SystemC-based framework. With its help, a virtual prototype of the E/E-architecture can be buildand used for a simulation-based evaluation of the overall system. Furthermore, the framework alreadyprovides models for various system aspects.

The goal of this work is to extend existing work within the virtual prototyping of automotive E/E-architectureswith models for partial networking techniques. Moreover, the impact of partial networking in conjunctionwith different networking techniques to energy consumption and timing behavior should be evaluated.

Prerequisites: Knowledge of C/C++Type of Work: Theory (30%), Conception (20%), Implementation (50%)Supervisor: Sebastian Graf ([email protected])



Speeding Up Success Tree Analysis of Embedded Systems

Embedded systems are an indispensable part of our every-day life.Malfunctioning in these systems have consequences ranging from an-noying computer crashes, loss of data and services to financial or evenhuman life losses. Such impacts are getting worse as systems beco-me more complex and pervasive. So, the design of reliable systems isessential to ensure that future systems perform correctly despite risinglevels of complexity and uncertainties caused by environmental chan-ges like cosmic rays or manufacturing tolerances. The main context ofthis work is to analyze the reliability of embedded systems at designtime by means of so-called success trees.

This work is part of the CRAU project which focuses on system-level reliability analysis and designof reliable embedded systems. Currently, different techniques for reliability analysis of these systemshave been proposed in the chair of Hardware/Software Co-Design. In this thesis, the student should beinvolved with parallelizing the evaluation of one of these techniques based on success trees to speed-upthe analysis. The parallelization can be implemented using different tools, for example OpenMP. As asecond part of the work, the number of required sampling points for the Monte Carlo-based successtree evaluation shall be reduced by designing and implementing an adaptive sampling algorithm.

Prerequisites: Basic knowledge in Java appreciatedType of Work: Theory (30%), Conception (20%), Implementation (50%)Supervisor: Hananeh Aliee ([email protected])



Comparing ESL Modeling Frameworks for Mobile Commu-nication Services.

Modern electronic systems are ever more complex, with an increasingnumber of features and tighter constraints on power consumption. Thequick evaluation of architectural choices is a very important step in thedesign process of such systems. To achieve this, a system specificationat the Electronic System Level (ESL) is nowadays the first choice.

The Chair for Hardware/Software Co-Design develops the SystemCo-Designer framework that is tailored to the ESL design of embeddedsystems. In this thesis, an application from the mobile communicationdomain given in the SystemCoDesigner framework shall be reimplemented in another ESL design fra-mework from the literature. This aims at comparing (I) the performance and power consumption numbersof the models and (II) the design complexity and the modeling effort for each framework.

This thesis contributes to an ongoing research project together with Intel Mobile Communications GmbHand the Institute for Electronics Engineering (LTE).

Requirements: Programming experience in C/C++ or JavaType of Work: Theory (30%), Conception (20%), Implementation (50%)Contact: Rafael Rosales ([email protected])



High-Level-Synthesis for Medical Image Processing

Developing for the FPGA platform in medical applications has the ad-vantage of easier certification, when compared to software-solutions,the time necessary for development is, however, significantly longerdue to the cumbersome development flow of FPGA designs. Designtool developers have been struggling for years to close this so-calledproductivity gap. Xilinx, one of the major FPGA manufacturers, has re-cently released a C-based high-level synthesis framework, called Viva-do HLS, as part of its integrated design environment for FPGA de-velopment. As opposed to the classic hardware development process,high-level synthesis (HLS) aims at closing the productivity gap betweenhardware and software development, as well as to make the hardwaredevelopment process more accessible to those not yet familiar with thedetails of the FPGA platform.The goal of this thesis is to testdrive this new set of tools in order to implement algorithms from medicalimage processing on the FPGA and to compare the results to existing implementations on CPUs andGPGPUs.

Required Skills: Good knowledge C/C++, basic knowledge of VHDL or Verilog a plusNature of work: Theory (30%), Conception (20%), Implementation (50%)Contact: Moritz Schmid ([email protected])



Development of a FPGA-based, dynamic reconfigurable satellite radio sys-tem with a high reliability against Single-Event-Effects

The design of ASIC circuits for digital signal processing applications in sa-tellite systems is time consuming and expensive. Therefore recently the useof FPGAs is considered in order to reduce development times of modern sa-tellite systems. The ability of reconfiguration of FPGAs allows to make last-minute changes in the circuit design during design time and to adapt to newrequirements of the signal processing applications during the whole life cycleof the satellite.

During operation in space the FPGA is encountered with cosmic ray showers,which may lead to Single-Event-Effects like undesired bit flippings in the configuration memory. Withthese occurring bit flippings the reliability of the circuit is not guaranteed. The goal of this work is toimprove the reliability of these circuits by using dynamic partial reconfiguration. During the work on thethesis different CAD software tools for dynamic reconfiguration have to be analyzed and evaluated. Thethesis will be jointly supervised by the chair Informatik 12 and the Fraunhofer IIS.

Prerequisites: Good VHDL programming skills and experience in the FPGA design flow, knowled-ge of digital signal processing for data transmission is beneficial.

Type of Work: Theory (20%), Conception (30%), Implementation (50%)Supervisors: Bernhard Schmidt ([email protected])



Combining TMR (Triple Modular Redundancy) with partialreconfiguration for communication satellites

Fraunhofer IIS is currently involved in the German Heinrich Hertz com-

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munications satellite mission (H2Sat), which is due for launch into orbitin 2017. One element of the mission’s in-orbit validation (IOV) capabi-lity is a reconfigurable on-board processor (OBP) which Fraunhofer IIShas developed for communication applications. Its main componentsare four state-of-the-art radiation-hardened Virtex5-QV FPGAs with themost recent technology for space applications.

To reduce the impacts of solar particle effects Triple Modular Redun-dancy (TMR) is used. The goal of this work is to analyze and to eva-luate the operation of TMR in combination with partial reconfiguration.Using both design strategies at the same time implemented with diffe-rent CAD software tools is a challenging task. During the work on thethesis the dependencies among the CAD software tools have to be analyzed, to be understood and tobe controlled.

Prerequisites: Basic knowlegde of FPGAs, VHDL and synthesis toolsType of Work: Theory (30%), Conception (20%), Implementation (50%)Supervisors: Robert Glein ([email protected])

Bernhard Schmidt ([email protected])



Automatic Tool Flow Creation for PerformanceMeasurements in Embedded Systems

The rising complexity of embedded systems also necessitates a rise inthe level of abstraction of the design flow. To facilitate this, the SystemClanguage, a C++ based class library and de facto industry standard, isused to model embedded systems at the electronic system level (ESL).

One of the requirements of an ESL design flow is the ability to take per-formance measurements at this abstraction level. The chair of Hard-ware/Software Co-Design has a design flow, which transforms modelsin a certain subset of SystemC into a virtual platform. The virtual plat-form consists of SystemC modules and an instruction set simulator.

In this thesis, the transformation step from a SystemC ESL model intoa virtual platform will be extended by an automatic generation of perfor-mance measurement infrastructure. This infrastructure should be us-able to extract performance measurements for each of the componentswhich make up the SystemC ESL model of the embedded system.

Prerequisites: Basic C++-knowledge helpfulType of Work: Theory (20%), Conception (30%), Implementation (50%)Supervisor: Joachim Falk ([email protected])



Development of a Visualization and Debugging Environmentfor MPSoC Prototypes

As the technology is shifting from few-core to many-core systems, de-signers face many challenges to ensure future advances in computerarchitecture and programming models that are nothing short of rein-venting computing. To tackle this problem, new architectures, langua-ges and algorithms are required. Therefore a new parallel paradigm,called Invasive Computing has been proposed that utilizes the proces-sing resources depending on the application requirements. In order todebug and verify the functionality of such complex massively parallel systems, powerful debugging andvisualization environments are needed that are capable of illustrating the system status precisely.

This thesis involves the conceptual design and the development of a visualization and debugging envi-ronment for very large Multi-Processor System-on-Chip (MPSoC) architectures, consisting of hundredsto thousands of small processors, and its integration within a graphical user interface. Such an environ-ment should aggregate different hardware monitors of a system and transfer them through a suitablecommunication interface to a host workstation, where the transferred data is visualized by the graphicaluser interface.

Prerequisites: Knowledge of C/C++ and JAVA, skilled HDL languagesType of Work: Theory (20%), Conception (20%), Implementation (60%)Supervisors: Vahid Lari, Srinivas Boppu ({vahid.lari, srinivas.boppu}@cs.fau.de)



Transformation from Simulink to SystemC

MATLAB/Simulink is a modeling and simulation platform, which is current-ly heavily used in the industry sector crossing multiple domains, suchas automotive industry, telecommunication, semiconductor. It offers func-tional simulation and code generation directly from its graphical blockdiagrams. For most embedded systems, however, non-functional pro-perties such as the timing behavior play also an essential role. To co-pe the non-functional properties, the chair for Hardware/Software Co-Design has developed a system-level description modeling languagewhich is based on SystemC.

The goal of this work is to develop a code generator that transformsSimulink block diagrams (consist of standard blocks, stateflow blocksand toolbox blocks ) to corresponding SystemC descriptions . An exis-ting automotive application - Brake-by-Wire serves as the test case.

Prerequistes: Programming skills in C/C++Nature of work: Theory (30%), Conception (30%), Implementation (40%)Supervisor: Liyuan Zhang ([email protected])



Boost FPGA Performance by using High Clock Frequencies

The utilization of the used FPGA resources in time is rather low com-pared to an ASIC due to the lower clock frequency. The efficiency ofFPGA resources (lookup tables) can be increased by using designswith many pipeline stages combined with a very high clock frequency.However, designs with clock frequencies up to 500 MHz needs sophisti-cated placement and routing techniques to hold the timing constraints.

In this work, the automatic insertion of pipeline stages in data pathsafter synthesis and the usage of high clock frequencies should be in-vestigated. The overall goal is to increase the efficiency and perfor-mance of FPGAs. The data paths of critical parts of a design should beanalyzed and additional pipeline stages should be automatic inserted.Moreover, the placement and routing of these pipeline stages shouldbe investigated in order to reach a high clock frequency.

Prerequisites: Good knowledge in FPGA design flowType of Work: Theory (30%), Conception (40%), Implementation (30%)Supervisor: Daniel Ziener ([email protected])



Increasing FPGA-Lifetime by Dynamical Reconfiguration

Ever shrinking device structures allow on the one hand more com-

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plex systems, whereas on the other hand this trend results in an in-creased susceptibility of modern embedded systems to radiation andtemperature-dependent aging effects. This holds also true for futureFPGA devices which suffer from the heat produced from computationintensive modules. These modules accelerate the local FPGA aging.Dynamical reconfiguration could help to distribute these high-activemodules in a way that the wear is equalized over the FPGA area. Byusing this technique, the lifetime of the FPGA can be increased signifi-cantly.

In this thesis, the local FPGA temperature dispensation should be esti-mated at run-time and modeled with the help of expected activities oncertain modules. This temperature information can be used by a me-thod which is developed at our chair to determine a better module pla-cement with respect to FPGA aging.

Prerequisites: Good knowledge in software programming (e.g., Java or C++)Type of Work: Theory (30%), Conception (40%), Implementation (30%)Supervisor: Daniel Ziener ([email protected])



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