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AliasesAliases

SubprogramsSubprograms

Generics & ConfigurationsGenerics & Configurations

March 2003March 2003 Advanced Topics on VHDLAdvanced Topics on VHDL Guangfa LuGuangfa Lu

AliasesAliases

An An alternate namealternate name for name items for name items

Can significantly improve the readability of VHDL codes by using a shorthand notation for long names.

Provides a mechanism to refer to the same named item in different ways.


AliasesAliases

signal S: BIT_VECTOR (31 downto 0);

31 30 23 0

31 26 23 18 0

Sign Exponent Mantissa

OP Reg Base Offset

Can represent:

Or:

An example:


AliasesAliases

Syntax:Syntax:

alias identifier [ : identifier-type] is item-name;

alias identifier [ : identifier-type] is item-name [signature];

Optional “signature” portion


AliasesAliases

Object aliases

Constant Signal Variable File

Non-Object aliases

Function names Literals Type names Attribute names

Except: labels, loop parameters, and generate parameters


AliasesAliases

Examples :

constant number_of_bytes : integer :=4;alias N : integer is number_of_byptes;

Object aliases:


AliasesAliases

Example:Suppose we need to use objects from two different packages,

work.alu_types.all and work.io_types.all, and each declare a constant named data_width with different values.

Then we have to refer to them as:• work.alu_tpes.data_width• work.io_types.all.data_width

It’s not convenient !

If we include packages as follows:

Object aliases:


AliasesAliases

We can avoid this by: Introducing two alias declarations into our model!

Object aliases:


AliasesAliasesNone-object aliases:

Example:

functionnames

literal

type name


AliasesAliases

With aliases, it is possible to declare something With aliases, it is possible to declare something like ‘like ‘subtypessubtypes’, if the what we required is just a ’, if the what we required is just a somewhat restricted version of the original type.somewhat restricted version of the original type.

In this way, we break down complex data In this way, we break down complex data structures into simpler parts that can be structures into simpler parts that can be accessed directly.accessed directly.


AliasesAliasesAn example:

functionnames


AliasesAliases

With aliases, it is possible to declare something With aliases, it is possible to declare something like ‘like ‘subtypessubtypes’, if the what we required is just a ’, if the what we required is just a somewhat restricted version of the original type.somewhat restricted version of the original type.

In this way, we break down complex data In this way, we break down complex data structures into simpler parts that can be structures into simpler parts that can be accessed directly.accessed directly.

Notice: we are NOT defining a new data type.

However, there are real subtypes.


AliasesAliases

SignatureSignature


The “signature” portion is optional.

Used for• Subprograms• Enumeration literals


AliasesAliases

Syntax:Syntax:


The “signature” portion is optional.

[ type_mark ,… return type_mark ]

Signature’s syntax rule:


AliasesAliasesNone-object aliases:

Example:

functionnames

literal

type name

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AliasesAliases





Like other programming languages, VHDL provides subprogram facilities in the form of functions and procedures.

VHDL also provided a package facility for collecting declarations and objects into modular units.

Packages also provide a measure of data abstraction and information hiding.



Two steps:

① First they must be declared;② Then they can be called elsewhere.



Modes:

FunctionsFunctions

inputinput

ProceduresProcedures

input outputinput output

Mode:Mode: inin in in outout / / inoutinout


Functions: Can be used within an expression; Can be used to describe frequently used sequential algorithms; Return a single value; Execute in zero simulation time (no WAIT allowed).

SubprogramsSubprograms: functions: functions



Declaration:

[pure | impure] function identifier [( parameter_interface_list )] return type_mark is{ subprogram_declarative_item }

begin{ sequential_statements }

end [ function ] [ identifier ];

Where parameter_interface_list is:

([ constant | variable | signal ] identifier {, …} : intype_indication [ := static_expression ] ) { ,…}

mode



Example:Example:



Declaration:




Call:

identifier [(parameter_association_list )]


Example:Example:




Declaration:




By default, functions are declared as pure;In pure functions, the only accessible data are the input arguments; and the only returned information from this function is the returned value. Pure functions do not have access to objects outside the function.

VHDL’93 introduces impure declaration;Impure functions must be explicitly declared;Impure functions can modify data outside their own scope.



Example:Example:

The file bit_file is an outside object. Since the function is impure, accessing to the file bit_file is possible.



Usages of functions:Usages of functions: Returning a value in an expression.Returning a value in an expression. Conversion functions.Conversion functions. ------ to convert an object of one type to ------ to convert an object of one type to

another another Resolution functions.Resolution functions. ------ to resolve bus contention on a ------ to resolve bus contention on a

multiply-driven signalmultiply-driven signal



Conversion functions.Conversion functions. are used to convert an object of one type to are used to convert an object of one type to

another to allow mapping of signals and ports another to allow mapping of signals and ports of different types. This type of situation of different types. This type of situation usually arises when a designer wants to make usually arises when a designer wants to make use of an entity from anther design that uses use of an entity from anther design that uses a different data type.a different data type.



Resolution functionsResolution functions

are used to return the value of a signal when are used to return the value of a signal when the signal is driven by multiple drivers. It is the signal is driven by multiple drivers. It is illegal in VHDL to have a signal with multiple illegal in VHDL to have a signal with multiple drivers without a resolution function attached drivers without a resolution function attached to it.to it.A resolution function has a signal-argument A resolution function has a signal-argument input (consists of an unconstrained array of input (consists of an unconstrained array of driver values for the signal) and returns a driver values for the signal) and returns a single signal value.single signal value.


Procedures: Can be used to partition large behavioral descriptions into modular sections; A procedure call may be a sequential or concurrent statement; Arbitrary number of parameters of any possible direction ( in / out / inout ); May or may not execute in zero simulation time.

SubprogramsSubprograms: procedures: procedures



Declaration:

procedure identifier [( parameter_interface_list )] is{ subprogram_declarative_item }


end [ procedure ] [ identifier ];

Where parameter_interface_list is:

([ constant | variable | signal ] identifier {, …} : modetype_indication [ := static_expression ] ) { ,…}



Declaration:




Call statement:

[ label : ] procedure_name [ (parameter_association_list)];


SubprogramsSubprograms: procedures: proceduresExample:



Default Values in the parameters:When the procedure is called, we can use

either leave it out in the caller’s parameter list, or use keyword ‘open’.


SubprogramsSubprograms: procedures: proceduresExample:

or

or



Declaration:




Call statement:

[ label : ] procedure_name [ (parameter_association_list)];;



call_proc: p ( s1, s2, val );call_proc: p ( s1, s2, val ); call_proc: call_proc: process isprocess is

beginbegin

p ( s1, s2, val );p ( s1, s2, val );

wait onwait on s1, s2; s1, s2;

end processend process call_proc; call_proc;

Concurrent Procedure Call Statements:are equivalent to the same procedures with a wait statement, whose

sensitivity clause includes the signals mentioned in the parameter list.

The equivalent procedure:The equivalent procedure:A concurrent procedure call:A concurrent procedure call:



Function: encapsulates a collection of statements that

compute a resultgenerate an expression

Procedure: encapsulates a collection of sequential statements to executegenerate a statement

GenericsGenerics&&

ConfigurationsConfigurations


GenericsGenerics

Can we write general models instead of Can we write general models instead of making specific models with VHDL ?making specific models with VHDL ?


GenericsGenerics

MotivationMotivation:: Oftentimes we want to be able to specify a property Oftentimes we want to be able to specify a property

separately for each instance of a component.separately for each instance of a component. VHDL allows models to be parameterized with VHDL allows models to be parameterized with

generics.generics. Allows one to make general models instead of Allows one to make general models instead of

making specific models for many different making specific models for many different configurations of inputs, outputs, and timing configurations of inputs, outputs, and timing information.information.

Information passed into a design description from Information passed into a design description from its environment.its environment.


GenericsGenericsA genericA generic

entity AND_GATE is generic ( N: natural := 2 ); port ( A: in bit_vector (1 to N ); Z: out bit);end AND_GATE;

architecture generic_ex of AND_GATE isbegin process (A) variable AND_OUT:bit; begin AND_OUT := ‘1’; for k in 1 to N loop AND_OUT := AND_OUT and A(k); exit when AND_OUT = ‘0’; end loop; Z<=AND_OUT; end process;end GENERIC_EX;

AND gateAND gate


GenericsGenerics

A generic declares a constant object of A generic declares a constant object of mode mode inin (read only); The value of this (read only); The value of this constant can be specified as a static constant can be specified as a static expression globally:expression globally:

Then it can be used in the entity declaration Then it can be used in the entity declaration and its corresponding architecture bodies.and its corresponding architecture bodies.

The value of a generic must be determined The value of a generic must be determined at elaboration time (explicitly specified at at elaboration time (explicitly specified at least once).least once).


GenericsGenerics

The value for a generic may be specifiedThe value for a generic may be specified

in an entity declaration;in an entity declaration; in a component declaration;in a component declaration; in a component instantiation.in a component instantiation.


GenericsGenericsentity ANOTHER_GEN_EX isend;

archiecture GEN_IN_COMP of ANOTHER_GEN_EX is component NAND_GATE generic (M: INTEGER); port (A: in bit_vector(M downto 1); z: out bit); end component;

component AND_GATE generic (N: natuaral := 5); port (A: in bit_vector(1 to N); Z: out bit); end component; signal S1, S2, S3, S4: bit; signal SA: bit_vector( 1to 5); signal SB: bit_vector( 2 downto 1); signal SC: bit_vector(1 to 10); signal SD: bit_vector(5 downto 0);begin N1: NAND_GATE generic map (6) port map (SD, S1); --N2: NAND_GATE port map (SB, S2); A1: AND_GATE generic map (N => 10) port map (SC, S3); A2: AND_GATE port map (SA, S4);end GEN_IN_COMP;

component declarationscomponent declarations

component instantiationscomponent instantiations


GenericsGenerics

Notes:Notes:

Generic information is staticGeneric information is static

------it can not be changed during the ------it can not be changed during the simulation.simulation.

Generic value is instance-specificGeneric value is instance-specific

------different instances of the same ------different instances of the same component can have different values.component can have different values.



Why we need configurations ?Why we need configurations ?

It may be convenient to specify multiple views It may be convenient to specify multiple views for a single entity and use any one of them for for a single entity and use any one of them for simulation.simulation.

For example, there are three architecture bodies, called For example, there are three architecture bodies, called FA_BEH, FA_STR, and FA_MIXED, corresponding to an entity FA_BEH, FA_STR, and FA_MIXED, corresponding to an entity FULL_ADDER. We can select any of them for simulation by FULL_ADDER. We can select any of them for simulation by specifying an appropriate configuration.specifying an appropriate configuration.



ConfigurationsConfigurationsA VHDL description may consist of A VHDL description may consist of

many design entities, each with several many design entities, each with several architectures, and organized into a design architectures, and organized into a design hierarchy. The hierarchy. The configurationconfiguration does the job does the job of specifying the exact set of entities and of specifying the exact set of entities and architectures to use, in other words, architectures to use, in other words, binding component instances to entities.binding component instances to entities.



ConfigurationsConfigurations Specify which architectures to use for a Specify which architectures to use for a

particular componentparticular component Specify which parameter values to use for a Specify which parameter values to use for a

particular componentparticular component



A configuration is therefore used to bind A configuration is therefore used to bind the following pairs:the following pairs: An architecture body to its entity declarationAn architecture body to its entity declaration A component with an entityA component with an entity

Definition:Definition: Associating an architectural description with a Associating an architectural description with a

component in a structural model. component in a structural model.



Choose componentChoose component


ConfigurationsConfigurationsVHDL provides two ways of binding:VHDL provides two ways of binding:

By using a configuration specificationsBy using a configuration specifications Is used to bind component instantiations to specific Is used to bind component instantiations to specific

entities stored in design libraries.entities stored in design libraries.

By using a configuration declarationsBy using a configuration declarations The binding can be performed after the architecture The binding can be performed after the architecture

body has been written.body has been written. More than one configuration declaration for an entity More than one configuration declaration for an entity

is possible.is possible. The power lies in that the sub-components in an The power lies in that the sub-components in an

entire hierarchy of a design can be bound using a entire hierarchy of a design can be bound using a single configuration declaration.single configuration declaration.

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