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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Topics
The logic design process.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Combinational logic networks
Functionality. Other
requirements:– Size.– Power.– Performance.
Combinationallogic
Primaryinputs
Primaryoutputs
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Non-functional requirements
Performance:– Clock speed is generally a primary requirement.
Size:– Determines manufacturing cost.
Power/energy:– Energy related to battery life, power related to heat.
– Many digital systems are power- or energy-limited.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Mapping into an FPGA
Must choose the FPGA:– Capacity.– Pinout/package type.– Maximum speed.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Hardware description languages
Structural description:– A connection of components.
Functional description:– A set of Boolean formulas, state
transitions, etc. Simulation description:
– A program designed for simulation.
Major languages:– Verilog.– VHDL.
A
NAND
x
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Logic optimization
Must transform Boolean expressions into a form that can be implemented.– Use available primitives (gates).
– Meet delay, size, energy/power requirements.
Logic gates implement expressions.– Must rewrite logic to use the expressions provided by
the logic gates.
Maintain functionality while meeting non-functional requirements.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Macros
Larger modules designed to fit into a particular FPGA.– Hard macro includes placement.– Soft macro does not include placement.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Physical design
Placement:– Place logic components into FPGA fabric.
Routing:– Choose connection paths through the fabric.
Configuration generation:– Generate bits required to configure FPGA.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Example: parity
Simple parity function:– P = a0 XOR a1 XOR a2 XOR a3.
Implement with Xilinx ISE.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Xilinx ISE main screen
Sources in project
Processes for source
Source window
Output
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
New project
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
New project info
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Create HDL file
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
I/O description
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
I/O info
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Empty Verilog description
module parity(a,p);
input [31:0] a;
output p;
endmodule
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Verilog with functional code
module parity(a,p);
input [31:0] a;
output p;
assign p = ^a;
endmodule
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
RTL schematic: top-level
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
RTL model: implementation
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Example: simulation
Apply stimulus/test vectors. Look at response/output vectors. Can’t exhaustively simulate but we can
exercise the module. Simulation before synthesis is faster and
easier than simulating the mapped design.– Sometimes want to simulate the mapped
design.
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Testbench
testbench
UnitUnderTest
(UUT)
Stimulus
Response
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Automatically-created testbench
module parity_testbench_v_tf();// DATE: 11:48:13 11/07/2003 // MODULE: parity// DESIGN: parity// FILENAME: testbench.v// PROJECT: parity// VERSION: // Inputs reg [31:0] a;// Outputs wire p;// Bidirs// Instantiate the UUT parity uut ( .a(a), .p(p) );// Initialize Inputs ‘ifdef auto_init initial begin a = 0; end ‘endifendmodule
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Test vector application code
initial begin $monitor("a = %b, parity=%b\n",a,p); #10 a = 0; #10 a = 1; #10 a = 2’b10; #10 a = 2’b11; #10 a = 3’b100; #10 a = 3’b101; #10 a = 3’b110; #10 a = 3’b111; … #10 a = 1024; #10 a = 1025; #10 a = 16’b1010101010101010; #10 a = 17’b11010101010101010; #10 a = 17’b10010101010101010; #10 a = 32’b10101010101010101010101010101010; #10 a = 32’b11101010101010101010101010101010; #10 a = 32’b10101010101010101010101010101011; $finish;end
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FPGA-Based System Design Copyright 2004 Prentice Hall PTR
Project summary