Today VLSI Fundamentals

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 20: April 3, 2018 Memory: Core Cells

Penn ESE 570 Spring 2018 – Khanna

Today

!  Memory "  RAM Memory

"  Architecture "  Memory core

"  SRAM "  DRAM

"  Periphery

2 Penn ESE 570 Spring 2018 - Khanna

Memory Overview


Array-Structured Memory Architecture

Input-Output(M bits)

Row

Dec

oder

AK

AK+1

AL-1

2L-K

Column Decoder

Bit Line

Word Line

A0

AK-1

Storage Cell

Sense Amplifiers / Drivers

M.2K

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

Penn ESE 570 Spring 2018 - Khanna

Read-Write Memories (RAM)

!  Static (SRAM) "  Data stored as long as supply is applied "  Large (6 transistors/cell) "  Fast "  Differential

!  Dynamic (DRAM) "  Periodic refresh required "  Small (1-3 transistors/cell) "  Slower "  Single ended


6T SRAM Cell

!  Cell size accounts for most of memory array size !  6T SRAM Cell

"  Used in most commercial chips "  Data stored in cross-coupled inverters

!  Read: "  Precharge BL, BL’ "  Raise WL

!  Write: "  Drive data onto BL, BL’ "  Raise WL

6

bit bit_b

word

BL BL’ WL


2

6-transistor CMOS SRAM Cell






Assume 1 is stored (Q=1)

1 0

CMOS SRAM Analysis (stored 1)

VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )VDD

2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=

(W/L)n,M5 ≤ 10 (W/L)n,M1 (supercedes read constraint)


1 0



1 0

Assume 1 is stored (Q=1) Read Operation: -  First bitlines get

precharged high (Vdd)

-  Then wordline goes high (Vdd)

VDD VDD

CMOS SRAM Analysis (Read)

VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=



1

VDD VDD

0

VDD

3


VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=



1

VDD VDD

0

kn,M5 VDD − ΔV −VTn( )2= kn,M1 (VDD −VTn)ΔV −

ΔV 2

2

⎛

⎝⎜⎜

⎞

⎠⎟⎟

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=



1

VDD VDD

0

kn,M1kn,M 5

=

WL

⎛

⎝⎜

⎞

⎠⎟1

WL

⎛

⎝⎜

⎞

⎠⎟5

=VDD −ΔV −VTn( )

2

(VDD −VTn )ΔV −ΔV 2

2

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=



1

VDD VDD

0

WL

⎛

⎝⎜

⎞

⎠⎟1

WL

⎛

⎝⎜

⎞

⎠⎟5

=VDD − 2VTn( )

2

(VDD −1.5VTn )VTn

ΔV =VTn

VDD

kn,M1kn,M 5

=

WL

⎛

⎝⎜

⎞

⎠⎟1

WL

⎛

⎝⎜

⎞

⎠⎟5

=VDD −ΔV −VTn( )

2

(VDD −VTn )ΔV −ΔV 2

2


0 0

0.2 0.4 0.6 0.8

1 1.2

0.5 1 1.2 1.5 2 Cell Ratio (CR)

2.5 3

Volta

ge R

ise

(V)



VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=



1

VDD VDD

0

VDD



1 0 0 VDD

Assume 1 is stored (Q=1) Write Operation: -  Want to write a 0 -  First drive bitlines

with input data -  Then wordline goes

high (Vdd)

4

CMOS SRAM Analysis (Write)

VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞ kp M4, VDD VTp–( )VDD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )V DD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

kn,M6 VDD −VTn( )2= kn,M4 (VDD −VTp)VQ −

VQ2

2

⎛

⎝⎜⎜

⎞

⎠⎟⎟

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

kn,M4kn,M6

=VDD −VTn( )

2

(VDD −VTp)VQ −VQ2

2

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

kn,M4kn,M6

=VDD −VTn( )

2

(VDD −VTp)VTn −VTn2

2

PR =W4 L4W6 L6

kn,M4kn,M6

=VDD −VTn( )

2

(VDD −VTp)VQ −VQ2

2

VQ =VTn

VDD


PR =W4 L4W6 L6



VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0 PR =W4 L4

W6 L6

VDD

5

Consider (5T SRAM)

!  How should we size the devices for read and write without faults?

25 Penn ESE 370 Fall 2018 - Khanna

Reminder: Charge Sharing

!  Initially "  A @ 1V "  B @ 0V

!  QA=1V*C1=C1 Close switch !  Qtot=Vfinal*(C1+C0) !  Charge conservation

"  QA=Qtot

!  C1=Vfinal*(C1+C0)

26

€

Vfinal =C1

C1+C0Penn ESE 370 Fall 2018 - Khanna

Consider

!  Read: What happens to voltage at A when WL turns from 0#1? "  Assume Waccess large "  Waccess >> Wpu=1 "  BL initially 0 "  A initially 1


Voltage After enable Word Line

!  QBL = 0 !  QA = (1V)(γ(2+Waccess)C0)

!  100fF=CBL>>CA=(γ(2+Waccess)C0)

!  After enable Waccess (Waccess large)

"  Total charge QBL +QA unchanged "  Charge conservation

"  Distributed over larger capacitance~=CBL

"  VA=VBL~= CA/CBL

28

€

Vfinal =C1

C1+C0

Penn ESE 370 Fall 2018 - Khanna

Simulation: Waccess=100


Larger Resistance?

!  What happens if Waccess small? "  Waccess < Wpu


6

Larger Resistance?

!  What happens if Waccess small? "  Waccess < Wpu

!  Takes time to move charge from A to BL

!  Moves more slowly than replenished by Wpu


Simulation


Charge Sharing

!  Conclude: charge sharing can pull down voltage


Consider (5T SRAM)

!  What happens to voltage at A when reading "  I.e when WL turns from 0#1? "  Assume Waccess large "  Bit cell stores a

"  A initially 1

"  BL precharged to 0 "  B initially 0


Simulation Waccess=20




7

Charge Sharing

!  Conclude: charge sharing can lead to read upset "  Charge redistribution adequate to flip state of bit


How might we avoid?


Charge to middle Voltage

!  Pre-charge bitlines to Vdd/2 before begin read operation

!  Now charge sharing doesn’t swing to opposite side of midpoint




Compare

!  Both Waccess=20; vary BL precharge voltage


Simulation Waccess=20 (precharge Vdd/2, reading 0)


8

Simulation Waccess=20 (with precharge Vdd/2)


Pre-Charge Vdd/2 Reference

!  Use one phase of clock to charge a node to some initial value before operation


Multiple Ports

!  We have considered single-ported SRAM "  One read or one write on each cycle

!  Multiported SRAM are needed for register files !  Examples:

"  Pipelined ALU register file: "  add r1,r2,r3 "  R3$R1+R2 "  Requires two

reads and one write


Dual-Ported SRAM

!  Simple dual-ported SRAM "  Two independent single-ended reads "  Or one differential write

46

bit bit_b

wordBwordA


Dual-Ported SRAM

!  Simple dual-ported SRAM "  Two independent single-ended reads "  Or one differential write

!  Do two reads and one write by time multiplexing "  Read during ph1, write during ph2

47

bit bit_b

wordBwordA


Multi-Ported SRAM

!  Adding more access transistors hurts read stability !  Multiported SRAM isolates reads from state node !  Single-ended bitlines save area


9

DRAM

!  Smaller than SRAM !  Require data refresh to compensate for leakage

49 Penn ESE 570 Spring 2018 – Khanna

3-Transistor DRAM Cell

M2M1

BL1

WWL

BL2

M3

RWL

CS

X

WWL

RWL

X

BL1

BL2

VDD-VT

ΔV

VDD

VDD-VT

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn


1-Transistor DRAM Cell

CSM1

BL

WL

CBL

WL

X

BL

VDD−VT

VDD/2

VDD

GND

Write "1" Read "1"

sensingVDD/2

ΔV VBL VPRE– VBIT VPRE–( )CS

CS CBL+------------------------= =

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.


DRAM Cell Observations

!  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out

!  DRAM memory cells are single ended in contrast to SRAM cells

!  The read-out of the 1T DRAM cell is destructive "  Read and refresh operations are necessary for correct operation

!  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design

!  When writing a “1” into a DRAM cell, a threshold voltage is lost "  This charge loss can be circumvented by bootstrapping the word

lines to a higher value than VDD


Memory Periphery


Array Architecture

!  2n words of 2m bits each !  Good regularity – easy to design !  Very high density if good cells are

used


10

Array Architecture


used


Array Architecture


used


Array Architecture


used


Decoders


Decoders

!  n:2n decoder consists of 2n n-input AND gates "  One output needed for each row of memory "  Build AND from NAND or NOR gates

Static CMOS

59

word

A0

A1

11

11

4

8word0

word1

word2

word3

A0A1


Large Decoders

!  For n > 4, NAND gates become slow "  Break large gates into multiple smaller gates

60

word0

word1

word2

word3

word15

A0A1A2A3


11

Predecoding

!  Many of these gates are redundant "  Factor out common

gates into predecoder "  Saves area "  Same path effort

61

A0

A1

A2

A3

word1

word2

word3

word15

word0

1 of 4 hotpredecoded lines

predecoders


Row Select: Precharge NAND


Row Select: Precharge NOR


Column Circuitry

& Bit-line Conditioning


Array Architecture


used


Column Circuitry

!  Some circuitry is required for each column "  Bitline conditioning

"  Precharging "  Driving input data to bitline

"  Sense amplifiers "  Column multiplexing (AKA Column Decoders)


12

Bitline Conditioning

!  Precharge bitlines high before reads

67

φbit bit_b


BL BL’



68

φbit bit_b


BL BL’



!  What if pre-charged to Vdd/2? "  Pros: reduces read-upset "  Challenge: generate Vdd/2 voltage on chip

69

φbit bit_b


BL BL’



!  What if pre-charged to Vdd/2? "  Pros: reduces read-upset "  Challenge: generate Vdd/2 voltage on chip

70

φbit bit_b


BL BL’

Voltage Midpoint Reference Generator

!  The inverter with input and output tied together settles to the midpoint of the transfer curve where the input and output are equal

!  The second inverter is driven to the same point. It helps isolate the output from the reference. The pass gate allows you to connect or disconnect this reference voltage to a node.


Sense Amplifiers

!  Bitlines have many cells attached "  Ex: 32-kbit SRAM has 128 rows x 256 cols "  128 cells on each bitline

!  tpd ∝ (C/I) ΔV "  Even with shared diffusion contacts, 64C of diffusion

capacitance (big C) "  Discharged slowly through small transistors in each

memory cell (small I)

!  Sense amplifiers are triggered on small voltage swing (ΔV)


V(0) t

VPRE

V BL

Sense amp activated Word line activated

V(1)

ΔV

13

Differential Pair Amp

!  Differential pair requires no clock !  But always dissipates static power

73

bit bit_bsense_b sense

N1 N2

N3

P1 P2


BL BL’

Clocked Sense Amp

!  Clocked sense amp saves power !  Requires sense_clk after enough bitline swing !  Isolation transistors cut off large bitline capacitance

74

bit_bbit

sense sense_b

sense_clk isolationtransistors

regenerativefeedback


SRAM Read Circuit

75

Kenneth R. Laker, University of Pennsylvania,

updated 02Apr15

MP2

M2 WBWB

MA2

MA4 MA5

MA1 MA3

VNOT-C VC

Differential Sense Amplifier (one per column)

Sense Amp Gain:

Read Select

φS


SRAM Read Circuit

76

Kenneth R. Laker, University of Pennsylvania,

updated 02Apr15

MP2

M2 WBWB

MA2

MA4 MA5

MA1 MA3

VNOT-C VC

Differential Sense Amplifier (one per column)

Sense Amp Gain:

Read Select

φS


SRAM Write Circuit

77

W DATA WB WB OPERATION (M3 ON)

WRITE CKT

(1) (0) (0)

(0)


SRAM Write Circuit

78

(1)

(0)

(0)

(1)

(0)

W DATA WB WB OPERATION (M3 ON)

WRITE CKT

(1)


14

Array Architecture Details


Column Drivers: Memory Bank


Tristate Buffer

!  Typically used for signal traveling, e.g. bus !  Ideally all devices connected to a bus should be

disconnected except for active device reading or writing to bus

!  Use high-impedance state to simulate disconnecting

81

Input Output

En Input En Ouptut

0 0 Z

1 0 Z

0 1 0

1 1 1 Active-high buffer


Tristate Buffer

82

Input Output

En

Input Output

En

Output

En

En Input

Vdd

CMOS circuit


Tristate Inverters


Output

En

Input

Output

En

Input

Ended here


15

8x4 Memory with column decoder

85

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

8x4 Memory 2-to-4

Decoder

Row

Decoder

A0

A1

1-to-2 Decoder Column Decoder

D0 D1 D2 D3

Tristate Buffer (read)

0 1

A0

Column Select CS


(A2)

Read/Write Memory

86





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder

1-to-2 Column Decoder 0 1

A0

CS

Rd/Wr

D0 D1 D2 D3


A0

A1

Column Select

(A2)

Read/Write Memory

87





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder


A0

CS

Rd/Wr = 0

D0 D1 D2 D3


A0

A1

Column Select

(A2) = 0

Read/Write Memory

88





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder


A0

CS

Rd/Wr = 1

D0 D1 D2 D3


A0

A1

Column Select

(A2) = 1

Idea

!  Memory for compact state storage !  Share circuitry across many bits

"  Minimize area per bit # maximize density

!  Aggressively use: "  Pass transistors, Ratioing "  Precharge, Amplifiers to keep area down


Admin

!  Homework 7 due Thursday

!  Final Project "  Design and layout memory "  Handout posted before Thursday class "  Due 4/24 (last day of class)

"  Everyone gets an extension until 5/4 "  Keep in mind our final exam is on 4/30

"  Leave time to study!


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