TLC59291 Datasheet - Texas Instruments · (LSD) with Invisible Detection Mode (IDM) • Output...

SIN

SCLK

LAT

BLANK

SOUT

VCC

GND

OUT0 - - - - - - - - - - OUT15

TLC59291

GND

GND

ICn

RIREF

IREF

BLANK

LAT

SCLK

3

VLED

Controller

DATASIN

SCLK

LAT

BLANK

SOUT

VCC

GND

OUT0 - - - - - - - - - - OUT15

TLC59291

GND

GND

IC1

IREF

VCC V

CC

SID read

RIREF

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC59291SLVSA96A –SEPTEMBER 2015–REVISED MARCH 2016

TLC59291 8/16-Channel, Constant Current LED Driver with 7-bit Brightness Control LowQuiescent Current and Full Self Diagnosis for LED Lamp

1

1 Features1• 8/16 Constant-Current Sink Output Channels with

On/Off Control• Current Capability:

– 1 - 40 mA (VCC ≤ 3.6 V)– 1 - 50 mA (VCC > 3.6 V)

• Global Brightness Control: 7-Bit (128 Steps)• Power-Supply Voltage Range: 3 V to 5.5 V• LED Power-Supply Voltage: Up to 10 V• Constant-Current Accuracy:

– Channel-to-Channel = ±3% (Typical)– Device-to-Device = ±2% (Typical)

• Low Quiescent Current• SOUT can be Configured for 8-Channel or 16-

Channel Output• LED Open Detection (LOD)/LED Short Detection

(LSD) with Invisible Detection Mode (IDM)• Output Leakage Detection (OLD) Detects 3 µA

Leak• Pre-Thermal Warning (PTW)• Thermal Shutdown (TSD)• Current Reference Terminal Short Flag (ISF)• Power-Save Mode with 10-µA Consumption• Undervoltage Lockout Sets the Default Data• 2-ns Delayed Switching Between Each Channel

Minimizes Inrush Current• Operating Temperature: –40°C to 85°C

2 Applications• Industry LED Indicator• Illumination• LED Video Display

3 DescriptionThe TLC59291 is a 8/16-channel constant currentsink LED driver. Each channel can be turned on-offby writing data to an internal register. The constantcurrent value of all 16 channels is set by a singleexternal resistor and 128 steps for the globalbrightness control (BC).

The TLC59291 has six type error flags: LED opendetection (LOD), LED short detection (LSD), outputleak detection (OLD), reference terminal shortdetection (ISF), Pre thermal warning (PTW) andthermal error flag (TEF). In addition, the LOD andLSD functions have invisible detection mode (IDM)that can detect those errors even when the output isoff. The error detection results can be read via aserial interface port.

The TLC59291 has low quiescent current in normalmode, it also has a power-save mode that sets thetotal current consumption to 10 uA (typical) when alloutputs are off.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TLC59291 VQFN (24) 4.00mm x 4.00mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Typical Application Circuit (Multiple Daisy Chained TLC59291s)

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 56.5 Electrical Characteristics........................................... 66.6 Switching Characteristics .......................................... 86.7 Timing Diagrams....................................................... 96.8 Typical Characteristics ............................................ 21

7 Parameter Measurement Information ................ 238 Detailed Description ............................................ 24

8.1 Overview ................................................................. 248.2 Functional Block Diagram ....................................... 24

8.3 Feature Description................................................. 258.4 Device Functional Modes........................................ 288.5 Register Maps ......................................................... 31

9 Application and Implementation ........................ 379.1 Application Information............................................ 379.2 Typical Application ................................................. 37

10 Power Supply Recommendations ..................... 3811 Layout................................................................... 39

11.1 Layout Guidelines ................................................. 3911.2 Layout Example .................................................... 39

12 Device and Documentation Support ................. 4012.1 Documentation Support ....................................... 4012.2 Community Resources.......................................... 4012.3 Trademarks ........................................................... 4012.4 Electrostatic Discharge Caution............................ 4012.5 Glossary ................................................................ 40

13 Mechanical, Packaging, and OrderableInformation ........................................................... 40

4 Revision History

Changes from Original (September 2015) to Revision A Page

• Changed Features From: Channel-to-Channel = ±1% (Typical) To: Channel-to-Channel = ±3% (Typical) .......................... 1• Deleted device number TLC5929 From the Electrical Characteristics table.......................................................................... 6• Changed ΔIOL(C0) Test Condition in Electrical Characteristics From: BC = 7Fh, RIREF = 1.6 kΩ To: BC = 0Eh, RIREF =

3.6 kΩ, ................................................................................................................................................................................... 7• Changed the ΔIOL(C1) values in Electrical Characteristics From: TYP = ±2%, MAX = ±4% To TYP = 1% , MAX =

÷3%: ....................................................................................................................................................................................... 7• Deleted device number TLC5929 From the Switching Characteristics table ......................................................................... 8• Changed text From: "with the 1-bit data" To: "with the 16-bit data" in the Function Control Data Writing section ............. 34


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LAT

OUT0

OUT1

OUT2

OUT3

OUT4

BLANK

OUT15

OUT14

OUT13

OUT12

OUT11

1

2

3

4

5

6

18

17

16

15

14

13

Thermal Pad(Bottom Side)

SC

LK

24

OU

T5

7

SIN

23

OU

T6

8

GN

D22

OU

T7

9

VC

C21

OU

T8

10

IRE

F20

OU

T9

11

SO

UT

19

OU

T10

12

3

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5 Pin Configuration and Functions

RGE Package24-Pin VQFN(Top View)

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

BLANK 18 I

BLANK PIN, has two configures:When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:a. When BLANK = Low, SOUT is connected to the bit 7 of the 16-bit shift register, worked as 8ch

device;b. When BLANK = High, SOUT is connected to the bit 15 of the 16-bit shift register, worked as

16ch device;When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;a. When BLANK = Low, all constant current outputs are controlled by the on/off control data in the

data latch.b. When BLANK = High, all OUTx are forced off

GND 22 — Ground

IREF 20 I/O

Maximum current programming terminal.A resistor connected between IREF and GND sets the maximum current for every constant-currentoutput. When this terminal is directly connected to GND, all outputs are forced off. The externalresistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ.

LAT 1 I

Data latch.The rising edge of LAT latches the data from the common shift register into the output on/off datalatch. At the same time, the data in the common shift register are replaced with SID, which isselected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID)section for more details.


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4




Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.OUT0 2 O

Constant-current sink outputs.Multiple outputs can be configured in parallel to increase the constant-current capability. Differentvoltages can be applied to each output.

OUT1 3 OOUT2 4 OOUT3 5 OOUT4 6 OOUT5 7 OOUT6 8 OOUT7 9 OOUT8 10 OOUT9 11 OOUT10 12 OOUT11 13 OOUT12 14 OOUT13 15 OOUT14 16 OOUT15 17 O

SCLK 24 I

Serial data shift clock.Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Datain the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of thecommon shift register appear on SOUT.

SIN 23 I Serial data input for the 16-bit common shift register.When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK.

SOUT 19 O

Serial data output of the 16-bit common shift register.When FC9(BLANK Mode) = 0 and BLANK = LOW;SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK risingedge.In other case:SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK risingedge.

VCC 21 — Power-supply voltage

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to device ground terminal.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

VALUEUNITMIN MAX

Supply voltage, VCC(2) –0.3 6 V

Input voltage SIN, SCLK, LAT, BLANK, IREF –0.3 VCC + 0.3 V

Output voltageSOUT –0.3 VCC + 0.3 VOUT0 to OUT15 –0.3 11 V

Output current (DC) OUT0 to OUT15 65 mAOperating junction temperature, TJ (max) 150 °CStorage temperature, TSTG –55 150 °C


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5




(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

6.3 Recommended Operating ConditionsAt TA= –40°C to 85°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

DC Characteristics: VCC = 3 V to 5.5 V

VCC Supply voltage 3 3.3 5.5 V

VO Voltage applied to output OUT0 to OUT15 10 V

VIH High-level input voltage SIN, SCLK, LAT, BLANK 0.7 × VCC VCC V

VIL Low-level input voltage SIN, SCLK, LAT, BLANK GND 0.3 × VCC V

IOH High-level output current SOUT –2 mA

IOL Low-level output current SOUT 2 mA

IOLC Constant output sink currentOUT0 to OUT15 3 V ≤ VCC ≤ 3.6 V 40 mA

OUT0 to OUT15 3.6 V < VCC ≤ 5.5 V 50 mA

TA Operating free-air temperature range –40 85 °C

TJ Operating junction temperature range –40 125 °C

AC Characteristics: VCC = 3 V to 5.5 V

fCLK (SCLK) Data shift clock frequency SCLK 33 MHz

tWH0

Pulse duration(see Figure 1 and Figure 3)

SCLK 10 ns

tWL0 SCLK 10 ns

tWH1 LAT 20 ns

tWH2 BLANK 40 ns

tWL2 BLANK 40 ns

tSU0 Setup time(see Figure 1, Figure 3 andFigure 4)

SIN to SCLK↑ 5 ns

tSU1 LAT↑ to SCLK↑ 200 ns

tSU2 SCLK ↓to LAT↑ 10 ns

tH0 Hold time(see Figure 1, Figure 3, andFigure 13)

SIN to SCLK↑ 3 ns

tH1 LAT↑ to SCLK↑ 10 ns

tH2 LAT↑ to SCLK ↓ 40 ns

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1)TLC59291

UNITRGE (VQFN)24 PINS

RθJA Junction-to-ambient thermal resistance 38.1

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 45.3RθJB Junction-to-board thermal resistance 16.9ψJT Junction-to-top characterization parameter 0.9ψJB Junction-to-board characterization parameter 16.9RθJC(bot) Junction-to-case (bottom) thermal resistance 6.2


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6




(1) Not tested; specified by design.

6.5 Electrical CharacteristicsAt VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage IOH = –2 mA at SOUT VCC – 0.4 VCC V

VOL Low-level output voltage IOL = 2 mA at SOUT 0.4 V

VLOD LED open detection threshold All OUTn = on 0.25 0.30 0.35 V

VLSD0

LED short detection threshold

All OUTn = on, detection voltage code = 0h 0.32 × VCC 0.35 × VCC 0.38 × VCC V

VLSD1 All OUTn = on, detection voltage code = 1h 0.42 × VCC 0.45 × VCC 0.48 × VCC V



VIREF Reference voltage output RIREF = 1.3 kΩ 1.175 1.205 1.235 V

IIN Input current VIN = VCC or GND at SIN, SCLK, LAT, and BLANK –1 1 μA

ICC0

Supply current (VCC)

SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,VOUTn = 0.8 V, BC = 7Fh, RIREF = open 2 3 mA

ICC1

SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ(IOUT = 18.3 mA target)

5 7 mA

ICC2

SIN/SCLK/LAT/BLANK =Low, All OUTn = on,VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ(IOUT = 18.3 mA target)

5 7 mA

ICC3

SIN/SCLK/LAT/BLANK =Low, All OUTn = on,VOUTn = 0.8 V, BC = 0Eh, RIREF = 1.6 kΩ(IOUT = 2 mA target)

3 4 mA

ICC4

SIN/SCLK/LAT/BLANK = Low, All OUTn = on,VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.6 kΩ(IOUT = 41.3 mA target)

9 11 mA

ICC5

VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,All OUTn = on, VOUTn = 0.8 V, BC = 7Fh,RIREF = 1.3 kΩ (IOUT = 50.8 mA target)

11 14 mA

ICC6

VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.3 kΩ(IOUT = 50.8 mA target), all output data off with power-save mode enabled

10 40 µA

IOL(C0) Constant output sink current(OUT0 to OUT15, seeFigure 28)

All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,RIREF = 1.6 kΩ 38.5 41.3 44.1 mA

IOL(C1)VCC = 5 V, All OUTn = on, VOUTn = VOUTfix = 1 V,BC = 7Fh, RIREF = 1.3 kΩ 47.3 50.8 54.3 mA

IOL(KG0) Output leakage current(OUT0 to OUT15, seeFigure 28)

BLANK = high, VOUTn = VOUTfix =10 V, RIREF = 1.6 kΩ

TJ = 25°C 0.1 μA

IOL(KG1) TJ = 85°C (1) 0.2 μA

IOL(KG2) TJ = 125°C (1) 0.3 0.8 μA


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( ) ( )( )

n n n n

n n

OLC( ) OUT OLC( ) OUT

OLC( ) OUT

I at V 3 V I at V 1 V(%) 100 x

2 x I at V 1 V

æ ö= - =ç ÷D =ç ÷=è ø

( ) ( )( )

OLC(n) CC OLC(n) CC

OLC(n) CC

I at V 5.5 V - I at V 3 V(%) 100 x

2.5 x I at V 3 V

é ù= =ê úD =ê ú=ë û

O(LC _IDEAL)IREF

1.20I 54 x

R

æ ö= ç ÷

è ø

( )OLC(0) OLC(1) OLC(14) OLC(15)I + I +...+ I + I

16(%) 100 x (Ideal Output Current)

Ideal Output Current

é ùé ùê úê úê úê ú

ë ûê úD = -ê úê úê úë û

( )n

+ +...+ +

OLC( )

OLC(0) OLC(1) OLC(14) OLC(15)

I(%) 100 x 1

I I I I

16

é ùê úê úê úD = -ê úé ùê úê úê úê ú

ë ûë û

7




Electrical Characteristics (continued)At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:

.(3) The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the

formula:

Ideal current is calculated by the formula:(4) Line regulation is calculated by the formula:

(5) Load regulation is calculated by the equation:

ΔIO(LC0)

Constant-current error(channel-to-channel, OUT0 toOUT15) (2)

All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 0Eh,RIREF = 3.6 kΩ, TA = 25°C ±3% ±6%

ΔIOL(C1)

Constant-current error(device-to-device, OUT0 toOUT15) (3)

All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,RIREF = 1.6 kΩ, TA = 25°C ±1% ±3%

ΔIOL(C2) Line regulation (4) All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,RIREF = 1.6 kΩ ±0.1 ±1 %/V

ΔIOL(C3) Load regulation (5) All OUTn = on, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,BC = 7Fh, RIREF = 1.6 kΩ ±0.5 ±3 %/V

TTEF Thermal error flag threshold Junction temperature (1) 150 165 180 °C

THYS Thermal error flag hysteresis Junction temperature (1) 5 10 20 °C

TPTW Pre-thermal warning threshold Junction temperature (1) 125 138 150 °C


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8




(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – 40 ns. tOUT_ON is the actual on-time of OUTn.

6.6 Switching CharacteristicsAt VCC = 3 V to 5.5 V, TA = –40°C to 85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1.3 kΩ, and VLED = 5 V.Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITtR0 Rise time

At SOUT 10 15 nstR1 At OUTn, BC = 7Fh 40 60 nstF0 Fall time

At SOUT 10 15 nstF1 At OUTn, BC = 7Fh 40 60 nstD0

Propagation delay

SCLK↑ to SOUT↑↓ 8 22 ns

tD1LAT↑ or BLANK↑↓ to OUT0 sink current on/off,BC = 7Fh 35 65 ns

tD2 OUTn on/off to OUTn + 1 on/off, BC = 7Fh 2 6 ns

tD3LAT↑ to power-save mode by data writing for all outputoff 400 ns

tD4 SCLK↑ to normal mode operation 100 µstD5 BLANK↑↓ to SOUT↑↓ when BLANK MODE=0 100 ns

tON_ERR Output on-time error (1) Output on/off data = all '1',BLANK low pulse = 40 ns, BC = 7Fh –30 20 ns

fOSCInternal oscillatorfrequency 12 20 28 MHz


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t , t , t , t , t , t , t :R0 R1 F0 F1 D0 D1 D2

Input(1) 50%

50%

90%

10%

Output

tD

t or tR F

V or VOL OUTnL

V or VOH OUTnH

VIL

VIH

t , tWH0 WH1, t , t , t :WL0 WH2 WL2

Input(1)

SCLK Input(1)

SIN/LAT Input(1)

t , t , t , tSU0 SU1 H0 H1:

VIH

VIH

VIL

VIH

VIL

VIL

50%

50%

50%

tWH tWL

tSU tH

9




6.7 Timing Diagrams

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 1. Input Timing

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 2. Output Timing


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tD0

SIN

OUTn(1)

ON

OFF

LAT

Output On/OffData Latch

(Internal)

SOUT

SCLK

Shift RegisterLSB Data(Internal)

BLANK

OFF

tWH2

tWH0

tH1

tWH1

13 14 15 161 2 3 4 5 1 2 3 4 5 6

tSU0 tH0

tWL0

t /tR0 F0

tD1tD1

tWL2

Shift RegisterLSB + 1 Data

(Internal)

Shift RegisterMSB Data(Internal)

Shift RegisterMSB - 1 Data

(Internal)

DATA0A

DATA0A

SID0A

DATA15B

DATA14B

DATA13B

DATA12B

DATA3B

DATA2B

DATA1B

DATA15C

DATA14C

DATA13C

DATA12C

DATA11C

Selected SID0B

DATA0B

DATA1A

SID1A

SID0A

DATA15B

DATA14B

DATA13B

DATA4B

DATA3B

DATA2B

SID0B

DATA15C

DATA14C

DATA13C

DATA12C

Selected SID1B

DATA14A

SID14A

SID13A

SID12A

SID11A

SID10A

SID1A

SID0A

DATA15B

SID13B

SID12B

SID11B

SID10B

SID9B

Selected SID14B

DATA15B

DATA14B

DATA13B

DATA12B

DATA11B

DATA3B

DATA2B

DATA1B

DATA0B

DATA15C

DATA14C

DATA13C

DATA12C

DATA11C

DATA10C

DATA15A–0A

tSU1

ControlData Latch

(Internal)Latest DataControl

DATA1B

DATA15B–0B

DATA14B

ON

OUTn(2)

OUTn(3)

OUTn(4)

ON

OFFOFF

ON

ON

OFF

ON

ON

OFFOFF

OFF

tOUTON

tD1

tR1

tF1

OUTn+1(1)

ON

OFF

ON

OFFtD2

tD2

OFF

OFF OFF

ON

tD1

DATA15A

SID14A

SID13A

SID12A

SID11A

SID2A

SID1A

SID0A

SID14B

SID13B

SID12B

SID11B

SID10B

SID15A

SelectedSID

DATA15A

SID15A

SID14A

SID13A

SID12A

SID11A

SID2A

SID1A

DATA0A

SID14B

SID13B

SID12B

SID11B

SID10B

Selected SID15B

DATA15B

DATA15B

OFF

tSU2

10




Timing Diagrams (continued)

(1) On/off latched data is '1'.(2) On/off latched data change from '1' to '0' at second LAT signal.(3) On/off latched data change from '0' to '1' at second LAT signal.(4) On/off latched data is '0'.

Figure 3. Write for ON/Off Data and Output Timing (BLANK Mode = 1)


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tD0

SIN

OUT(1)

ON

OFF

LAT

Output On/OffData Latch

(Internal)

SOUT

SCLK

Shift RegisterLSB Data(Internal)

BLANK

tWH0tH1

tWH1

14 15 161 2 3 1 2 7 8 6

tSU0 tH0

t /tR0 F0

tD1tD1

Shift RegisterLSB + 1 Data

(Internal)

Shift RegisterMSB Data(Internal)

Shift RegisterMSB - 1 Data

(Internal)

DATA0A

DATA0A

DATA15B

DATA14B

DATA2B

DATA1B

DATA0B

DATA7C

DATA1C

DATA0C

DATA15B

DATA14B

DATA13B

DATA2B

DATA1B

DATA0B

DATA7C

DATA6C

DATA1C

DATA0C

DATA15A–0A

ControlData Latch

(Internal)Latest DataControl

DATA15B–0B

ON

OUTn(2)

OUTn(3)

OUTn(4)

ON

OFF

ON

ON

OFF

ON

OFFOFF

OUTn+1(1)

ON

OFF

ON

OFFtD2tD2

OFF

OFF

ON

DATA1A

DATA0A

DATA15B

DATA3B

DATA2B

DATA1B

DATA0B

DATA2C

DATA1C

DATA14A

DATA13A

DATA12A

DATA0A

DATA15B

DATA14B

DATA14B

DATA14B

DATA14B

DATA15A

DATA14A

DATA13A

DATA1A

DATA0A

DATA15B

DATA15B

DATA15B

DATA15B

DATA15A

DATA14A

DATA13A

DATA1A

DATA0A

DATA15B

DATA7B

DATA0B

DATA7C

tD5

DATA6B

tD1

tD1 tD1OFF OFF

tSU2

11





(1) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at second LAT signal.(2) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at second LAT signal.(3) If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at second LAT signal.(4) if the on/off latched data is “0”.

Figure 4. Write for On/Off Data and Output Timing (BLANK Mode = 0)


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tD4tD3

Less Than 100 µA

More Than 100 µA

1

SIN

LAT

SCLK

BLANK

PSMODE Bit inControl Data Latch

(Internal)

On/Off ControlData Latch

(Internal)

OUT0

OUT1

OUT15

Power-SaveMode

ICC(The Current

of VCC)

Low

1 2 3 14 15 16 1 2 3 4 5 6

Don’t Care

Previous On/Off Data All Data are 0

OFF

ON

OFF

ON

OFF

ON

OFF

OFF

OFF

Normal Mode Normal Mode Normal ModePower-Save Mode

12





Figure 5. Power-Save Mode


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T < TJ PTW

T ³ TJ PTW

T ³ TJ TEFT ³ TJ PTW T < T - TJ TEF HYST

PTW is not reset at LAT rising edge because SIDLDdoes not select LOD. PTW is reset to 0 when thedevice junction temperature is less than T and

SIDLD selects LOD.PTW

Device JunctionTemperature (T )J

SCLK

0TEF in SID

(Internal Data) 0

1 1

LAT

1 1

PTW in SID(Internal Data) 0

1

T < TJ PTW

These data are copied to the on/off data latch at LAT rising edge.

Previous On/Off Data New Latched GS DataOutput On/OffData (Internal)

LOD/TEF DataCommon Shift

Register Bits[15:0](Internal)

PTW is set to 1 when devicejunction temperature is greaterthan T .PTW

LowBLANK

High

OUTn

OFF

ON

OFF OFF

ONON

OFF

01 (LOD is selected)SIDLD Data(Internal)

0Common ShiftRegister Bit 16

(Internal)

All outputs are forced offby TSD function.

Resumed with T

going down.J

TEF is set to 1 when device junctiontemperture is grerater than T .TEF

TEF is reset to 0at LAT riging edge foron/off data writing when the device junctiontemperature is less than T and SIDLD

selects LOD.TEF

T ³ TJ TEF

13





Figure 6. PTW/TEF/TSD Timing (LOD Selected)


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Normal Mode

1 2 313 14 15 16

SIN

LAT

Output On/OffControl Data

Latch (Internal)Previous On/Off Data

SCLK

1 2 3 4 5

All Data are 0

Low

Power-SaveMode

Normal mode (No power save mode) Power-Save mode (I = 30 A,(typ))µCCNormal mode

BLANK Don’t Care

PSMODE bitin Control DataLatch (Internal)

1

OFF

ON

OFF

OUT0

OFF

ON

OFF

OUT1

OFF

ON

OFF

OUT15

Depend on output on-off dataWhen PSMODE bit is 0, the device does not intothe power save mode even if output on-off data is all "0".

Because it takes about 50 s return to normalmode, 1'st SCLK rising edge should be input50 s or more before OUTn is turned on.

µ

µ

14





Figure 7. Power-Save Mode Timing


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2/10/20 Aµ

BLANK

OUTn currentfor IDM

17 bit commonshift register data

(Internal)

SID is loaded into the shift registerLatched output on-off data

LAT

Selected on time by IDMTIM bit

in the function control latch.

When BLANK signal is High, all output is

forced off even if the IDM on time has not

been passed the selected time.

High

LODXXXXh

LOD data is not stable just after BLANK goes low.

SID holderdata

(Internal)

16 bit LODcircuit output

data (Internal)

LOD0000h

LOD0000h

LODOld data

LODXXXXh

LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.

0uA

SIDLD in FCdata latch(Internal)

01b

LOD0000h

LODXXXXh

LODXXXXh

0 Aµ

2/10/20 Aµ

LOD data is held in SID holder whileBLANK is high level or the data is held inSID holder when IDM working time haspassed.

OUTn current0mA

Set current by externalresistor and BC data

0mA

Selected output current by “IDMCUR”bit in the function control latch

Programmed output current

Low

(working as enable pin)

for LED lighting

15





Figure 8. IDM Operation Timing with LOD Selected and IDM Enabled


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BLANK

OUTn currentfor IDM

17 bit commonshift register data

(Internal)

SID is loaded into the shift registerLatched on-off control data

LAT

When BLANK signal is “H” , all output isforced off even if the IDM on time has notbeen passed the selected time.

High

LODXXXXh

LOD data is not stable just after BLANK goes low.

SID holderdata

(Internal)

16 bit LODcircuit output

data (Internal)

LOD0000h

LOD0000h

LODOld data

LODXXXXh

LOD data goes through SID holder while BLANK is low level.

0 Aµ


01b

LOD0000h

LODXXXXh

LODXXXXh

0 Aµ

LOD data is held in SID holder whileBLANK is high level.

OUTn currentfor LED lighting 0mA

Set current by externalresistor and BC data

0mA

The output for IDM is not turned on becauseIDM is disabled by “IDMCUR” setting.

Programmed output current

0 Aµ

Low

16





Figure 9. IDM Operation Timing with LOD Selected and IDM Disabled


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DetectorXXXXh

The detectors data are not stable just after BLANK signal goes low.

DATA1A

DATA13C

SID15A

SID0A

SID15B

DATA16C

SID0A

DATA15C

DATA16C

SID0A

SID0A

DATA16B

DATA14B

DATA16B

DATA15B

SID15A

DATA16A

SID0A

0

DATA15C

DATA16C

DATA15B

DATA16B

DATA0A

DATA2B

1 2 3 ---13 14 15 16

SIN

LAT

Output on-offdata latch(Internal)

SOUT

DATA14B

DATA13B

DATA12B

DATA0B

DATA1B

DATA3B

SID14A

SID13A

SID12A

SID2A

SID1A

Old on-off data

SCLK1 2 3 4 5

DATA14C

SID14B

BLANK

DATA16B

DATA0B

DATA0A

DATA2B

DATA14B

DATA13B

DATA1B

DATA3B

Shift registerLSB Data

(Internal)

SID0B

SID0B

DATA1A

DATA3B

DATA15B

DATA2B

DATA4B

Shift registerLSB +1 Data

(Internal)

SID1B

SID14B

DATA15A

SID14A

DATA13A

DATA12A

DATA11A

SID1A

SID13B

Shift registerMSB -1 Data

(Internal)

SID15B

SID15B

SID1A

SID14A

SID13A

SID12A

SID2A

SID14B

Shift registerMSB Data(Internal)

DATA16B


SID1A

SID15A

DATA1B

DATA15B

Low

0

DATA16B

DATA16A

0

0

0

High

1

Low Low

1

14 15 16

DATA1A

DATA2A

DATA2A

DATA3A

DATA16A

DATA0

DATA0

DATA1

DATA0

DATA1

SID holderdata

(Internal)

XXb

16 bit LOD orLSD or OLD

data (Internal)

Detector data0000h

Detector data0000h

Detector dataXXXXh

Detector dataXXXXh

Detector dataXXXXh

Selected detector data by SIDLD is held in SID holder while BLANK is high level. Or the data is held in SID holder when IDMworking time is passed. The held data is loaded into the common shift register as SID except the case SIDLD is 00h.

LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.

16 bit SID data

LOD data is selected when SIDLD is 01h. LSD data is selected when SIDLD is set to10b. OLDdata is selected when SID is set to 11b. No SID data is loaded when SIDLDis 00h.

DATA15A-0A

SID data selected by SIDLD bit is loaded into the commonshift register at LAT rising edge except SIDLD is 00b.

17





Figure 10. SID Read Timing


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SID15A

SID0A

SID15B

DATA15C

DATA16C

SID0A

DATA15C

DATA16C

SID0A

SID0A

DATA16B

DATA14B

DATA16B

DATA15B

SID15A

DATA16A

SID0A

0

DATA14C

DATA15C

DATA14B

DATA15B

DATA10C

DATA0A

DATA2B

1 2 3 4 5 613 14 15 16

SIN

LAT

Output on-off

data latch

(Internal)

SOUT

DATA13B

DATA12B

DATA11B

DATA0B

DATA1B

DATA3B

SID14A

SID13A

SID12A

SID2A

SID1A

DATA15B-0B

SCLK

1 2 3 4 5

DATA13C

DATA12C

DATA11C

SID14B

SID13B

SID12B

SID11B

BLANK

DATA16B

DATA0B

DATA0A

DATA2B

DATA14B

DATA13B

DATA1B

DATA3B

DATA14C

DATA13C

DATA12C

Shift register

SID0B

SID0B

DATA1A

DATA3B

DATA15B

DATA2B

DATA4B

DATA14C

DATA13C

Shift register

LSB +1Data

(Internal)

SID1B

SID14B

DATA15A

SID14A

DATA13A

DATA12A

DATA11A

SID1A

SID13B

SID12B

SID11B

SID10B

Shift register

MSB -1Data(Internal)

SID15B

SID15B

SID1A

SID14A

SID13A

SID12A

SID2A

SID14B

SID13B

SID12B

SID11B

Shift register

MSB Data

(Internal)

DATA16B

Control dataLatch Control data is not changed from previous data

SID1A

SID15A

DATA1B

DATA15B

0

DATA16B

DATA16A

0

0

0

1

Low Low

1

OFF

ONON

OFFOFF

ON

ON

OFFOFF

ON

ON

OFF

ON

OFF

ON

OFFOFF

OFF

ON

OFF

These dotted lines are output pulse timing for IDM

DATA15A-0A

OUTn(1)

OUTn(2)

OUTn(3)

OUTn(4)

(Internal)

LSB Data

(Internal)

18





(1) On/off latch data is '1'.(2) On/off latch data change from '1' to '0' at second LAT signal.(3) On/off latch data is change from '0' to '1' at second LAT signal.(4) On/off latch data is '0'.

Figure 11. On-Off Control Data Write Timing (BLANK Mode = 1)


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OFF

ON

DATA6C

DATA7C

DATA14B

DATA15B

DATA0A

DATA2B

1 2 7 814 15 16

OFF

DATA13B

DATA0B

DATA1B

DATA13A

DATA14A

1 2 3

DATA1C

DATA0C

DATA6B

DATA0B

DATA7C

ON

ON

OFF

ON

ON

OFF

OFF

ON

OFFOFFOFF

OFF

Latest control data

ON

ON

OFF

ON

OFF

DATA15A-0A DATA15B-0B

DATA15A

DATA0A

DATA7C

DATA1B

DATA15B

DATA14B

DATA2B

DATA1C

DATA1A

DATA0B

DATA2B

DATA0A

DATA15B

DATA3B

DATA2C

DATA14A

DATA14B

DATA15B

DATA13A

DATA12A

DATA0A

DATA14B

15DATA15B

DATA0A

DATA14A

DATA13A 15

DATA1A

DATA15B 15B

DATA 7C-0C

DATA1A

DATA0A

DATA15B

DATA7B

SIN

LAT

Output on-off

data latch

(Internal)

SOUT

SCLK

BLANK

Shift register

Shift register

LSB +1Data

(Internal)

Shift register

MSB -1Data(Internal)

Shift register

MSB Data

(Internal)

Control dataLatch

(Internal)

LSB Data

(Internal)

OUTn(1)

OUTn(2)

OUTn(3)

OUTn(4)

OUTn+1(1)

DATA0C

DATA1C

DATA14B

DATADATAA

DATA0B

DATA1B

DATA

DATAB

14B

19





(1) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at 2’nd LAT signal.(2) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at 2’nd LAT signal.(3) If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at 2’nd LAT signal.(4) If the on/off latched data is “0”.

Figure 12. On-Off Control Data Write Timing (BLANK Mode = 0)


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DATA15C

DATA16C

DATA15C

DATA16C

DATA16B

SID0A

DATA16B

DATA15B

DATA15B

DATA16B

SID0A

SID15A

SID0A

DATA15B

SID15A

DATA15C

DATA15B

DATA16A

DATA16A

DATA14C

DATA14B

DATA10C

DATA0A

DATA2B

1 2 3 4 5 613 14 15 16

SIN

LAT

Output Oo-offdata

(Internal)

SOUT

DATA13B

DATA12B

DATA11B

DATA0B

DATA1B

DATA3B

SID14A

SID13A

SID12A

SID2A

SID1A

Old function control data

SCLK

1 2 3 4 5

DATA13C

DATA12C

DATA11C

DATA14B

DATA13B

DATA12B

DATA11B

DATA16B

DATA0A

DATA2B

DATA14B

DATA13B

DATA1B

DATA3B

DATA14C

DATA13C

DATA12C

Shift registerLSB Data(Internal)

DATA0B

DATA0B

DATA1A

DATA3B

DATA14B

DATA2B

DATA4B

DATA14C

DATA13C

Shift registerLSB +1 Data

(Internal)

DATA1B

DATA14B

DATA15A

SID0A

SID14A

DATA13A

DATA12A

DATA11A

SID1A

DATA13B

DATA12B

DATA11B

DATA10B

Shift registerMSB -1 Data

(Internal)

DATA15B

DATA15B

SID1A

SID14A

SID13A

SID12A

SID2A

DATA14B

DATA13B

DATA12B

DATA11B

Shift registerMSB Data

(Internal)

DATA16B

Function controlLatch Data

(Internal)

DATA15B-0B

Low

0

High

1

1

1

1

0

0

DATA15A-0A DATA15A-0A

SID0A

SID1A

SID15A

tH2

20





Figure 13. Function Control Data Write Timing


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Output Voltage (V)

1.50 3.0

56

55

54

53

52

51

50

49

48

Ou

tpu

t C

urr

en

t (m

A)

0.5 1.0 2.0 2.5

T = -40 C

T = +25 C

T = +85 C

A

A

A

°

°

°

Output Current (mA)

200 50

3

2

1

0

-1

2

3

-

-

ΔI

(%)

OL

C

10 30 40

V = 3.3 V

V = 5 VCC

CC

Output Voltage (V)

1.50 3.0

46

45

44

43

42

41

40

39

38

Ou

tpu

t C

urr

en

t (m

A)

0.5 1.0 2.0 2.5

T = -40 C

T = +25 C

T = +85 C

A

A

A

°

°

°

Output Voltage (V)

1.50 3.0

60

50

40

30

20

10

0

Ou

tpu

t C

urr

en

t (m

A)

0.5 1.0 2.0 2.5

I = 40 mAOLCMax

I = 30 mAOLCMax

I = 20 mAOLCMax

I = 10 mAOLCMax

I = 5 mAOLCMax

I = 50 mAOLCMax

I = 2 mAOLCMax

I = 1 mAOLCMax

I (V)OLCMax

0 50

100

10

1

R(k

)Ω

IRE

F

10 20 30 40

2.64

13.2

33.0

1.32

1.47

66.0

6.60

4.403.30

2.201.89

1.65

Output Voltage (V)

1.50 3.0

60

50

40

30

20

10

0

Ou

tpu

t C

urr

en

t (m

A)

0.5 1.0 2.0 2.5

I = 40 mAOLCMax

I = 30 mAOLCMax

I = 20 mAOLCMax

I = 10 mAOLCMaxI = 2 mAOLCMax

I = 1 mAOLCMax I = 5 mAOLCMax

21




6.8 Typical CharacteristicsAt TA = 25°C, unless otherwise noted.

Figure 14. Reference Resistor vs Output Current

VCC = 3.3 V BC = 7Fh VOUTn = 0.8 V

Figure 15. OUTn Current vs Output Voltage

VCC = 3.3 V BC = 7Fh RIREF = 1.58 kΩVOUTn = 0.8 V


VCC = 5 V BC = 7Fh VOUTn = 0.8 V50 mA = 1 V


VCC = 5 V BC = 7Fh RIREF = 1.28 kΩVOUTn = 1 V


BC = 7Fh VOUTn = 0.8 V 50 mA = 1 V

Figure 19. Constant-Current Errorvs Output CurrenT set by RIREF or BC Data (Channel-to-

Channel)


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Ambient Temperature ( C)°

0-40 100

30

25

20

15

10

5

0

-20 20 80

V = 3.3 V

V = 5 VCC

CC

40 60

I(

A)

CC

µ

CH1-BLANK

CH2-OUT0

CH3-OUT1

CH4-OUT15

Time (20 ns/div)

CH1 (5 V/div)

CH2 (2 V/div)

CH3 (2 V/div)

CH4 (2 V/div)

Output Current (mA)

300 50

16

14

12

10

8

6

4

2

0

I(m

A)

CC

10 20 40

V = 3.3 V

V = 5 VCC

CC

Ambient Temperature (°C)

0-40 100

14

12

10

8

6

4

2

0

I(m

A)

CC

-20 20 80

V = 3.3 V

V = 5 VCC

CC

40 60

Temperature (°C)

0-40 100

3

2

1

0

-1

2

3

-

-

ΔI

(%)

OLC

-20 20 80

V = 3.3 V

V = 5 VCC

CC

40 60

BC Data (Decimal)

1120 128

60

50

40

30

20

10

0

Outp

ut C

urr

ent (m

A)

32 6448

V = 3.3 V

V = 5 VCC

CC

16 9680

I = 2 mAO

I = 5 mAO

I = 10 mAO

I = 20 mAO

I = 40 mAO

I = 50 mAO

22




Typical Characteristics (continued)At TA = 25°C, unless otherwise noted.

RIREF = 1.28 kΩ VOUTn = 0.8 V

Figure 20. Constant-Current Errorvs Ambient Temperature (Channel-to-Channel)

Figure 21. Global BrightnessControl Linearity

BC = 7Fh RIREF = 1.6 kΩ SIN = 17.5 MHzSCLK = 35 MHz All Outpts on

Figure 22. Supply Currentvs Output Current Set by RIREF

BC = 7Fh RIREF = 1.6 kΩ SIN = 17.5 MHzSCLK = 35 MHz All Outpts on

Figure 23. Supply Currentvs Ambient Temperature

BC = 7Fh RIREF = 1.6 kΩ SIN = SCLK = LowPower-Save Mode

Figure 24. Supply Current in Power-Save Modevs Ambient Temperature

VCC = 3.3 V BC = 7Fh RIREF = 1.6 kΩVLED = 5 V RL = 100 Ω CL = 15 pF

Figure 25. Constant-Current OutputVoltage Waveform


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¼¼

VCC

RIREF

VOUTfix

VOUTn

OUT0VCC

OUTn

OUT15GND

IREF

VCC

VCC

GND

SOUT

CL

(1)

VCC

VCC

GND

IREF OUTn

RIREF

RL

CL

(1)VLED

23




7 Parameter Measurement Information

(1) CL includes measurement probe and jig capacitance.

Figure 26. Rise Time and Fall Time Test Circuit for OUTn

(1) CL includes measurement probe and jig capacitance.

Figure 27. Rise Time and Fall Time Test Circuit for SOUT

Figure 28. Constant-Current Test Circuit for OUTn


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RESET

IDM timingcontrol

ERRORSELECT

TempError

Status

Powersave

control

Control data latch(Global brightness control, LSD voltage select,

loaded error select, other function control)

16

1616

MSB

VCC

SIN

BLANK

IREF

Common shift register

Output On-Off data Latch

OUT0

VCC

Referencecurrentcontrol 16channels constant current sink driver

with 7bit global brightness control

LED Open Detection (LOD) / LED Short Detection (LSD)/Output Leak Detection (OLD)

OUT1

7

16

GND

GND

LSB

LSB MSB

0

0 15

LSB MSB

0 15

ThermalDetector

SCLK

LAT

SIDSelector

16

SOUT

OUT2

16

DetectionVoltage

OUT13 OUT15

3

OUT14

165C

138C

UVLO

On-Off control with output delay

OSC

To allanalog

circuit

All off

2

ISF

ISF

4

2

2

VLSD

SELECT

BC

ERRORSELECT

LOADSELECT

2

SIDHolder

16

RESET

1

2

1

15

BlankMode

Bit 7/15Select

16 bit LOD or 16 bit LSD data or 16 bit OLD data

24




8 Detailed Description

8.1 OverviewThe TLC59291 is a 8/16-channel constant current sink LED driver. Each channel can be turned on-off by writingdata to an internal register. The constant current value of all 16 channels is set by a single external resistor and128 steps for the global brightness control (BC).

The TLC59291 has six type error flags: LED open detection (LOD), LED short detection (LSD), output leakdetection (OLD), reference terminal short detection (ISF), Pre thermal warning (PTW) and thermal error flag(TEF). In addition, the LOD and LSD functions have invisible detection mode (IDM) that can detect those errorseven when the output is off. The error detection results can be read via a serial interface port.

8.2 Functional Block Diagram


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IREFIREF

O(CLmax)

V (V)R (K ) x 54.8

I (mA)W =

25




8.3 Feature Description

8.3.1 Maximum Constant Sink CurrentThe maximum output current of each channel (IO(LCmax)) is programmed by a single resistor (RIREF) that is placedbetween the IREF and GND pins. The current value can be calculated by Equation 1:

Where:VIREF = the internal reference voltage on IREF (typically 1.205 V when the global brightness controldata are at maximum.IO(LCmax) = 1 mA to 40 mA ( VCC ≤ 3.6 V), or 1 mA to 50 mA (VCC > 3.6 V) at OUT0 to OUT15 (BC =7Fh) (1)

IO(LCmax) is the highest current for each output. Each output sinks IO(LCmax) current when it is turned on with themaximum global brightness control (BC) data. Each output sink current can be reduced by lowering the globalbrightness control value. RIREF must be between 1.32 kΩ and 66 kΩ to hold IO(LCmax) between 50 mA (typical) and1 mA (typical). Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved bysetting IO(LCmax) to 1 mA or higher and then using the global brightness control to lower the output current.

Figure 14 and Table 1 show the characteristics of the constant-current sink versus the external resistor, RIREF.

Table 1. Maximum Constant Current Output versusExternal Resistor Value

IO(LCmax) (mA) RIREF (kΩ, typ)50 (VCC > 3.6 V only) 1.3245 (VCC > 3.6 V only) 1.47

40 1.6535 1.8930 2.2025 2.6420 3.3015 4.4010 6.605 13.22 331 66


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O(LCmax)O(LCn)

I (mA) x BCI (mA)

127d=

26




8.3.2 Global Brightness Control (BC) FunctionThe TLC59291 has the ability to adjust the output current of all constant current outputs simultaneously. Thisfunction is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) can be set witha 7-bit word. The global BC adjusts all output currents in 128 steps from 0% to 100%. where 100% correspondsto the maximum output current set by RIREF. Equation 2 calculates the actual output current. BC data can be setvia the serial interface.

Where:IO(LCmax) = the maximum constant-current value for each output determined by RIREF.BC = the global brightness control value in the control data latch (0h to 127d) (2)

Table 2 shows the BC data versus the constant-current ratio against IO(LCmax).

Table 2. BC Data versus Constant-Current Ratio Against IO(LCmax)

BC DATA RATIO OF OUTPUTCURRENT TO IO(LCmax)

(%)

IO(LC)(mA, IO(LCmax)= 40mA,

typ)IO(LC)

(mA, IO(LCmax)= 1mA, typ)BINARY DECIMAL HEX000 0000 0 00 0 0 0000 0001 1 01 0.8 0.31 0.01000 0010 2 02 1.6 0.63 0.02

∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙111 1101 125 7D 98.4 39.4 0.98111 1110 126 7E 99.2 39.7 0.99111 1111 127 7F 100.0 40.0 1.00

8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)The thermal shutdown (TSD) function turns off all constant-current outputs when the junction temperature (TJ)exceeds the threshold (TTEF = 165°C, typical) and sets all LOD data bit to ‘1’. When the junction temperaturedrops below (TTEF – THYST), the output control starts. The TEF is remains ‘1’ until LAT is input even if lowtemperature. Figure 6 shows a timing diagram and Table 3 shows a truth table for TEF.

8.3.4 Pre-Thermal Warning (PTW)The PTW function indicates that the IC junction temperature is high. The PTW is set and all LSD data bit are setto “1” while the IC junction temperature exceeds the temperature threshold (TPTW = 138 °C, typical). Then OUTnare not forced off. When the PTW is set, the IC temperature should be reduced by lowering the power dissipatedin the driver to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished bylowering the values of the BC data. When the IC junction temperature decreases below the temperature of TPTW,PTW is reset. Figure 6 shows a timing diagram and Table 3 shows a truth table for PTW.


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27




8.3.5 Current Reference Terminal – IREF Terminal - Short Flag (ISF)The ISF function indicates that IREF terminal is short to GND with low impedance. When IREF is set, all OLDdata bit is set to “1”. Then all outputs (OUTn) are forced off and remain off until the short is removed. Table 3shows the truth table for ISF.

Table 3. TEF/PTW/ISF Truth Table

TEF PTW ISFCORRESPONDING DATA BITS

IN SIDDevice temperature is lower than

high-side detect temperature(temperature ≤ TTEF)

Device temperature is lower thanpre-thermal warning temperature

(temperature ≤ TPTW)IREF terminal is not shorted Depends on LOD/LSD/OLD

Device temperature is higherthan high-side detect

temperature and all outputs areforced off (temperature >TTEF)

Device temperature is higherthan pre-thermal warning

temperature(temperature > TPTW)

IREF terminal is shorted to GNDwith low impedance and all

outputs (OUT0 to OUT15) areforced off

SID is all 1s for TEF when SIDLDbit = '01'. SID is all 1s for PTW

when SIDLD = '10'. SID is all 1sfor ISF when SIDLD = '11'.

8.3.6 Noise ReductionLarge surge currents may flow through the IC and the board on which the device is mounted if all 16 outputs turnon simultaneously when BLANK goes low or on-off data changes at LAT rising edge with BLANK low. Theselarge current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits.The TLC59291 turns the outputs on in 2ns series delay for each output to provide a circuit soft-start feature.


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8.4 Device Functional Modes

8.4.1 Blank Mode Selection (BLKMS)The device has two configuration for BLANK pin, which is decided by BIT[9] in FC register. When BLANK mode= 1, the device is in ENABLE mode, BLANK pin is worked as OUTPUT enable pin: when BLANK=Low, allconstant current outputs are controlled by the on/off control data in the data latch; when BLANK=High, all OUTxare forced off.

When BLANK mode = 0, the device is in SOUT mode, BLANK pin is worked as SOUT select pin; when BLANK=Low, SOUT is connected to the bit7 of the 16-bit shift register, worked as 8 channel device; when BLANK= High,SOUT is connected to the bit15 of the 16-bit shift register, worked as 16ch device. If device is already inENABLE mode and we want to switch to SOUT mode, the new FC data with BIT[9]=0 must be input. Then itenter SOUT mode.

If device is already in SOUT mode and the user wants to switch to ENABLE mode. First make sure BLANK pin ishigh, SOUT is connected with bit15 of common shift register. Then input the new FC data with BIT[9] = 1. Thedevice enters ENABLE mode

When the IC is powered on, SOUT mode is selected as default value. Refer to table 7 for detail.

8.4.2 Power-Save ModeIn this mode, the device dissipation current becomes 30 µA (typical). When “PSMODE” bit is ‘1’, the power savemode is enabled. Then if LAT rising edge is input to write all ‘0’ data into the output on-off data latch or to writeany data into the control data latch when the on-off data latch are all ‘0’, TLC5929 goes into the power savemode. When SCLK rising edge is input, the device returns to normal operation. The power-save mode timing isshown in Figure 7.

8.4.3 LED Open Detection (LOD)LOD detects the fault caused by LED open circuit or a short from OUTn to ground by comparing the OUTnvoltage to the LOD detection threshold voltage level (VLOD = 0.3 V typical). If the OUTn voltage is lower thanVLOD, that output LOD bit is set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data areonly valid for outputs programmed to be on. LOD data for outputs programmed to be off are always '0' (Table11).

The LOD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is setto ‘01b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LOD data are stored to SID holder atthe end timing of IDM working time.

The stored LOD data can be read out through the common shift register as Status Information Data (SID) fromSOUT pin. LOD/LSD data are not valid until 0.5 µs after the falling edge of BLANK.

8.4.4 LED Short Detection (LSD)LSD data detects the fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection If theOUTn voltage is higher than the programmed voltage, that output LSD bit is set to '1' to indicate a shorted LED.Otherwise, the LSD bit is set to'0'. LSD data are only valid for outputs programmed to be on. LSD data foroutputs programmed to be off are always '0' (Table 4).

The LSD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set to‘10b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LSD data are stored to SID holder at theend timing of IDM working time. The stored LSD data can be read out through the common shift register asStatus Information Data (SID) from SOUT pin. LOD/LSD data are not stabled until 0.5 µs after the falling edge ofBLANK. Therefore, BLANK must be low for at least that time.

The LSD need to be executed after propagation delay, “td4” or more from the device operation resumed from thepower save mode because LOD does not work during the power save mode.


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VLSD

VLOD

OLD

Control2 A (typ)m

VCC VLED

On/Off

ControlUp to

50 mA

IDM

Control

2 A/10 A/20 A

(typ)

m m m

LED Lamp

OUTn

GND

LSD/OLD Data

‘1’ = Error

LOD Data

‘1’ = Error

29




Device Functional Modes (continued)8.4.5 Invisible Detection Mode (IDM)Invisible Detection Mode (IDM) is the mode which can detect LOD and LSD when output on-off data is set to offstate. When “IDMCUR” bit in the control data latch are set any data except “00b”, OUTn start to sink the currentset by the “IDMCUR” bit at BLANK falling edge and OUTn stop to sink the current at BLANK rising signal or thetime set by “IDMTIM” has passed. When OUTn is stopped, the selected SID data by “SIDLD” bit are latched tointo SID holder.

When IDM mode is enabled, OLD is always set to disable. When “IDMCUR” bit in the control data latch is set“00b”, OUTn doesn’t start to sink the current set. Figure 29 shows LOD/LSD/OLD/IDM circuit. Figure 8 showsIDM operation timing and Table 5 shows a truth table for LOD/LSD/OLD.

IDM can only be working when FC[9] = 1.

8.4.6 Output Leakage Detection (OLD)Output leak detection (OLD) detects a fault caused by OUTn is short to GND with high resistance by comparingthe OUTn voltage to the LSD detection threshold voltage when output on-off data is set to off state. Also OLDcan detect the short between adjacent pins. Small current is sourced from OUTn turned off to LED to detect LEDleaking when “SIDLD” bit are ‘11b’ and BLANK is low. OLD operation is disabled when SIDLD bit are set anydata except “11b” and then the sourced current is stopped. Also OLD is disabled when Invisible Detection Mode(IDM) is enabled. If the OUTn voltage is lower than the programmed LSD threshold voltage, that output OLD bitis set to '1' to indicate a leaking LED. Otherwise, the OLD bit is set to '0'. OLD result is valid for outputsprogrammed to off only. The OLD data is latched into SID holder when BLANK goes high. OLD data for outputsnot programmed to off are always '0'. The OLD need to be executed after propagation delay, “td4” or more fromthe device operation resumed from the power save mode because OLD does not work during the power savemode.

Figure 29. LOD/LSD/OLD/IDM Circuit

8.4.7 Status Information Data (SID)The status information data (SID) contains the status of the LED Open Detection (LOD), LED Short Detection(LSD), Output Leakage Detection (OLD), Pre-Thermal Warning (PTW), Thermal Shutdown (TSD) and ThermalError Flag (TEF) and Current Reference Terminal – IREF Terminal - Short Flag (ISF). The loaded SID data canbe selected by “SIDLD” bits in the control data latch. When the MSB of the common shift register is set to '0', theselected SID overwrites lower 16-bit data in the common shift register data at the rising edge of LAT after thedata in the common shift register are copied to the output on-off data latch. If the common shift register MSB is'1', the selected SID does not overwrite the 16-bit data in the common shift register


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LSBMSB

012341112131415

SelectedSID forOUT15





SelectedSID forOUT4

SelectedSID forOUT3

SelectedSID forOUT2

SelectedSID forOUT1

SelectedSID forOUT0

SOUTSLCK

SIN

LSBMSB = ‘0’

01234111213141516

LatchSelect

Bit

CommonData Bit

15

CommonData Bit

14

CommonData Bit

13

CommonData Bit

12

CommonData Bit

11

CommonData Bit

4

CommonData Bit

3

CommonData Bit

2

CommonData Bit

1

CommonData Bit

0

Common Shift Register (17 Bits)

SID are loaded to thecommon shift registerat the rising edge ofLAT when the commonshift register MSB is 0.

No data are loadedinto the MSB of thecommon shift register

Selected SID (16 bits) by SIDLD Data in the Control Data Latch

30




Device Functional Modes (continued)After being copied into the common shift register, new SID data are not available until new data are written intothe common shift register. If new data are not written, the LAT signal is ignored. To recheck SID withoutchanging the on-off control data, reprogram the common shift register with the same data currently programmedinto the on-off data latch. When LAT goes high, the output on-off data is not changed, but new SID data areloaded into the common shift register. LOD, LSD, OLD, PTW, TEF, ISF are shifted out of SOUT with each risingedge of SCLK. The SID need to be read out after td4 or more from the device operation resumed from the powersave mode.

The SID reading must be delayed for a duration of tD4 or more after the device resumes operation from thepower-save mode because SID does not indicate correct data during the power-save mode. The SID loadconfiguration and SID read timing are shown in Figure 10 and Figure 30, respectively.

Figure 30. SID Load Configuration

Table 4. SID Load Assignment

SIDLD1/0 BIT

SELECTEDDETECTOR CHECKED OUTn

BIT NUMBERLOADED INTO

COMMON SHIFTREGISTER

DESCRIPTION

00b No detector selected — No data loadedThe data in the common shift register are not changed.The data in the common shift register are updated with LOD or TEF data.All bits '1' = device junction temperature (TJ) is high (TJ > TTEF) and alloutputs are forced off by the thermal shutdown function.'1 = OUTn showslower voltage than the LED open detection threshold (VLOD).0 = normal operation.

01b LED open detection(LOD)

OUT0 0

OUT1 1

∙ ∙ ∙ ∙ ∙ ∙

OUT14 14

OUT15 15

10b LED short detection(LSD)

OUT0 0The data in the common shift register are updated with LSD or PTW data.All bits '1' = device junction temperature (TJ) is high (TJ > TPTW).1 = OUTn shows higher voltage than the LED short detection threshold(VLSD) selected by LSDVLT.0 = normal operation.

OUT1 1

∙ ∙ ∙ ∙ ∙ ∙

OUT14 14

OUT15 15

11b Output leakagedetection (OLD)

OUT0 0The data in the common shift register are updated with OLD or ISF data.All bits '1' = IREF pin is shorted to GND with low impedance.1 = OUTn is leaking to GND with greater than 3µA.0 = normal operation.

OUT1 1

∙ ∙ ∙ ∙ ∙ ∙

OUT14 14

OUT15 15


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16 bit

16 bit

SOUTCommonData bit

11 SCLK

SIN

To output on-off control circuit

Common shift register (16 bits)

LSB

CommonData bit

0

CommonData bit

1

CommonData bit

2

MSB

CommonData bit

14

CommonData bit

15

16 bit

CommonData bit

13

CommonData bit

12

CommonData bit

4

CommonData bit

3

Output on - off data latch (16 bits)

012341112131415 ---

LSB

0MSB

OUTON

0

0

12341112131415 ---

OUTON

1

OUTON2

OUTON

3OUTON

4

OUTON11

OUTON12

OUTON13

OUTON14

OUTON

15

To output constant currentcontrol circuit

To powersave mode

controlcircuit

To IDMworking time

controlcircuit

7 bit

To LSDcircuit

2 bit

To SIDdata load

controlcircuit

2 bit2 bit1 bit

To IDMcurrentcontrolcircuit

2 bit

SID 16 bit

MSB681112131415

Brightnesscontrol(BC) 6

SID loadcontrol

1

IDMworking

time 1

Powersave

enable

IDMworkingtime 0

IDMcurrent

select 1

IDMcurrent

select 0

---910

LSDdetect

voltage1

LSDdetect

voltage0

SID loadcontrol

0

7

Brightnesscontrol(BC) 0

LSB

0

The latch pulsecomes from LATpin when SCLKsignal = 0.

The latch pulsecomes from LATpin when SCLKsignal = 1.

Control data latch (16 bits)

31




Table 5. LOD/LSD/OLD Truth TableLOD LSD OLD CORRESPONDING BIT IN SID

LED is not opened(VOUTn > VLOD) LED is not shorted (VOUTn ≤ VLSD)

OUTn does not leak to GND (VOUTn >VLSD when constant-current output off

and OUTn source current on)0

LED is open or shorted to GND(VOUTn ≤ VLOD)

LED is shorted between anode andcathode, or shorted to higher voltage

side (VOUTn > VLSD)

Current leaks from OUTn to internalGND, or OUTn is shorted to externalGND with high impedance (VOUTn ≤

VLSD when constant-current output offand OUTn source current on)

1

8.5 Register Maps

8.5.1 Register and Data Latch ConfigurationThe TLC59291 has one common shift register and two control data latch. The common shift register is 16-bits inlength and two control data latch is 16-bits length. When SCLK is '0' at LAT rising edge, the 16-bits common shiftregister are copied into the output on-off data latch. Also when SCLK is '1' at LAT rising edge the 16-bits data arecopied into the control data latch. Figure 31 shows the common shift register and two control data latchesconfiguration.

Figure 31. Common Shift Register and Control Data Latches Configuration


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OUTON4

16 bit

From common shift register

LSB

0MSB

OUTON

0

12341112131415 ---

OUTON

1

OUTON

2OUTON

3

OUTON11

OUTON12

OUTON13

OUTON14

OUTON

15

16 bit

To output on off control circuit

Output on-off data latch (16 bits)

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Register Maps (continued)8.5.1.1 Common Shift RegisterThe 16-bit common shift register is used to shift data from the SIN pin into the TLC59291. The data shifted intothe register are used for the data writing for output on-off control, global brightness control, and some functionscontrol. The register LSB is connected to SIN. On each SCLK rising edge, the data on SIN are shifted into theregister LSB and all bits are shifted towards the MSB.

SOUT can be connected to either bit 15 or bit 7 of common shift register depending on BLANK signal and controldata setting.

Also Status Information Data (SID) selected by the load select data in the control data latch are loaded to thecommon shift register when LAT rising edge is input with SCLK is “0” of the shift register.

When the device powered up, the data in the 16-bit common shift register is set to all “0”.

8.5.1.2 Output On/Off Data LatchThe output on/off data latch is 16 bits long and sets the on or off status for each constant-current output.

When FC[9] = 1 and BLANK is high, all outputs are forced off. But then the data in the latch are not changed. Inother case, the corresponding output is turned on if the data in the output on-off data latch are '1' and remains offif the data are '0'.

When the IC is initially powered on, the data in the data latch is set to all “0”.

The output on/off data latch configuration is shown in Figure 32 and the data bit assignment is shown in Table 6.

Figure 32. Output On/Off Data Latch Configuration

Table 6. On/Off Control Data Latch Bit AssignmentBIT NUMBER BIT NAME CONTROLLED CHANNEL

0 OUTON0 OUT01 OUTON1 OUT12 OUTON2 OUT2∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙ ∙13 OUTON13 OUT1314 OUTON14 OUT1415 OUTON15 OUT15


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From common shift register

16 bitControl data latch (16bits)

LSB

0MSB

681112131415

Brightnesscontrol

(BC) 6

SID loadcontrol

1

IDMworking

time 1

Powersave

enable

IDMworking

time 0

IDMcurrentselect 1

IDMcurrentselect 0

---910

BLANKMode

Select1

BLANKMode

Select0

SID loadcontrol

0

7

Brightnesscontrol

(BC) 0

To output constant currentcontrol circuit

To powersave mode

controlcircuit

To IDMworking

time controlcircuit

7 bit

To BLANKModeselectcircuit

2 bit

To SIDdata load

controlcircuit

2 bit2 bit1 bit

To IDMcurrentcontrolcircuit

2 bit

33




Figure 33. Output On/Off Data Latch

15 14 13 12 11 10 9 80 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 00 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/WLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Output On/Off Data LatchBit Field Type Reset Description[15] OUTON15 R/W 00

When IC is powered up, these all data are set to “0”0 = output OFF (default)1 = output ON

[14] OUTON14 R/W 00[13] OUTON13 R/W 00[12] OUTON12 R/W 00[11] OUTON11 R/W 00[10] OUTON10 R/W 00[9] OUTON9 R/W 00[8] OUTON8 R/W 00[7] OUTON7 R/W 00[6] OUTON6 R/W 00[5] OUTON5 R/W 00[4] OUTON4 R/W 00[3] OUTON3 R/W 00[2] OUTON2 R/W 00[1] OUTON1 R/W 00[0] OUTON0 R/W 00

8.5.1.3 Control Data LatchThe control data latch is 16-bit in length and contains the Global Brightness Control (BC) Function data, StatusInformation Data (SID) load select data, Blank Mode Selection (BLKMS) data, the current value for InvisibleDetection Mode (IDM), IDM working time, and Power-Save Mode enable control data.

When the device is powered up, the data in this data latch are set to the default values shown in Table 8.

The function control data latch configuration is shown in Figure 34.

Figure 34. Function Control Data Latch Configuration


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34




Figure 35. Control Data Latch

15 14 13 12 11 10 9 81 0 0 0 0 1 0 0

R/W R/W R/W R/W R/W R/W R/W R/W

7 6 5 4 3 2 1 00 1 1 1 1 1 1 1

R/W R/W R/W R/W R/W R/W R/W R/WLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Control Data LatchBit Field Type Reset Description[15] PSMODE R/W 1b Power save mode enable (Default value = ‘1b’)

The data selects power save mode enable or disable. When themode is enabled, the device goes into power save mode if alldata in the on/off data latch are “0”. Table 15 shows the powersave mode truth table. Figure 7 shows the power save modeoperation timing.

[14:13] IDMTIM R/W 00b IDM working time select (Default value = ‘00b’)The data selects the time of output current sink at OUTn for IDMto detect LED open detection (LOD) or LSD without visiblelighting. Table 15 shows the work time truth table.Figure 9shows the IDM operation timing.

[12:11] IDMCUR R/W 00b IDM current select (Default value = ‘00b’)The data selects the sink current at OUTn for IDM to detect LEDopen detection (LOD) or LSD without visible lighting. Table 14shows the current value truth table. Figure 9 shows the IDMoperation timing.

[10] LSDVLT R/W 1b LSD detection voltage select. (Default value = ‘1b’)These two bits select the detection threshold voltage for the LEDshort detection (LSD). Table 12 shows the detect voltage truthtable.

[9] BLKMS R/W 0b BLANK Mode Select (Default value = ‘0b’)The data selects the working mode for BLANK pin. Table 11shows the truth table.

[8:7] SIDLD R/W 00b SID load control (Default value = ‘00b’)The data selects the SID data loaded to the common registerwhen LAT pulse is input for on-off data writing. Table 10 showsthe selected data truth table.

[6:0] BCALL R/W 1111111b Global brightness control (Default value = ‘1111111b’)The 7-bit data controls the current of all output with 128 stepsbetween 0~100% of the maximum current value set by aexternal resistor. Table 13 shows the current value truth table.

8.5.1.4 Output On/Off Data Write Timing and Output ControlWhen SCLK = “0” at LAT rising edge, the output on-off data can be updated with the 16-bit data in the shiftregister after the data are stored to the shift register using SIN and SCLK signals. When the on-off data latch isupdated, SID is loaded into the shift register except SID load control is “00b”. See Figure 11.

When BLANK = SOUT mode, the timing is show in Figure 12.

8.5.1.5 Function Control Data WritingWhen SCLK = “1” at LAT rising edge, the control data latch can be updated with the 16-bit data in the shiftregister after the data are stored to the shift register using SIN and SCLK signals. When the control data latch isupdated, SID is not loaded into the shift register.

If the device is in SOUT mode (FC[9] = 0) and BLANK = Low, SOUT is connected with BIT 7 of common shiftregister. Then FC data can’t be input and not valid. See Figure 13


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8.5.1.6 Function Control (FC) DataThe FC data latch is 16 bits long and is used to adjust output current values for LED brightness, select the SID,BLANK mode select, the output current for IDM, the output on time for IDM, and power-save modeenable/disable. When the IC is powered on, the control data latch is set to the default value (E67Fh).The controldata latch truth tables are shown in Table 9 through Table 14.

Table 9. Global Brightness Control (BC) Truth TableBCALL (BIT 6:0) Brightness Control for all Output with Output Current

0000000 Output current of OUTn is set to IO(LCmax) × 0%0000001 IO(LCmax) × 0.8%

∙ ∙ ∙ ∙ ∙ ∙1111110 IO(LCmax) × 99.2%1111111 IO(LCmax) × 100%

Table 10. SID Load Control Truth TableSIDLD

SID LOADED TO THE COMMON SHIFT REGISTERBIT 8 BIT 7

0 0 No data is loaded (default value)0 1 LED open detection (LOD) or thermal error flag (TEF) data are loaded1 0 LED short detection (LSD) or pre-thermal warning (PTW) data are loaded1 1 Output leakage detection (OLD) or IREF pin short flag (ISF) data are loaded

Table 11. BLANK Mode Selection TableBLKMS (BIT 9) BLANK MODE SELECTION

0 SOUT mode, BLANK pin worked as SOUT 8/16 select signal (default)1 Enable mode, BLANK pin worked as OUTPUT enable

Table 12. LSD Threshold Voltage Truth TableLSDVLT (BIT 10) LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE

0 VLSD0 (0.35 × VCC typ)1 VLSD3 (0.65 × VCC typ, default value)

Table 13. Current Select for IDMIDMCUR

SINK CURRENT AT OUTn FOR INVISIBLE DETECTION MODE (IDM)BIT 12 BIT 11

0 0 IDM is disabled (default value)0 1 2 µA (typ)1 0 10 µA (typ)1 1 20 µA (typ)

Table 14. IDM Work-Time Truth TableIDMTIM

INVISIBLE DETECTION MODE (IDM) WORKING TIMEBIT 14 BIT 13

0 0 All outputs are turned on for 17 OSC clocks (0.85 µs typ)0 1 All outputs are turned on for 33 OSC clocks (1.65 µs typ)1 0 All outputs are turned on for 65 OSC clocks (3.25 µs typ)1 1 All outputs are turned on for 129 OSC clocks (6.45 µs tyicalp, default value)


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36




Table 15. Power-Save Mode Truth TablePSMODE (BIT 15) POWER-SAVE MODE FUNCTION

0Power-save mode is disabled.The device does not go into power-save mode even if the bits in the output on/off data latchare all '0'.

1Power save mode is enabled (default value).The device goes into power-save mode when the bits in the output on/off data latch are all'0'.


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SIN

SCLK

LAT

BLANK

SOUT

VCC

GND

OUT0 - - - - - - - - - - OUT15

TLC59291

GND

GND

ICn

RIREF

IREF

BLANK

LAT

SCLK

3

VLED

Controller

DATASIN

SCLK

LAT

BLANK

SOUT

VCC

GND

OUT0 - - - - - - - - - - OUT15

TLC59291

GND

GND

IC1

IREF

VCC V

CC

SID read

RIREF

37




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe device is a 8/16-channel, constant sink current, LED driver. This device is typically connected in series todrive many LED lamps with only a few controller ports. On/Off control data and FC control data can be writtenfrom the SIN input terminal. The device has six type error flags: LED open detection (LOD), LED short detection(LSD), output leak detection (OLD), reference terminal short detection (ISF), Pre themal warning (PTW) andthermal error flag (TEF).

9.2 Typical ApplicationIn this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.

Figure 36. Multiple Daisy-chained TLC59291 Devices

9.2.1 Design RequirementsThe parameters for the design example are shown in Table 16.

Table 16. Design ParametersPARAMETER VALUE

VCC input voltage range 3 V to 5.5 VLED lamp (VLED) input voltage range Maximum LED forward voltage (VF) + 0.3 V (knee voltage)

SIN, SCLK, LAT, and GSCLK voltage range Low level = GND, High level = VCC

9.2.2 Detailed Design ProcedureTo begin the design process, a few parameters must be decided upon. The designer needs to know thefollowing:• Maximum output constant-current value for each color LED lamp.• Maximum LED forward voltage (VF).• Which error flags are used.


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Time = 400 ns/div

Ch

1 -

1 V

/div

Ch

2 -

2 V

/div

Time = 400 ns/div

Ch

1 -

1 V

/div

Ch

2 -

2 V

/div

38




9.2.3 Application Curves

Figure 37. Output Waveform When BLANK_Mode = 0 Figure 38. Output Waveform When BLANK_Mode = 1

10 Power Supply RecommendationsThe VCC power supply voltage should be decoupled by placing a 0.1-µF ceramic capacitor close to the VCC pinand GND plane. Depending on the panel size, several electrolytic capacitors must be placed on the boardequally distributed to get a well regulated LED supply voltage (VLED). The VLED voltage ripple must be less than5% of it nominal value. Futhremore, the VLED must be set to the voltage calculated by Equation 3.

VLED > VF + 0.4 V (10-mA constant-current example) (3)

Where• VF = maximum forward voltage of all LEDs.


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39




11 Layout

11.1 Layout Guidelines• Place the decoupling capacitor near the VCC pin and GND plane• Place the current programming resistor RIREF close to the IREF pin an the IREFGND pin.• Route the GND pattern as widely as possible for large GND currents.• The routing wire between the LED cathode side and the device OUTXn pin must be as short and straight as

possible to reduce wire inductance.• When several ICs are chained, symmetric placements are recommended.

11.2 Layout Example

Figure 39. Layout


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40




12 Device and Documentation Support

12.1 Documentation Support

12.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.3 TrademarksE2E is a trademark of Texas Instruments.

12.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://e2e.ti.com

http://support.ti.com/

http://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TLC59291RGER ACTIVE VQFN RGE 24 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59291

TLC59291RGET ACTIVE VQFN RGE 24 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59291

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

http://www.ti.com/product/TLC59291?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/TLC59291?CMP=conv-poasamples#samplebuy

http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2015

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max heightPLASTIC QUAD FLATPACK - NO LEAD

4204104/H

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PACKAGE OUTLINE

C

SEE TERMINALDETAIL

24X 0.30.2

2.45 0.1

24X 0.50.3

1 MAX

(0.2) TYP

0.050.00

20X 0.5

2X2.5

2X 2.5

A 4.13.9

B

4.13.9

0.30.2

0.50.3

VQFN - 1 mm max heightRGE0024BPLASTIC QUAD FLATPACK - NO LEAD

4219013/A 05/2017

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

1

6 13

18

7 12

24 19

(OPTIONAL)PIN 1 ID

0.1 C A B0.05

EXPOSEDTHERMAL PAD

25 SYMM

SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

DETAILOPTIONAL TERMINAL

TYPICAL

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EXAMPLE BOARD LAYOUT

0.07 MINALL AROUND

0.07 MAXALL AROUND

24X (0.25)

24X (0.6)

( 0.2) TYPVIA

20X (0.5)

(3.8)

(3.8)

( 2.45)

(R0.05)TYP

(0.975) TYP


4219013/A 05/2017

SYMM

1

6

7 12

13

18

1924

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

25

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

METAL

SOLDER MASKOPENING

SOLDER MASK DETAILS

NON SOLDER MASKDEFINED

(PREFERRED)

EXPOSEDMETAL

www.ti.com

EXAMPLE STENCIL DESIGN

24X (0.6)

24X (0.25)

20X (0.5)

(3.8)

(3.8)

4X ( 1.08)

(0.64)TYP

(0.64) TYP

(R0.05) TYP


4219013/A 05/2017

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

25

SYMM

METALTYP

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:20X

SYMM

1

6

7 12

13

18

1924

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated

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