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Transcript of TKT-1212 Digitaalijärjestelmien toteutus Digitaalijärjestelmien toteutus Lecture 15 - System...
TKT 1212 Digitaalijärjestelmien TKT-1212 Digitaalijärjestelmien toteutus
Lecture 15 - System design trends & challenges
Erno Salminen TUT 2012Erno Salminen, TUT, 2012
Sidenote regarding exercises: Always mark the initial
state of the FSM!
Outline and acknowledgementsOutline and acknowledgements Challenges in digital systems
Introduction to system design
Most slides were made by Ari Kulmala
The International Technology Roadmap for Semiconductors
M. Keating and P. Bricaud, “Reuse Methodology Manual for System on a Chip Designs 3rd Edition”System-on-a-Chip Designs, 3rd Edition
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System driversy There isn’t any
“one size fits all solution”
Digital products have e g 6 different have e.g. 6 different segments, all with with emphasizing diff t tdifferent aspects E.g. security vs.
cost
http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/200p9_SysDrivers.pdf
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Implementation style trend: Moore’s law and moreMoore’s law and more
”Moore’s law” states roughly: The number of componentsnumber of components [transistors] on an integrated circuit doubles every 1.5-2 years
SiP M IC i i l SiP: Many ICs in a single package(system-in-package)
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System on chip (SoC)System-on-chip (SoC) Integrated circuit (IC) that integrates most (all?) components of a computer or
other electronic system into a single chipy g p Processors, memories, hardware accelerators, I/Os Interfaces to external memories, analog devices, etc
1990-1992 mobile phones included 15 ICs and 800 other discrete components d i 2002 3 4 IC d 200 di t t [N 2004]and in 2002 3-4 ICs and 200 discrete components [Neuvo, 2004]
Using SoC reduces system costs ($) and power, offers fasterfaster…
Two main SoC types: 1. power-efficient (PE) for
mobilemobile2. high-performance (HP, later
a.k.a. CS – consumer stationary)
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stationary)
Texas Instruments’ OMAP chips have been used e.g. in many smart phones
[Y. Neuvo, Cellular phones as embedded systems, IEEE Int’l Solid-State Circuits Conference,Digest of Technical Papers, 2004. pp. 32-37.]
System on chip typesSystem-on-chip types1. Consumer stationary E g a high-end game machine
2. Power-efficient
E bil hE.g. a high end game machine (like PS3)
Performance is most important differentiator.
d l d
E.g. mobile phones
Power consumption is strictly limited by the battery (lifetime)
Wide application domain Many functions implemented
with software General purpose processing
High performance required nevertheless
Specialized application domain with rather predictable processing (e.g. channel
General-purpose processing engines
Has less processing engines than mobile SoCsl l l l f l
coding, video…)
Some general-purpose and many specialiazed HW units
Relatively long life cycle Easy to add or modify functions
Die-size about 220 mm2
Rapid progress and hence life cycle is short
Die-size about 64 mm2
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Challenges in digital system designChallenges in digital system design High-level challenges, not taking into account physical and
manufacturing issues
M d l d f1. Managing design complexity and verification
2. Minimizing power consumption
3 E i3. Economics
4. (optimizing chip area & performance)
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Design challenge #1 :ComplexityDesign challenge #1 :Complexity Good news: "Over the past ten years, reuse
leverage more than doubled, and more reuse tends to translates into less project effort, shorter cycle times as well as fewer spins and less schedule slip.”
Bad news: ”85%-89% of IC projects miss their p joriginal schedules… Schedule slip is 5-30% [Accenture’s report] or even 44% [Numetrics’ report]”
One reason is that re usable components are not One reason is that re-usable components are not, after all, easy to integrate
[Eetimes] http://eetimes.eu/semi/showArticle.jhtml?arti
cleID=204702114 http://www.eetasia.com/ART_8800520301_4
80200_NT_68f71562.HTM
8
Fig. SoC size as function of time (CAGR= compound annual growth rate)
Design complexityDesign complexity Logic size increases over 10x per decade!
There will be lots of people, lots of files, lots of requirements…
All h l d bl h k d h ll All things must at least double-checked, hence all steps must be repeatable
Reuse and automation are crucial Reuse and automation are crucial
Be extra careful with versioning and verification
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Example: IBM/Sony/Toshiba CELL BE 2005BE, 2005-
Commercial chip with multiple heterogeneous processors: 1 64-b PowerPC (32KB L1) + 8 128-b SPEs (256 KB scratch-pad mem), each ( p )with DMA, 512 KB L2 3.2 GHz, orig. 90 nm, 221 mm2, 240M transistors, theor. max 230 GFLOPS
Acronyms:Acronyms:synergistic processor elements (SPE)dual-threaded power processor element (PPE)element interconnect bus (EIB) (actually ring)
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New architectures: Intel Terascale/Polaris 2007Terascale/Polaris, 2007- Research processor with 80 homogeneous cores (small processors) Interconnected with 2 D mesh network on chip Interconnected with 2-D mesh network-on-chip Stacked chip: to solve local memory problems
Parallel programmingp g gbecomes mainstream
How to do it efficiently?
11 Fig 1.Die stacking improves performance Fig 2. Intel Polaris
High performance SoC trendHigh-performance SoC trend
DPE = data processing engineengine
ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf
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SoC PE Design complexity trendsSoC-PE Design complexity trends
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#DPEs is 3-4x compared to SoC-HP
Memory dominates the area
Additional constraints (power-efficient SoC)efficient SoC)
Problem #2
Problem #1
More More performance, very
well…
ITRS 2005, http://www.itrs.net/Links/2005ITRS/SysDrivers2005.pdf14
Challenge #2: Power consumptionChallenge #2: Power consumption Chip power consumption can be defined as
Pavg = Pdynamic + Pleakage
Traditionallly Pdynamic dominated in CMOS and Pleakage was very small
However, in 90nm and below, leakage becomes an increasingly important factor (see fig)
Other factors such short Other factors, such short-circuit power when gate switches state, are often
dignored Power optimization done
both at design time and a Fig. Leakage vs. dynamic power
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both at design time and a runtime
Fig. Leakage vs. dynamic power [http://asic-soc.blogspot.com/2008/03/leakage-power-trends.html]
D i tiDynamic power consumption2
dynamic out ddP K C V f
K = average number of transitions of the output node every cycle divided by two (e.g. ½ means that
dynamic out dd f
node every cycle divided by two (e.g. ½ means that there is a single transition each cycle) Glitches etc
l l Vdd = Supply voltage f = clock frequency C = output capacitance Cout = output capacitance Note the square-law dependence of Vdd
Typically, higher the f, higher Vdd required
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yp y, g f, g dd q
Power breakdown in Hi perf SocPower breakdown in Hi-perf SocS
taD
yatic P
ynamic P
Variability between devices and temperature effects will increase leakage notably
Power consumptionof one DPE reduces but their number increases. Battery life is not an issue, but chip packaging and cooling are.
ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/01_SysDrivers_2006UPDATE.pdf
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Power breakdown in mobile SoCPower breakdown in mobile SoCLarger fraction of power is static since these devices are ”always-on”. Note also that memory’s static (leakage) power is larger than dynamic
Dynadynamic. am
ic PS
tatic P
Note the difference in y-axis scales: 14W vs. 600 W (prev slide)
Challenge #3: EconomicsChallenge #3: Economics Rapid technology change shortens product life cycles and
makes time-to-market a critical issue
Margins are very small in many business areas
V h h d d d d Very high design productivity is needed Sure we can build that but will anyone want to buy it with such
a price?p
Maximizing volume reduces unit costs Speed binning – chips are priced according to their freqeuncy
Note that many customers in cosumer markets appreciate little bit different things than engineers
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Simplified Electronic Product D l t C t M d l Development Cost Model
http://www.itrs.net/Links/2005ITRS/Design2005.pdf20
Major steps in design in design productivityReuse, higher abstraction level anddesign automation are the intertwinedthe intertwined cornerstones.
Lots of research needed in general.In many cases, adopting the existing good methods is already amethods is already a step forward for many companies.
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Design development costsDesign development costs Manufacturing non-recurring engineering (NRE) costs are in the order
of millions of dollars (mask set + probe card) for high-end chips( p ) g p High non-recurring engineering (NRE) costs necessitate high volume
Design errors can cause silicon re-spins that multiply manufacturing NRE ASIC manufacturing cycle times are measured in weeks, with low S C a u actu g cyc e t es a e easu e ee s, t o
uncertainty. Design and verification cycle times are measured in months or years,
with high uncertainty. Test cost has grown faster than manufacturing costs Software can account for 80% of embedded-systems development cost Verification engineers outnumber design engineers on microprocessor g g g p
project teams Verification is top priority from day one, not the last phase just before
delivery
http://www.itrs.net/Links/2005ITRS/Design2005.pdf22
System design processSystem design process
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System design phasesphases Blocks are preferably re-
usable IPs
Blocks implemented as in earlier lectures with reearlier lectures with re-usable macros
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System Design ProcessSystem Design Process1. System specification Identify the system requirements (engineering marketing) Identify the system requirements (engineering, marketing) Formulate the preliminary specification
2. Develop a behavioural model and test environment Basic algorithms their usability (e g good enough video encoding Basic algorithms, their usability (e.g. good enough video encoding
quality) Executable specification, “golden reference”, e.g. C++/SystemC Develop environment for verifying the functionality and Develop environment for verifying the functionality and
performance of the design3. Model refinement Do not intrdocude too many details at first. Add them gradually.o ot t ocu e too a y eta s at st. t e g a ua y. Try to discard definitely bad choices early E.g. floating point model -> fixed-point model -> cycle-accurate
and bit-accurate model
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System Design Process (2)System Design Process (2)4. HW/SW partitioning (decomposition)
Largely a manual process guided by experience and understanding of Largely a manual process guided by experience and understanding of tradeoffs (area vs. performance)
Define the interfaces between HW and SW, communication protocols5. Specify and develop a hardware architectural modelp y p
IPs, Memory architecture, interconnection structure… Bandwidth, latency… Start from high level models, transaction-level modeling
R fi h hi il i h i Refine the architecture until it meets the requirements6. Refine and test architectural model (co-simulation)
A behavioural model of the HW A prototype version of the SW A prototype version of the SW System-level test SW Key to success – efficient HW-SW co-design
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System Design Process (3)System Design Process (3)7. Specify and implement blocks Reuse if possible E.g. HW specification: Basic functions Basic functions
Timing, area, and power requirements
Physical and SW interfaces
D f h I/O d Descriptions of the I/O pins and register map
Separate testbenches for all HW components!
8. Integration8. Integration First small blocks together, then bit larger, then... Check the assumptions and estimations made in earlier phases
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System design ti litimeline
”Spiral flow” instead of waterfallwaterfall
Maximum parallelism HW development
(prototypes, emulation)(prototypes, emulation) SW development Verification (verification
environment)) HW/SW integration
Iterations after iterations Inevitable Gradual refinement
Physical issues taken into account early
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y
ITRS 2006 update, http://www.itrs.net/Links/2006Update/FinalToPost/02_Design_2006Update.pdf29
Teaching in DCSTeaching in DCS
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DI-tutkinto 30 opEsitiedot/Koulutusohjelma-
Kandidaatin tutkinto 25 op
Yksinkertaistetut kurssien esitiedot 11/12, laatinut ES
jkohtaiset
p
TKT-1101 DigTeknPer.
TKT-1202 DigSuunn
TKT-1212 DigJärjTot8 op (k3)
TKT-2431 SoC-Suunn
5 op (s1)
TKT-1400 ASIC I
5 op (s1)
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4 op (s1) 5 op (s1)
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TKT-1527DigSysDesIss.
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tai ELE1010
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TKT-1230 Laboratorio
3 op (k4)
5 op (k3)
TKT-3526Proc. Design
TKT-2526Project work
5-8 op
TKT-9626/9636Seminar
3-6 opTKT-3400Tietokonetekn. II
5 op (s1)p
5 op (k3)TKT-3500
Mikrokontroll.5 op (s1)
g5 op (k3)
TKT-2301 Lang. sens.vsov. 5 op (s1)
TKT-2456 Wireless.sens. 5 op (k3)
TKT-1540/1550DI-työ semin.
1+0 op
TKT-9646Colloqium
3 op
5 op (k3)
TKT-1570Kandityösemin.
8 op
tai ELE-2300
TKT-2530SatellPaikann
5 op (s1)pakollinenTKT-2556
Inertial nav.
p ( ) p ( ) 3 op
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Esitietoksi käy TKT-1202 tai TKT-1212TKT-9617
ScientificPubl6 op (s1)
suositeltava
Tarkista eksaktit esitietovaatimukset opinto-oppaasta.
5 op (k4)y
SummarySummary Increasingly complex systems need new methodologies Hierarchical gradual refinement Hierarchical, gradual refinement Reuse evertyhing you can. Pay attention that your own work is
reusable Accessible, easy to start with, well commented, tool-independent…, y , , p
Invest in executable specifications Divergence to two types of SoCs: High-performance & Low-
powerp Several advances and active research required in order to keep on
pushing the technology in its limits Parallel processing seems the best way to increase performanceParallel processing seems the best way to increase performance New methodologies for SW programmers need to be adapted Currently, tool support for parallelization is weak
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Course summaryCourse summary Most important things you must know (V)HDL basics: entity architecture process signal data types (V)HDL basics: entity, architecture, process, signal, data types… What happens in simulation and synthesis Testbench and reuse concepts Clocking synchronization Clocking synchronization
Supplementary knowledge: FPGA technology and project management
You made a great progress during the exercises! From simulated You made a great progress during the exercises! From simulated 1-b adder to an audio synthesizer on FPGA
Please fill in the official course feedback in Kaiku You can have 1 A4 sheet of your own notes in the examYou can have 1 A4 sheet of your own notes in the exam See you on the other TKT-courses! Thank you for your interest
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