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TITRE

INSTITUTD’ÉLECTRONIQUEETDETÉLÉCOMMUNICATIONSDERENNES

DesignSpaceExplora>oninthecontextofSKA

Jean-FrançoisNEZANCompu>ngforSKAFebruary2016

WiththecourtesyofKalray,

D.Ménard,M.PelcatandK.Desnos

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Introduc>on

•  Manychallengingapplica>ons–  MPEGCodecs

•  MPEG4Part2,AVC,SVC,HEVC,SHVC

–  ComputerVisionand3DProcessing•  StereoVision,SLAM

–  Cryptography•  Chao>c-basedCryptography

–  Telecommunica>ons•  3GPPLTEeNodeB

–  SquareKilometerArrayproject(SKA)

•  DesignSpaceExplora>on:Whatisthebesthardware?

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Introduc>on

3

Texas Instruments Keystone II 8x DSP cores @ 1.2 GHz – 4x ARM Cortex A15 @ 1.4 GHz – 6 MB memory + DDR – 650$ - 28nm – 16 Watts

Odroid with Samsung Exynos 5 4x Cortex A15 @ 1.8 GHz– 4x Cortex A7 @ 1.2 GHz + PowerVR GPU – 50$ - 28 nm – 1Watt to 6 Watts

•  Poten>alCandidates– Mul>core

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Introduc>on

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Zboard with Xilinx Zynq 2x ARM Cortex A9 @ 1 GHz – 444 Logic Cells

512 MB memory + DDR – 400$ - 28nm – 3 or 4 Watts ?

Nvidia GeForce GTX Titan X 3072 cores – 12 Go memory – 1200€ – 1 GHz – 28nm – 313 Watts

•  Poten>alCandidates

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Introduc>on

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Kalray MPPA

MPPA®-1024

§ 16computeclusters§ 2I/Oclusterseachwithquad-coreCPUs,DDR3,4Ethernet10Gand8PCIeGen3§ Dataandcontrolnetworks-on-chip§ Distributedmemoryarchitecture§ 634GFLOPSSPfor25W@600Mhz

§ 16usercores+1systemcore§ NoCTxandRxinterfaces§ Debug&SupportUnit(DSU)§ 2MBmul>-bankedsharedmemory§ 77GB/sSharedMemoryBW§ 16coresSMPSystem

§ 32-bitor64-bitaddresses§ 5-issueVLIWarchitecture§ MMU+I&Dcache(8KB+8KB)§ 32-bit/64-bitIEEE754-2008FMAFPU§ Tightlycoupledcryptoco-processor§ 2.4GFLOPSSPpercore@600Mhz

•  Poten>alCandidates– Manycore(NUMAarchitecture)

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Outline


1.  Introduc>on2.  Casestudy:SKACSPChannelizeronMPPA3.  ChallengesforDSE4.  PiSDF:aparallelModelofComputa>onforDSE5.  PREESM:atoolforDSE

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SKACSPChannelizeronMPPA

•  SquareKilometerArrayProjectinSouthAfrica

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Channelizer64Kà256KFFT3-4bitsà8bits

Correlator

PulsarSearchbeamformer

PulsarSearch

CSP Central Processing Unit

MiddleArray Receiver

197 x 15m dishes

SDP Science Data Processing

Ingest Gridding InverseFFT Deconvolu>on

ReginonalScienceCenters

80 PFlops

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•  CSPChannelizerapplica>on–  219realFFTin524µs– Mainconstraints:throughputandenergy–  Selec>onofbothalgorithm&architecture

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Inpu

t

Outpu

t

Tran

spose

FFT

Tran

spose

TwiddleCo

r.

FFT

Tran

spose

Combine

219 x 8bit real

219 x 8bit Real Part

219 x 8bit Imaginary Part

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•  Profilingof219realFFT(requirementof524µs)includingdatatransfers

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Implementa@onMPPAComputeCluster

Andey@400MHz(ms)

MPPA-256Andey@400MHz

(ms)

MPPA-256Bostan@400MHz

(ms)


(ms)

FullyFixed-point–6steps 11,64 1,07 0,975 0.65

MixFloatImplementa@onFloa@ng-pointinFFTstageswithfixed-pointstorageinthemiddleofthe6-step

13.70 1.17 1,05 0.70

FullyFixed-point–6stepsMPPA-256

Andey@400MHz




Powerconsump@onof1MPPA 8.7W 8.7W 8W 17W

NumberofMPPA 2+1cluster 1+14clusters 2 1+4clusters

Powerconsump@on 17,95W 16,3W 16W 22W

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MPPA®-1024

AndeyKalray1stgenera@on

211GFLOPSSP70GFLOPSDP

32-bitaddressing400Mhz

Kalray2ndgenera@on634GFLOPSSP316GFLOPSDP64-bitaddressing

600Mhz

Kalray3rdgenera@on1056GFLOPSSP527GFLOPSDP64-bitaddressing

1000Mhz

2014 2015

Coolidge

MPPA®-256

MPPA®-64

2016 2017

TSMC28nm(HP) 28nm/16nm

Bostan

Volume Samples Volume Samples Volume

Produc'on

Development

UnderSpecifica'on

MPPA® MANYCORE Processor Roadmap

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•  Architecturedependentop>miza>ons–  Throughput

–  Latency

–  Energy

– Memory

–  ProgrammingTime

SIMD&singlecoreParallelism

Datarepresenta>on

ManycoreMapping

Energy-awareprocessing

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•  MatlabCodetransla>on–  Timeconsuming–  Errorprone

•  Evolu>onofthealgorithmrequirements–  Discussionsaroundaccuracy–  Futuredeployments(1stin2018andseveralonesun>l2030)

•  Evolu>onoftheHardware–  NumberofCores–  Corearchitecture–  Technology

•  SameworktobedoneonFPGA,GPU,Mul>core...

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Outline



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Source:ITRSSystemDrivers2011

Hardware Complexity

2010 2015 2020 2025

5000

4000

3000

2000

1000

0

Nb of PE per SoC

ChallengesforDesignSpaceExplora>on

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Lines of code/chip x2 every 10 months

Software productivity Lines of code/day x2 every 5 years

Hardware complexity Transistors/chip x2 every 18 months

Software Productivity Gap

Source:ITRS&Hardware-dependentSo9ware,Eckeretal.,Springer

1990 1995 2000 2005 2010 2015

log


Multicore Era

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•  Specifica>onofparallelalgorithms–  Throughput/Latencyevalua>on–  Predictablememoryfootprints–  Legacycodereuse

•  Workingprototypes–  Seamlesspor>ngtoanexis>ngplaporm(CPU,GPU,NUMA…)–  Guaranteeddeadlock-freeness–  Inter-PEcommunica>ons

•  Virtualprototypes–  Numberofcores– Memorysizeandtechnology–  Hierarchicaltopologies(memoriesandclustersofcores)

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•  Fromsequen>altoparallelModelsofComputa>ons(MoCs)

–  OpenACC,M-TAPI,OpenDataPlane(ODP)…

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Legacycode

Shared/Dist.memories

GPU Mapping/scheduling

HeterogeneousMPSoC

Hardwaredependance

VHDL

VivadoHLS

OpenCL

OpenMP3

OpenMP4

PThread

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•  Analogywithsequen>almodels,toolsandmethods

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Hardware independence Efficiency

Assembly

Sequential Models

Compilers

OpenCL,OpenMP…

Tobedefined:PiSDF?

Tobedefined:PREESM?

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Outline



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PiSDFMoC

Algorithmdescrip@onsusingDataflowGraphs•  SynchronousDataflow(SDF)

–  ActorsandDataports–  FIFOqueues

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2

2

1

1 1 2 1 1

B

A C D E

E.LeeandD.Messerschmis,“Synchronousdataflow”,ProceedingsoftheIEEE,1987.

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PiSDFMoC

Algorithmdescrip@onsusingDataflowGraphs•  Data-drivenexecu>on

–  AnactorisfiredwhenitsinputFIFOscontainenoughdata-tokens.

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B

A C D E

Core1 A B C C D E

2

2

1

1 1 2 1 1

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PiSDFMoC

Algorithmdescrip@onsusingDataflowGraphs•  Expressionofparallelisms:///

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2

2

1

1 1 2 1 1

B

A C D E

Core1

Core2

Core3

x2

A B C C E A C +1 +1

B C +1 +1

D E +1 +1

D

Task parallelism Data parallelism Pipeline parallelism Internal parallelism

Data Pipeline InternalTask


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PiSDFMoC

PiSDF(ParameterizedandInterfacedSynchronousDataflow)

N

Read Header Size =4

Size Size Read Image

Filter

/N Size

out

Size

in

Size

SetNb Slices =2 Size

Kernel /N Size Size

Size Size Send

=6

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PiSDFMoC

PiSDF(ParameterizedandInterfacedSynchronousDataflow)•  PiSDFis:

–  Hierarchical&Composi>onal–  Sta>callyparameterizable(forcompile>meanalysis)–  Dynamicallyreconfigurable(atrun>me)

•  PiSDFfosters:–  Predictability–  Parallelism–  Lightweightrun>meoverhead–  Developer-friendliness

K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, S. Aridhi “PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration”, SAMOS XIII

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Outline



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PREESM:atoolforDesignSpaceExplora>ons

WhatisPREESMIS:•  OpenSourceTool

–  AvailableonGitHub•  Research-OrientedTool

–  Newmodels,op>miza>ons,scheduling•  Eclipse-basedIntegratedTool

–  Severalplug-ins,metamodels•  ExtendedWebTutorials

–  hsp://preesm.sourceforge.net/website

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PREESM +C compiler

Simulator + Debugger

+ Profiler

Algorithm

Architecture PE

DSP DSP

DSP DSP

PE PE PE PE

Peripherals

Main Memory

Multicore Runtime

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•  PREESMMainfeatures:–  Automa>cmapping/scheduling

•  Workingandvirtualprototypes– Memoryanalysis:boundingthememoryneeds– Memoryop>misa>on:Buffermergingtechniques–  Powerop>miza>ontechniques–  Codegenera>on

•  Baremetal(sta>cparameters)•  Specificrun>me(dynamicparameters)

•  AskforaDemo!!

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PREESMDeployment

Mapping/Scheduling•  State-of-the-artalgorithms(FAST,List,…)•  Latencyandloadbalancingop>miza>on•  Customizableaccuracy(w.r.t.communica>ons)

core1 core2 core3 core4

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Memoryop@miza@ons•  Boundingthememoryneedsofanapplica>ongraphto

–  Evaluatethememoryrequirements–  Adjustthesizeofarchitecturememory–  Assesstheop>malityofamemoryalloca>on

0 Available Memory

Wasted memory

Possible allocated memory

Insufficient memory

Upper Bound Lower Bound

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Memoryop@miza@ons•  BuffermergingtechniqueforSDFgraphs

– 48%lessmemorythanstate-of-the-arttechniques

B

D

C A 20

30 10

No buffer merging AB 30

BC 20

BD 10

memory

Buffer merging

AB 30

BC 20

BD 10

memory

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Energyop@miza@on:plaeormExynos5

OdroidExynos5Big.LITTLE

A7

A7

A7

A7

A15

A15

A15

A15

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Energyop@miza@onsetupcore1 core2 core3 core4

P=0 P=1 P=0.5 P=1 P=0.5 P=0

OdroidExynos5Big.LITTLE

A7

A7

A7

A7

A15

A15

A15

A15

Image Processing

Linux-basedRun>me

(AboAkademi)QoS DVFS

DPM

P-Value

20% energy savings on a parallel Sobel + sequential postprocessing wrt. Linux completely fair scheduler and on-demand governor

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Codegenera@onformul@pletargets•  Mul>-C6XDSPs:

–  TMS320c6678fromTexasInstruments–  Supportstheac>va>onoftheDSPcaches.

•  Mul>-x86andmul>-ARMCPUs:–  LinuxandWindows,pthread

•  OMAP4heterogeneousplaporm:–  dual-coreARMCortex-A9,2Cortex-M3,andaC64xTDSP

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PREESM:academicpartners

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PREESM:industrialpartners

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Questions ?

http://preesm.sf.net @PreesmProject

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