Timing System with Two-Way Signaling cRIO-EVR

Micro-Research Finland Oy

Timing System with Two-Way Signaling

cRIO-EVR

Jukka Pietarinen

EPICS Meeting PadovaOctober 2008


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Timing System Topology

Event Generator (EVG)

12-Way Fan-Out

RF input (50 MHz to 1.6 GHz)Rep. Rate Trigger Input

e.g. 50 Hz TTL

Hardware Triggers/Clocks

12-Way Fan-Out

Event Receiver (EVR)

Hardware Outputs



Multimode fiber


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Two-Way Signaling


Fan-Out/Concentrator


e.g. 50 Hz TTL




Hardware Outputs



Multimode fibers

VME orCompactPCI/PXI

Hardwareinputs


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cPCI-FCT-8


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Fan-Out• one in – eight out fan-out• up to 2.5 Gbps SFPs with multimode transceivers (single

mode for extended reach)• CDR to regenerate gigabit rate signal

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX RX

UPLINK87654321RXRXRXRXRXRXRXRX

CDR

fan-outdifferential


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Concentrator

• Eight in – one out• Uplink TX port is using local reference

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX

SFP

TX RX

UPLINK87654321RXRXRXRXRXRXRXRX

FPGA

localref.

• Forwarding of– Events– Distributed bus bit– Data buffers


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Broadcasting




e.g. 50 Hz TTL




Hardware Outputs



Multimode fibers

Hardwareinputs

LoopbackUplink port


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Concentrator – Event Forwarding

• Each RX channel has 2k event FIFO– Hold events in case of simultaneous

events from several ports

• Priority encoding– First come – first served– Round-robin

• One event from one port

→ next port

1 3 4 5 6 7 8 UP2

01

0102 03 04 05 06 07 08 09

11 12 13 14 15 16 17 0618

07

08

09

02


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Concentrator – Distributed bus bits

• Eight bit wide distributed bus• Each distributed bus bits from all ports is logically OR’ed

together

OR

RX 1 DBUSn

RX 2 DBUSn

RX 3 DBUSn

RX 4 DBUSn

RX 5 DBUSn

RX 6 DBUSn

RX 7 DBUSn

RX 8 DBUSn

UPLINK TX DBUSn


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Concentrator – Data Buffer Forwarding

• Each RX channel has 2 kbyte data FIFO• Forwarding starts immediately after start of

reception– Latency is minimized

• Priority: Round-Robin


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Concentrator – Latency Performance

EVG

EVREVR

1 2 3 4 5 6 7 UL8

Fan-Out ConcentratorFCT

2 m

2 m

2 m

Scope

Events 162 ± 4 ns

Distributed bus bits 107 ± 4 ns

Data buffers 181 ± 8 ns

• 499.654/4 MHz Event Clock

• Latency of Concentrator only (without fibre delays)


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CompactRIO Event Receiver

• Timing receiver form factors:– VME64x 6U– PMC (PCI mezzanine)– CompactPCI/PXI 3U

• Need for timing for embedded systems• MRF is working together with LANL and NI

to design an Event Receiver for cRIO


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CompactRIO EVR prototype• SFP transceiver for event link• FPGA with high speed serial link• 10/100 ethernet for control and

configuration• 64 Mbytes DDR2 memory• 2 × 16 Mbits serial flash• EEPROM• 9 to 35 VDC power supply input

• Power dissipation• Achieve required timing resolution • Achieve required data transfer

capability• Control and configuration methods

– cRIO– ethernet

Challenges (when used with NI HW/LabView)


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cRIO-EVR Stand-alone

• 9 to 35 VDC power supply input• DSUB15 with max. 11 I/O pins, ethernet control• Lattice Mico32 (lm32) system

– 32-bit soft-core CPU– 10/100 ethernet MAC– DDR2 memory controller

• Work started to port RTEMS to lm32 target– Tool set compiled from sources

• Binutils 2.19 (Lattice toolkit + some patches)• Gcc-3.4.4 (Lattice toolkit + some patches)• Newlib-1.16 (with RTEMS patches)

• Existing lm32 port for ucLinux– Is and (most probably) will not get into kernel mainstream

Timing System with Two-Way Signaling cRIO-EVR

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