Timing in Digital Circuits - Notes
9
Input Clock Edge-Sensitive Flip-Flops Definition of Terms Clock: Periodic Event, causes state of memory element to change. Input is sampled at this clock edge. Input: Value sampled by flip-flop at clock edge. Example: D Flip-Flop Input Clock Output Input Clock Setup and Hold Time Definition of Terms Setup Time (Tsu) There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable T su T h Input Clock Edge-Sensitive Flip-Flops Input value changes after the setup time. The input is not stable long enough before the clock edge. Invalid! T su Input Clock Edge-Sensitive Flip-Flops T h Input value changes before the hold time. The input is not stable long enough after the clock edge. Invalid! Analogy - Taking Your Friend to the Train If the train leaves at 8:00 and you live 20 minutes away from the station, when should you leave your house? At 7:40! (“setup time” is 20 minutes) If you leave after 7:40, you will miss the train. If you leave before 7:40, you should have enough time to get to the station before it leaves. Analogy - Taking Your Friend to the Train ( cont .) Your friend needs help boarding the train and the train allows only 5 minutes for boarding. How long should you stay after you have arrived? Without your help for the full 5 minutes, your friend is not able to board and will miss the train. At least five minutes (“hold time”) or 8:05 at the earliest.
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Contains explanation for timing of digital circuits
Transcript of Timing in Digital Circuits - Notes
Input
Clock
Edge-Sensit ive Flip-Flops
Definition of Terms
Clock: Periodic Event, causes state of memory element to change. Input is sampled at this c lock edge.
Input: Value sampled by f lip-f lop at clock edge.
Example: D Fl ip-Flop
Input
Clock
Output
Input
Clock
Setup and Hold Time
Definition of Terms
Setup Time (Tsu)
There is a t iming " window" around the
clocking event during which the inpu t
must remain stable and unchanged
in o rder to be recognized
There is a t iming " window" around the
clocking event during which the inpu t
must remain stable and unchanged
in o rder to be recognized
Minimum time before the clocking event by which the input must be stable
Hold Time (Th)Minimum time after the clocking event du ring which the input must remain stable
Tsu
Th
Input
Clock
Edge-Sensit ive Flip-Flops
Input value changes after the setuptime. The input is not stable longenough before the clock edge.
Invalid!
Tsu
Input
Clock
Edge-Sensit ive Flip-Flops
Th
Input value changes before the holdtime. The input is not stable longenough after the clock edge.
Invalid!
Analogy - Taking Your Friend to the Train
If the train leaves at 8:00 and you live 20 minu tesaway from the station, when should you leave you rhouse?
At 7:40! (“ setup t ime” is 20 minu tes)
If you leave after 7:40, you wi ll miss the train. If youleave before 7:40, you should have enough t ime toget to the station b efore it leaves.
Analogy - Taking Your Friend to the Train (cont.)
Your friend needs help boarding the train and thetrain allows only 5 minutes for boarding .
How long should you stay after you h ave arr ived?
Withou t your help for the ful l 5 minutes, your friendis not able to board and wi l l miss the train.
At least five minu tes (“ hold time” ) or 8:05 at theearl iest.
Input
Clock
Negative Hold Time
Tsu
The valid region o r " window" associatedwith the clock ev entdoes not have to becentered around the
clock edge.
The region can be tothe right or left of theclock edge when thesetup or hold t imes
are negative.
The valid region o r " window" associatedwith the clock ev entdoes not have to becentered around the
clock edge.
The region can be tothe right or left of theclock edge when thesetup or hold t imes
are negative.
Th (Negative Hold Time)
When the hold time is negative, thevalid region is to the left of the clockedge.
This allows the inpu t to change slightly before the clock edge withoutdisturbing the operation o f the fl ip-flop.
Input
Clock
Negative Setup Time
Tsu
The valid region o r " window" associatedwith the clock ev entdoes not have to becentered around the
clock edge.
The region can be tothe right or left of theclock edge when thesetup or hold t imes
are negative.
The valid region o r " window" associatedwith the clock ev entdoes not have to becentered around the
clock edge.
The region can be tothe right or left of theclock edge when thesetup or hold t imes
are negative.Th
(Negative Setup Time)
When the setup time is negative, thevalid region is to the right of the clockedge.
This allows the inpu t to change slightly after the clock edge withou tdisturbing the operation o f the fl ip-flop.
Note: you canno t have botha negative setup time anda negative hold time!
Propagation Delay
The output of a flip-flip does not change instantaneously at theclock edge. The change in output occurs after a propagationdelay through the flip flop.
D
Clk
Q
T plh T phl
The propagation delay is usually different for thelow to high and high to low transitions.
Edge-Triggered Timing Specifications
74LS74 Posit iveEdge Triggered
D Flipflop
• Setup t ime• Hold time• Minimum clock width• Propagation delays (low to high , high to low, max and typical)
All measurements are made from the clocking eventthat is, the rising edge of the clock
D
Clk
Q
T su 20 ns
T h 5 ns
T w 25 ns
T plh 25 ns 13 ns
T su 20 ns
T h 5 ns
T phl 40 ns 25 ns
Cascaded Flipflops
Cascaded Flipflops and Setup/Hold/Propagation Delays
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
Clock
Q0
Q1
IN
Cascaded Flipflops
Are the Setup and Hold Times met?
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
Clock
Q0
Q1
IN
Q0: Input is IN
Setup and ho ldtimes are metif the inpu t, IN,does not changewithin the vali dregion orwindo w.
Cascaded Flipflops
Are the Setup and Hold Times met?
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
Clock
Q0
Q1
IN
Q1: Input is Q0
Wait!
Q0 is changingright at the clockedge. Won’t thisviolate the holdtime of Q1?
Does it violatethe setup time ofQ1?
Cascaded Flipflops
Are the Setup and Hold times of Q1 met?
Q1
IN
Q0
T plh
T h
T phl
T h
As long as Tplh > Th and Tphl > Th
Cascaded Flipflops
Are the Setup and Hold times of Q1 met?
Q1
IN
Q0
T plh
T h
T phl
T h
If Tplh < Th or Tphl < Th, there is a hold time violation!
Cascaded Flipflops
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
Clock
Q0
Q1
?
How fast can you clock this circuit?
T clk
Cascaded Flipflops
IN
CLK
Q0 Q1D
C
Q
Q
D
C
Q
Q
Clock
Q0
Q1
Tclk > Tp + Tsetup
How fast can you clock this circuit?
T plh
T setup
Clock Skew
• Proper operation o f synchronou s sys temsrequires that all registered elements are clockedat the same time
• Some times this is not possible - the clock seen atone flip-flop may be slightly delayed with respectto the clock at another flip-flop
• The relative delay of the clock is called clockskew
Clock Delay
IN
CLK0
Q0 Q1D
C
Q
Q
D
C
Q
Q
∆∆ CLK1
Clock Skew
CLK1 is a delayed version of CLK0 (delayedby the clock skew, δδ)
Q0
IN
IN
CLK0
Q0 Q1D
C
Q
Q
D
C
Q
Q
∆∆ CLK1
CLK0
CLK1 δ
Clock Skew
Are the Setup and Hold Times of Q1 met?
Q0
IN
IN
CLK0
Q0 Q1D
C
Q
Q
D
C
Q
Q
∆∆ CLK1
CLK0
CLK1 δ
Clock Skew
How do we guarantee proper operation?
Q0
IN
IN
CLK0
Q0 Q1D
C
Q
Q
D
C
Q
Q
∆∆ CLK1
CLK0
CLK1 δ
Th
Tsu
Clock Skew
Are the Setup and Hold times of Q1 met?
IN
Q0
T plh
T phl
To insure hold-time constraints are met,Tskew + Thold < Tprop, or Tskew < Tprop - Thold
Setup time will be guaranteed if hold-time constraints are met
CLK0
CLK1 Th
Tδ
Ts
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Timing in Synchronous Systems
The maximum clock rate (i.e. minimum clock period) is determined by
the longest path from the output of a flip-flop to an input of a flip flop(Q to D). We need to evaluate all Q to D paths and determine the paththat takes the longest time.
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Moore Machine - Review
• State Flip-Flops
• Input Forming Logic (IFL)
• Output Forming Logic (OFL)
What are the Critical Paths?
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Critical Path #1
1. Output of state flip-flops, through the IFL, and back into the FFs• FF propagation, IFL propagation, and FF setup time
Tp_ff + Tp_ifl + Tsu
There may be multiple paths between the state FFs, throughthe IFL and back into the FFs. You need to identify the longest(i.e. slowest) path.
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Critical Path #2
2. Inputs signals through the IFL and into the FFs• Input delay, IFL propagation, and FF setup time
Tinput + Tp_ifl + Tsu
State Machine Timing
Input Delay • specifies the maximum delay of a synchronous input
relative to the clock edge.
Input
Tinput
CLK
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Moore Machine - Critical Path#1 - FF, IFL, FF (Q to D)#2 - Input, IFL, FF
You must identify the longest critical path!
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Moore Machine - Output Timing
When is the output signal valid?
State Machine Timing
InputForming
Logic
OutputForming
Logic
Inputs NS CS clrcnt
Moore Machine - Output Timing
When is the output signal valid?
Tp_ff + Tp_ofl
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Tp_fl
40 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
40 + 22 + 22 ns
Tp_fl + Tp_ifl
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
40 + 22 + 22 + 20 = 104 ns
Tp_fl + Tp_ifl + Tsu
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
35 ns
Tinput
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
35 + 22 + 22 ns
Tinput + Tp_ifl
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
35 + 22 + 22 + 20 = 99 ns
Tinput + Tp_ifl + Tsu
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Feedback Path: 104 nsInput Path: 99 ns
Critical Path: 104 ns (9.6 MHz)
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Timing
Tp_fl
40 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Timing
Tp_fl + Tp_ofl
40 + 22 = 62 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path: 62 ns
Critical Path: 104 ns (9.6 MHz)
State Machine Timing
Input/OutputForming
Logic
Inputs NS CS
Mealy Machine - Critical Path Same as the Moore Machine#1 - FF, IFL, FF (Q to D)#2 - Input, IFL, FF
Outputs
State Machine Timing
Input/OutputForming
Logic
Inputs NS CS
Mealy Machine - Critical Path Same as the Moore Machine#1 - FF, IFL, FF (Q to D)#2 - Input, IFL, FF
Outputs
Tp_ff + Tp_ifl + Tsu
State Machine Timing
Input/OutputForming
Logic
Inputs NS CS
Mealy Machine - Critical Path Same as the Moore Machine#1 - FF, IFL, FF (Q to D)#2 - Input, IFL, FF
Outputs
Tinput + Tp_ifl + Tsu
State Machine Timing
Input/OutputForming
Logic
Inputs NS CS
Mealy Machine - Output Timing#1 - FF, OFL#2 - Input, OFL
Outputs
Tinput + Tp_ofl
State Machine Timing
Input/OutputForming
Logic
Inputs NS CS
Mealy Machine - Output Timing#1 - FF, OFL#2 - Input, OFL
Outputs
Tp_ff + Tp_ofl
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Critical Path: 104 ns (9.6 MHz)
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path
Tp_ff
40 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path
Tp_ff + Tp_ofl
40 + 22 = 62 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path
Tinput
35 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path
Tinput + Tp_ofl
35 + 22 = 57 ns
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
A
ZB
B
A
X
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Output Path
62 ns
Critical Path: 104 ns (9.6 MHz)
State Machine Timing
Example
AD Q
Q
D Q
Q
B
BCLK
AZB
A
B
Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max)25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max)10 ns (min)
Tplh 22 ns (max)10 ns (min)
Tphl 40 ns (max)20 ns (min)
Tphl 15 ns (max)8 ns (min)
Cou
nter
clr
S3
S2
S1
S0
