Zhao Xiusheng INET, Tsinghua University Beijing 100084, China zhaoxs@tsinghua
Time-Domain Segmentation based Massively Parallel Simulation Bichen Wu Dept. Micro/nano electronics...
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Transcript of Time-Domain Segmentation based Massively Parallel Simulation Bichen Wu Dept. Micro/nano electronics...
Time-Domain Segmentation based Massively Parallel Simulation
Bichen WuDept. Micro/nano electronicsTsinghua Univ., Beijing, ChinaEmail:[email protected]: +86 152 1056 0855
Background• On the one hand, transient circuit simulation is time
consuming• Sigma-Delta ADC: 71h• SAR ADC: 41h• FLASH ADC: 38h• PLL: 148h
• On the other hand, we got strong parallel computing resource• Many core, distributed computing
• How can we increase the circuit simulation efficiency with parallel computing?
Circuit simulation Transient circuit simulation is to solve the
initial condition problem of the following differential equation
Backward Euler was used to convert the above to sequence of discrete equations
Previous parallel circuit simulation Domain decompositionA New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level ( 1996 )
Parallel numerical integral methodWavePipe: Parallel Transient Simulation of Analog and Digital Circuits on Multi-Core Shared-Memory Machines(DAC 2008)
Multi-algorithm parallelHierarchical Multi-algorithm Parallel Circuit Simulation (TCAD 2011)
Time domain segmentation based parallel simulation
Method descriptiont0 tend
t0
t1
t2
Time domain segmentation based parallel simulation
In general, solution of equation is dependent on initial condition
Uncertainty brought by time domain segmentation may leads to erroneous result
Short memory assumption
Short memory : the state of the circuit at a certain time point is correlated only to the a limited history of the the input as well as the internal state of the circuit.
Circuits such as ADC , possess short memory property
A
D
Analog input
Digital output
Calculating SNDR through transient simulation for ADC
A
DAnalog input
Digital output
Fourier Transfor
m Power spectrum density
Two examples5bits FLASH ADC Fsam=3.75GHz, Ttotal=2us, Tov=6ns
Time for serial simulation : 38hNumber of segmentation : 1 , 2 , 4 , 8 , 100
6bits SAR ADC Fsam=2GHz, Ttotal=8us, Tov=13.3ns
Time for serial simulation : 41hNumber of segmentation : 1 , 2 , 4 , 8 , 100
Transient simulation for ADCPower spectrum density of FLASH ADC(left) and SAR ADC ( right ) output, with serial and parallel simulation
FLASH SAR
Transient simulation for ADC
Result
Transient simulation for Sigma-Delta ADC
Sigma-Delta modulatorBecause of integrator, it’s not short memory
Transient simulation for Sigma-Delta ADC
Direct segmentation with the modulator output of modulator brings erroneous result
Time domain deviation between serial and parallel result
Frequency domain deviation between serial and parallel result
Transient simulation for Sigma-Delta ADC
Uncertainty brought by time domain segmentation
Transient simulation for Sigma-Delta ADC
Digital filter realized in
matlab
Solution:
Transient simulation for Sigma-Delta ADC
Result showed efficiency enhancement with high accuracy
Transient simulation for PLL
Phase lock loop(PLL) is not short memory circuit Self-driven system Integral property
f[ ] h(t)+-
Transient simulation for PLL
Phase lock loop(PLL)The expression of the phase growth in the equation above is as follow.
Let
So we get:
Transient simulation for PLL
Phase lock loop(PLL)
Transient noise analysis
PSD of 1/f noise generated in serial and parallel
Parallel:
Serial
The bandwidth gets wider
Transient noise analysis
1/f noise in TDSM
serial parallel
Summary We proposed TDSM for transient circuit simulation
Testified on FLASH , SAR , Sigma-Delta ADC
Maximum 78X acceleration with 100 cores parallelization
Efficient for phase noise simulation for PLL, testified by behavior model.
Proposed 1/f noise generator that support TDSM,
testified on a single transistor
Now submitted to DAC 2013