TILERA TILE64

BY :IBRAHEM BATTA

EMAD SHAKHSHEER

To Dr. SAMER ARANDI

15 min

OBJECTIVE:

Construct a basic knowledge about the

tile64 and its architecture.

SECTIONS:

- WHAT IS TILE64 ?

- APPLICATIONS

- BASIC ARCHITECTURE.

- WHAT IS TILE ?

- IMISH

- TAPERED FAT TREE TOPOLOGY

- MEMORY MODEL

- POWERMODEL

- HARDWALL TECHNOLOGY

- REFERANCES

What is TILERA TILE64 ?

• The name for the first processor in the family of Tile Processor chips from Tilera Corporation.

• The TILE64 processor is based on an architecture that can scale to hundreds, or even thousands of cores.

• The processor contains 64 full-featured, programmable cores, each capable of running its own operating system.

Cont.

• Tilera's architecture eliminates the on-chip bus interconnect by :

• placing a communications switch on each processor core

• arranging Cores in a grid fashion.

• homogeneous cores.

• Each of the 64 cores is a general-purpose processor that includes L1 5MB and L2 caches, as well as an innovative distributed L3 cache.

TILE64 applications and uses.

• Advanced networking:

• Unified Threat Management (UTM).

• Network Security Appliances.

• Deep Packet Inspection (DPI) is a networking technology that Internet Service Providers use to monitor customers' data traffic

• Network Monitoring.

Cont.

• Digital Video:

• Video Conferencing.

• Video-on-Demand (VoD) Servers, IPTV technology

• Video Surveillance. is the monitoring of the

behavior.

• Media ‘Head-End’ Services.

Cont.

• Cloud Computing applications such as web

indexing, search engine and cache acceleration

servers

ARCHITECTURE -TILES

x5

Cont.

• TILES:

• non-blocking switch.

• Each tile uses a fully connected

• crossbar all-to-all five-way communication.

Cont.

Cont.

• Using multiple processors require a system to allow communication among them.

• Old Solution: bus interconnection.

• Problem: more cores added to chips bus creates data congestion, limiting performance scalability with the increased number of cores.

• Tilera’s solution: iMesh.

Cont. iMESH

iMesh:

• user dynamic network (UDN).

• I/O dynamic network (IDN).

• static network (STN).

• memory dynamic network (MDN).

• tile dynamic network (TDN).

Cont.

• Five physical mesh networks

• UDN, IDN, SDN, TDN, MDN

• TDN and MDN are used for handling memory traffic.

• Memory requests transit TDN

• Large store requests, small load requests

Cont.

• Memory responses transit MDN

• Large load responses, small store responses

• Includes cache-to-cache transfers and off-chip transfers.

• MIMD processor.

TAPERED FAT-TREE

Good for many-to-few connectivity

• Fewer hops Shorter latency

• Fewer routers Less power, less area

TILE64 WITH TAPERED FAT TREE

Legend

- Level 3 Routers

- Level 2 Routers

- Level 1 Routers(Connect to memory controllers)

Tapered fat-tree topology (TFT)

• Physical design of the tapered fat-tree is more

difficult.

• The TFT topology can reduce memory latency

and power dissipation for many-core systems

MEMORY MODEL

• Directory-based cache coherence.

• Directory cache at every node.

• Off-chip directory controller.

• Tile-to-tile requests and responses transit the TDN.

• Off-chip memory requests and responses transit the MDN.

POWER MODEL

• Like the CELL processor, unused tiles (cores) can be put into a sleep mode to. further decrease power consumption

• 500MHz – 866MHz operating frequency.

• ClearSpeed MTAP Co-processor.

• 15 – 22W @ 700MHz all cores active.

• Lower operating cost.

Multicore coherent cache

• Cache subsystem high performance, two-level,

nonblocking ,cache hierarchy.

• Each tile's cache can be shared with other tiles

each tile can access the aggregate multi-megabyte

cache.

Cont.

• Each tile can view the collection of on-chip caches of all

tiles, serving as an L3 cache.

• Neighborhood caching to provide an on-chip distributed

shared cache.

Cont.

Multicore Hardwall Technology

• Enables the user to define one or many cores as

a processing island, eliminating communication

between it and other cores unless specified.

• If a packet attempts to cross the established

boundary, an interrupt is signaled and control is

passed on to the hypervisor. the established

boundary, an interrupt is signaled and control is

passed on to the hypervisor.

Cont.

RESULT !

REF.

• http://www.webopedia.com/TERM/T/Tile64.html

• http://www.cs.berkeley.edu/~kubitron/courses/cs258-

S08/projects/reports/project2_talk.ppt

• http://www.csa.com/discoveryguides/multicore/revie

w4.php

• http://www.tilera.com/about_tilera/press-

releases/tilera-announces-production-availability-

tile64%E2%84%A2-processor

• http://www.tilera.com/sites/default/files/productbriefs/

PB010_TILE64_Processor_A_v4.pdf

• http://home.dei.polimi.it/silvano/FilePDF/ARC-

MULTIMEDIA/Presentation_Tilera_Tile64.pdf

• http://en.wikipedia.org/wiki/Tilera