Ti Pci1250
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PCI1250APC CARD CONTROLLER
XCPS014 DECEMBER 1997
1POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Peripheral Component Interconnect (PCI)Power Management Compliant
DACPI 1.0 Compliant
D Packaged in 256-Pin BGA
DPCI Local Bus Specification Revision 2.1
CompliantD 1995 PC Card Standard Compliant
D3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-VPCI Signaling Environments
D Mix-and-Match 5-V/3.3-V PC Card16 Cardsand 3.3-V CardBus Cards
D Supports Two PC Card or CardBus SlotsWith Hot Insertion and Removal
D Uses Serial Interface to TI TPS2206 DualPower Switch
D Supports Burst Transfers to Maximize DataThroughput on Both PCI Buses
D Supports Serialized Interrupt request (IRQ)With PCI Interrupts
D 8-Way Legacy IRQ Multiplexing
DSystem Interrupts Can Be Programmed as
PCI Style or Industry Standard Archeticture(ISA-IRQ) Style
D ISA-IRQ Interrupts Can Be Serialized Ontoa Single IRQ Serial (IRQSER) Pin
D EEPROM Interface for Loading SubsystemID and Subsystem Vendor ID
D Pipelined Architecture Allows Greater Than130M-Bytes-Per-Second Throughput FromCardBus to PCI and From PCI to CardBus
D Supports Zoom Video With InternalBuffering
DProgrammable Output Select for CLKRUN
D Four General Purpose I/Os
DMultifunction PCI Device With Separate
Configuration Space for Each SocketD Five PCI Memory Windows and Two I/O
Windows Available for Each PC Card16Socket
D Two I/O Windows and Two MemoryWindows Available to Each CardBusSocket
D Exchangeable Card Architecture (ExCA)Compatible Registers Are Mappable inMemory and I/O Space
D Supports Distributed DMA (DDMA) andPC/PCI DMA
D Intel 82365SL-DF Register Compatible
DSupports 16-Bit DMA on Both PC Card
Sockets
DSupports Ring Indicate, SUSPEND, PCI
CLKRUN, and CardBus CCLKRUN
DAdvanced Submicron, Low-Power CMOS
Technology
D Provides VGA/Palette Memory and I/O andSubtractive Decoding Options
D LED Activity Pins
D Supports PCI Bus Lock (LOCK)
D For the Complete Data Sheet for PCI1250A,Please See Literature #SCPS014B
Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Functions 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 17. . . . . . . . . . . . . . . . . . . .
Electrical Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock/Reset Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . .
PCI Timing Requirements 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information 20. . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information 21. . . . . . . . . . . . . . . .
PC Card Cycle Timing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.
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PCI1250APC CARD CONTROLLERXCPS014 DECEMBER 1997
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description
The TI PCI1250A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports twoindependent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1250A provides a richfeature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktopcomputers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA
Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. ThePCI1250A supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or3.3 V, as required.
The PCI1250A is compliant with the latest PCI Bus Power Management Specification. It is also compliant withthe PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slavedevice. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers orCardBus PC Card bridging transactions.
Multiple system-interrupt signaling options are provided and they include:
D Parallel PCI interrupts
DParallel ISA interrupts
DSerialized ISA interrupts
D Serialized ISA and PCI interrupts
Additionally, general-purpose inputs and outputs are provided for the board designer to implement sidebandfunctions.
All card signals are internally buffered to allow hot insertion and removal without external buffering. ThePCI1250A is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1250A internal data pathlogic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustainedbursting. The PCI1250A can also be programmed to accept fast posted writes to improve system-bus utilization.
The PCI1250A provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC boardmanufacturers to add a ZV-compatible solution and guarantees compliance with the CardBus loadingspecifications. Many other features are designed into the PCI1250A, such as socket activity light-emitting diode
(LED) outputs, and are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve lowsystem-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enablethe host power management system to further reduce power consumption.
Unused PCI1250A inputs must be pulled up using a 43 k W resistor.
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system block diagram
A simplified system block diagram using the PCI1250A is provided below. The zoomed video (ZV) capabilitycan be used to route the ZV data directly to the VGA controller.
The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interfaceincludes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV)
is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.
The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.The ring indicate terminal is included in the interrupt interface because its function is to perform system wakeup on incoming PC Card modem rings. Other miscellaneous system interface terminals are available on thePCI1250A that include:
D Programmable general purpose multifunction terminalsD SUSPEND, RI_OUT/PME (power management control signal)D SPKROUT.
PCI Bus
PCI1250A
Activity LEDs
South Bridge
IRQSER
Embedded
Controller
DMA
PME
68
23 for ZV(See Note)
PC Card
Socket A
TPS2206
Power
Switch 3
PC Card
Socket B
VGA
Controller
Zoom Video
19 Video
4 Audio
CLKRUN
Interrupt Routing Options:
1) Serialized, including PCI and ISA
2) Serialized ISA and parallel PCI
3) Parallel PCI and parallel ISA
4) Parallel PCI interrupts only
ZVEnable
23 for ZV
68
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video
mode 23 pins are used for routing the zoomed video signals too the VGA controller.
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terminal groups and locations
GFN PACKAGE
(BOTTOM VIEW)
P P P P P P P
P P P P P P P
P P P P P P P
Z Z Z Z Z
P
P P P P
P P P P
P P P P
P P P P
P P P
P P P
P P P
P P P P
P P P P
C
C C
C C C C
C C C
C
C C C
C C C C C C C C
C C C C C C C C
C C CC
C C C C
C C C
C C C C
C C C C
C C C C
C C C
C C C
C C C C
C C C
C C C
C C C C
C C C C
C C C C C C C C C C C C
C C C C C C C C C C C C
C C C C C C C C C C C C
C C C
C C C
C C
C C C C C
Z Z Z Z Z Z
Z Z Z Z Z Z Z
Z Z Z
Z Z Z Z
Z Z Z
Z
ZZ
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
P
C
Z
VCC
GND
Power Switch
Interrupt and Miscellaneous PCI Signals
CardBus Signals
Zoom Video Signals
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Terminal Functions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. Theterminal numbers are also listed for convenient reference.
power supply
TERMINAL
NAME NO.
GND
A1, D4, D8, D13, D17, H4,
H17, N4, N17, U4, U8, U13,
U17
Device ground terminals
VCCD6, D11, D15, F4, F17, K4,
L17, R4, R17, U6, U10, U15Power supply terminal for core logic (3.3 V)
VCCA K2, R3, W5 Rail power input for PC Card A interface. Indicates Card A signaling environment.
VCCB B16, C10, F18, Rail power input for PC Card B interface. Indicates Card B signaling environment.
VCCI V10
Rail power input for interrupt subsystem interface and miscellaneous I/O. Indicates signaling level
of the following inputs and shared outputs: IRQSER, PCGNT, PCREQ, SUSPEND, SPKROUT,
GPIO1:0, IRQMUX7IRQMUX0, INTA, INTB, CLOCK, DATA, LATCH, and RI_OUT.
VCCP K20, P18, V15, W20 Rail power input for PCI signaling (3.3 V or 5 V)
VCCZ A4, D1 Rail power input for zoom video interface (3.3 V or 5 V)
PCI system
TERMINAL I/O
NAME NO. TYPE
CLKRUN J18 I/OPCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow
it down, and the PCI1250A responds accordingly.
PCLK J17 IPCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PRST J19 I
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1250A to place all output buffers in a
high-impedance state and reset all internal registers. When PRST is asserted, the device is completely
nonfunctional. After PRST is deasserted, the PCI1250A is in its default state. When the SUSPEND mode isenabled, the device is protected from the PRST, and the internal registers are cleared. All outputs are placed in
a high-impedance state, but the contents of the registers are preserved.
PC Card power switch
TERMINAL I/O
NAME NO. TYPE
CLOCK U12 I/O
3-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK
defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the system control
register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines
this terminal as an output, CLOCK requires an external pullup resistor. The frequency of the PCI1250A output
CLOCK is derived by dividing the PCI CLK by 36.
DATA V12 O 3-line power switch data. DATA is used to serially communicate socket power-control information to the powerswitch.
LATCH W12 O3-line power switch latch. LATCH is asserted by the PCI1250A to indicate to the PC Card power switch that the
data on the DATA line is valid.
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Terminal Functions (Continued)
PCI address and data
TERMINAL I/O
NAME NO. TYPE
AD31AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1AD0
K18K19
L20
L18
L19
M20
M19
M18
N19
N18
P20
P19
R20
R19
P17
R18V18
Y19
W18
V17
U16
Y18
W17
V16
W16
U14
Y16
W15
V14
Y15
W14Y14
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface.
During the address phase of a primary bus PCI cycle, AD31AD0 contain a 32-bit address or other destination
information. During the data phase, AD31AD0 contain data.
C/BE3
C/BE2
C/BE1
C/BE0
M17
T20
W19
Y17
I/O
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary bus PCI cycle, C/BE3C/BE0 define the bus command. During the data phase, this
4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0 applies to byte 0 (AD7AD0), C/BE1 applies to byte 1 (AD15AD8), C/BE2 applies to
byte 2 (AD23AD16), and C/BE3 applies to byte 3 (AD31AD24).
PAR Y20 I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI1250A calculates even parity across the AD31AD0
and C/BE3C/BE0 buses. As an initiator during PCI cycles, the PCI1250A outputs this parity indicator with a
one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiators parity indicator.
A compare error results in the assertion of a parity error (PERR).
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Terminal Functions (Continued)
PCI interface control
TERMINAL I/O
NAME NO. TYPE
DEVSEL V20 I/OPCI device select. The PCI1250A asserts DEVSEL to claim a PCI cycle as the target device. As a PCIinitiator on the bus, the PCI1250A monitors DEVSEL until a target responds. If no target responds before
timeout occurs, the PCI1250A terminates the cycle with an initiator abort.
FRAME T19 I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is
deasserted, the PCI bus transaction is in the final data phase.
GNT J20 I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1250A access to the PCI bus after the
current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the
PCI bus parking algorithm.
GPIO2/LOCK V19 I/O
PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI LOCK and used
to gain exclusive access downstream. Since this functionality is not typically used, a general-purpose I/O
may be accessed through this terminal. GPIO2/LOCK defaults to a general-purpose input and can be
configured through the GPIO2 control register.
IDSEL N20 IInitialization device select. IDSEL selects the PCI1250A during configuration space accesses. IDSEL can
be connected to one of the upper 24 PCI address lines on the PCI bus.
IRDY T18 I/O
PCI initiator ready. IRDY indicates the PCI bus initiators ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted.
Until IRDY and TRDY are both sampled asserted, wait states are inserted.
PERR U18 I/OPCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR is enabled through bit 6 of the command register.
REQ K17 O PCI bus request. REQ is asserted by the PCI1250A to request access to the PCI bus as an initiator.
SERR U19 O
PCI system error. SERR is an output that is pulsed from the PCI1250A when enabled through the command
register, indicating a system error has occurred. The PCI1250A need not be the target of the PCI cycle to
assert this signal. When SERR is enabled in the bridge control register, this signal also pulses, indicating
that an address parity error has occurred on a CardBus interface.
STOP T17 I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not
support burst data transfers.
TRDY U20 I/O
PCI target ready. TRDY indicates the primary bus targets ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted.
Until both IRDY and TRDY are asserted, wait states are inserted.
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Terminal Functions (Continued)
system interrupt
TERMINAL I/O
NAME NO. TYPE
GPIO3/INTA V13 I/OParallel PCI interrupt. GPIO3/INTA can be connected to an available PCI interrupt if parallel PCI interruptsare used, and the PCI1250A outputs PCI INTA through this terminal. GPIO3/INTA defaults to a
general-purpose input.
IRQSER/INTB W13 I/O
Serial interrupt signal/parallel PCI interrupt. When IRQSER/INTB is configured as IRQSER, it provides the
IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream.
IRQSER/INTB can be configured as the parallel PCI INTB interrupt. IRQSER/INTB defaults to IRQSER
because this is the default interrupt signaling method.
IRQMUX7
IRQMUX6
IRQMUX5
IRQMUX4
IRQMUX3
IRQMUX2
IRQMUX1
IRQMUX0
Y12
U11
W10
Y9
W9
V9
U9
Y8
O
Interrupt request/secondary functions multiplexed. The primary function of these terminals is to provide the
ISA-type IRQ signaling supported by the PCI1250A. These interrupt multiplexer outputs can be mapped to
any of 15 IRQs. The device control register must be programmed for the ISA IRQ interrupt mode and the
IRQMUX routing register must have the IRQ routing programmed before these terminals are enabled.
All of these terminals have secondary functions, such as PC/PCI DMA request/grant, ring indicate output,
and zoom video status, that can be selected with the appropriate programming of this register. When the
secondary functions are enabled, the respective terminals are not available for IRQ routing.
See the IRQMUX routing register for programming options.
RI_OUT/PME Y13 O
Ring indicate output/power management event. RI_OUT allows the RI input from a PC Card to pass through
to the system. This pin can be configured as the PME pin by setting bit 0 in the system control register. This
pin is RI_OUT when RIENB is enabled in the card control register and ExCA interrupt and general control
register. This pin is PME when RIENB is disabled and bit 1 of the system control register is 1.
IRQMUX4 or IRQMUX3 can be used to route the RI_OUT signal when the PME signal is routed on pin Y13
and a ring indicate signal is still required.
PC/PCI DMA
TERMINAL I/O
NAME NO. TYPE
PCGNT/
IRQMUX6U11 I/O
PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI
DMA scheme.Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output
of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over
PCGNT, and should not be enabled in a system using PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
PCREQ/
IRQMUX7Y12 O
PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system supporting the PC/PCI
DMA scheme.
Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7 interrupt output
of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over
PCREQ, and should not be enabled in a system using PC/PCI DMA.
This terminal is also used for the serial EEPROM interface.
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Terminal Functions (Continued)
zoom video
TERMINAL I/O AND MEMORY I/O
NAME NO.SIGNAL
TYPE
ZV_HREF A6 A10 O Horizontal sync to the zoom video port
ZV_VSYNC C7 A11 O Vertical sync to the zoom video port
ZV_Y7
ZV_Y6
ZV_Y5
ZV_Y4
ZV_Y3
ZV_Y2
ZV_Y1
ZV_Y0
A3
B4
C5
B5
C6
D7
A5
B6
A20
A14
A19
A13
A18
A8
A17
A9
O Video data to the zoom video port in YV:4:2:2 format
ZV_UV7
ZV_UV6
ZV_UV5
ZV_UV4ZV_UV3
ZV_UV2
ZV_UV1
ZV_UV0
D2
C3
B1
B2A2
C4
B3
D5
A25
A12
A24
A15A23
A16
A22
A21
O Video data to the zoom video port in YV:4:2:2 format
ZV_SCLK C2 A7 O Audio SCLK PCM
ZV_MCLK D3 A6 O Audio MCLK PCM
ZV_PCLK E1 IOIS16 O Pixel clock to the zoom video port
ZV_LRCLK E3 INPACK O Audio LRCLK PCM
ZV_SDATA E2 SPKR O Audio SDATA PCM
ZV_RSVD F1, F2, F3, G4 O Reserved. No connection.
ZV_RSV1
ZV_RSV0
C1
E4
A5
A4O
Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0 are
put into the high-impedance state by host adapter.
miscellaneous
TERMINAL I/O
NAME NO. TYPE
GPIO0/LEDA1 V11 I/O
GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output
indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose
input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal
through the GPIO0 control register. GPIO0/LEDA1 defaults to a general-purpose input.
GPIO1/LEDA2 W11 I/O
GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output
indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose
input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be
used for power switch overcurrent (OC) sensing. See GPIO1 control registerfor programming details.
GPIO1/LEDA2 defaults to a general-purpose input.
SPKROUT Y10 O
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the
PCI1250A from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR//CAUDIO inputs.
SUSPEND Y11 ISuspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See
SUSPEND modefor details.
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Terminal Functions (Continued)
16-bit PC Card address and data (slots A and B)
TERMINAL
NO. I/O
NAME SLOTA
SLOTB
TYPE
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
T4
U2
U1
P4
R2
R1
P1
N2
M4
T1
T2
P2
N3
T3
M1
L1
M3
N1
V1
V2
V3
W2
W3
W4
V4
U5
C14
B15
C15
C16
A18
C17
B18
A20
C18
A17
A16
B17
A19
D14
D18
E18
B20
B19
A15
A14
B13
A13
C12
A12
B11
C11
O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
K3
J2
J4
H2
G1
W8
Y7
V7
J1
J3
H1
H3
G2
V8
W7
Y6
E19
E20
G18
G19
H18
B7
C8
A8
G17
F19
F20
G20
H19
A7
B8
D9
I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.
Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25. Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.
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Terminal Functions (Continued)
16-bit PC Card interface control (slots A and B)
TERMINAL
NO. I/O
NAME SLOTA
SLOTB
TYPE
BVD1
(STSCHG/RI)V6 A9 I
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries.BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card.Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high,the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceableand the data in the memory PC Card is lost.
Status change. STSCHG is used to alert the system to a change in the READY, write protect, orbattery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
BVD2
(SPKR) Y5 D10 I
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries.BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card.Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, thebattery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceableand the data in the memory PC Card is lost.
Speaker. SPKR is an optional binary audio signal available only when the card and socket havebeen configured for the 16-bit I/O interface. The audio signals from cards A and B are combinedby the PCI1250A and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bitPC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.
CD1
CD2
G3
W6
H20
C9I
PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on thePC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low.
CE1
CE2
K1
L2
D20
D19O
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes.CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
INPACK Y1 D12 I
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycleat the current address.
DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bitPC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate arequest for a DMA operation.
IORD L4 E17 O
I/O read. IORD is asserted by the PCI1250A to enable 16-bit I/O PC Card data output during hostI/O read cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Cardthat supports DMA. The PCI1250A asserts IORD during DMA transfers from the PC Card to hostmemory.
IOWR M2 C19 O
I/O write.IOWR is driven low by the PCI1250A to strobe write data into 16-bit I/O PC Cards duringhost I/O write cycles.
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Cardthat supports DMA. The PCI1250A asserts IOWR during transfers from host memory to the PCCard.
OE L3 C20 O
Output enable. OE is driven low by the PCI1250A to enable 16-bit memory PC Card data outputduring host memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card
that supports DMA. The PCI1250A asserts OE to indicate TC for a DMA write operation. Terminal name for slot A is preceded with A_. For example, the full name for terminal Y1 is A_INPACK. Terminal name for slot B is preceded with B_. For example, the full name for terminal D12 is B_INPACK.
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Terminal Functions (Continued)
16-bit PC Card interface control (slots A and B) (continued)
TERMINAL
NUMBER I/O
NAME SLOTA
SLOTB
TYPE
READY
(IREQ)Y4 A10 I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket areconfigured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards toindicate that the memory card circuits are busy processing a previous write command. READY isdriven high when the 16-bit memory PC Card is ready to accept a new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device onthe 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when nointerrupt is requested.
REG Y2 B12 O
Attribute memory select. REG remains high for all common memory accesses. When REG isasserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD orIOWR active). Attribute memory is a separately accessed section of card memory and is generallyused to record card capacity and other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a16-bit PC Card that supports DMA. The PCI1250A asserts REG to indicate a DMA operation. REGis used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
RESET W1 C13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
WAIT V5 B10 IBus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) thememory or I/O cycle in progress.
WE P3 D16 O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is alsoused for memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supportsDMA. The PC1250 asserts WE to indicate TC for a DMA read operation.
WP
(IOIS16)U7 B9 I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protectswitch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card whenthe address on the bus corresponds to an address to which the 16-bit PC Card responds, and the
I/O port that is addressed is capable of 16-bit accesses.DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bitPC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMAoperation.
VS1
VS2
Y3
U3
A11
B14I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,determine the operating voltage of the 16-bit PC Card.
Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE. Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE.
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Terminal Functions (Continued)
CardBus PC Card interface system (slots A and B)
TERMINAL
NO. I/O
NAME SLOTA
SLOTB
TYPE
CCLK T1 A17 O
CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus
interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2:1, and
CVS2CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the
low state or slowed down for power savings.
CCLKRUN U7 B9 OCardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the
CCLK frequency, and by the PCI1250A to indicate that the CCLK frequency is decreased.
CRST W1 C13 I/O
CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers,
and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-stated,
and the PCI1250A drives these signals to a valid logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.
Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK. Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.
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Terminal Functions (Continued)
CardBus PC Card address and data (slots A and B)
TERMINAL
NO. I/O
NAME SLOTA
SLOTB
TYPE
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3CAD2
CAD1
CAD0
W8
Y7
W7
V7
Y6
U5
V4
W4
W3
W2
V3
V2
T4
V1
U2
M4
M2
M3
L4
M1
L3
L2
L1
K3
J1
J4
J3
H2
H1G1
H3
G2
B7
C8
B8
A8
D9
C11
B11
A12
C12
A13
B13
A14
C14
A15
B15
C18
C19
B20
E17
D18
C20
D19
E18
E19
G17
G18
F19
G19
F20H18
G20
H19
I/O
PC Card address and data. These signals make up the multiplexed CardBus address and data bus on
the CardBus interface. During the address phase of a CardBus cycle, CAD31CAD0 contain a 32-bit
address. During the data phase of a CardBus cycle, CAD31CAD0 contain data. CAD31 is the
most-significant bit.
CC/BE3
CC/BE2
CC/BE1
CC/BE0
Y2
T3
N1
K1
B12
D14
B19
D20
I/O
CardBus bus commands and byte enables. CC/BE3CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3CC/BE0 defines the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7CAD0), CC/BE1
applies to byte 1 (CAD15CAD8), CC/BE2 applies to byte 2 (CAD23CAD8), and CC/BE3 applies to
byte 3 (CAD31CAD24).
CPAR N3 A19 I/O
CardBus parity. In all CardBus read and write cycles, the PCI1250A calculates even parity across the
CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1250A outputs CPAR with a
one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiators
parity indicator; a compare error results in a parity error assertion.
Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR. Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR.
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Terminal Functions (Continued)
CardBus PC Card interface control (slots A and B)
TERMINAL
NO. I/O
NAME SLOTA
SLOTB
TYPE
CAUDIO Y5 D10 ICardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
PCI1250A supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CBLOCK P1 B18 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1 G3 H20CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CCD2 W6 C9CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card
type.
CDEVSEL R2 A18 I/OCardBus device select. The PCI1250A asserts CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the PCI1250A monitors CDEVSEL until a target responds.
If no target responds before t imeout occurs, the PCI1250A terminates the cycle with an initiator abort.
CFRAME U1 C15 I/OCardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is
asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT P3 D16 ICardBus bus grant. CGNT is driven by the PCI1250A to grant a CardBus PC Card access to the
CardBus bus after the current data transaction has been completed.
CINT Y4 A10 ICardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from
the host.
CIRDY T2 A16 I/O
CardBus initiator ready. CIRDY indicates the CardBus initiators ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
CPERR P2 B17 I/OCardBus parity error. CPERR is used to report parity errors during CardBus transactions, except
during special cycles. It is driven low by a target two clocks following that data when a parity error
is detected.
CREQ Y1 D12 ICardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.
CSERR V5 B10 I
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak
pullup, and may take several CCLK periods. The PCI1250A can report CSERR to the system by
assertion of SERR on the PCI interface.
CSTOP R1 C17 I/OCardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target
devices that do not support burst data transfers.
CSTSCHG V6 A9 ICardBus status change. CSTSCHG is used to alert the system to a change in the cards status, and
is used as a wake-up mechanism.
CTRDY P4 C16 I/OCardBus target ready. CTRDY indicates the CardBus targets ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY
and CTRDY are asserted; until this time, wait states are inserted.
CVS1 Y3 A11 CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunctionpCVS2 U3 B14 w t an to ent y car nsert on an nterrogate car s to eterm ne t e operat ng
voltage and card type.
Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO. Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.
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absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Supply voltage range, VCCP,VCCA,VCCB,VCCZ,VCCI 0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage range, VI: PCI 0.5 V to VCCP + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Card A 0.5 to VCCA + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Card B 0.5 to VCCB
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ZV 0.5 to VCCZ + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MISC 0.5 to VCCI + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Fail safe 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO: PCI 0.5 V to VCCP + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Card A 0.5 to VCCA+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Card B 0.5 to VCCB + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ZV 0.5 to VCCZ + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MISC 0.5 to VCCI + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Fail safe 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage temperature range, Tstg 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual junction temperature, TJ 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with
respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals are measured with
respect to VCCZ, and miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition.
2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured
with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCA or VCCB. ZV terminals are measured
with respect to VCCZ, and miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition.
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recommended operating conditions (see Note 3)
OPERATION MIN NOM MAX UNIT
VCC Core voltage Commercial 3.3 V 3 3.3 3.6 V
3.3 V 3 3.3 3.6CCP vo tage
5 V 4.75 5 5.25
3.3 V 3 3.3 3.6CC(A/B) ar vo tage
5 V 4.75 5 5.25
p3.3 V 3 3.3 3.6
CCZ port vo tage5 V 4.75 5 5.25
3.3 V 3 3.3 3.6CCI sce aneous vo tage
5 V 4.75 5 5.25
3.3 V 0.5 VCCP VCCP
5 V 2 VCCP
PC Card3.3 V
0.475
VCCA/BVCCA/B
VIH High-level input voltage 5 V 2.4 VCCA/BV
ZV 2 VCCZ
MISC 2 VCCI
Fail safe 2 VCC
3.3 V 0 0.3 VCCP
5 V 0 0.8
PC Card3.3 V 0
0.325
VCCA/BVIL Low-level input voltage 5 V 0 0.8
V
ZV 0 0.8
MISC 0 0.8
Fail safe 0 0.8
PCI 0 VCCP
PC Card 0 VCCA/B
VI Input voltage ZV 0 VCCZ V
MISC 0 VCCI
Fail safe 0 VCC
PCI 0 VCCP
PC Card 0 VCCA/B
VO Output voltage ZV 0 VCCZ V
MISC 0 VCCI
Fail safe 0 VCC
Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous pins are V13, W13, Y13, U12, V12, W12, U11, V11, W11, Y11, Y10, W10, Y09, W09, V09, U09, Y08, all IRQMUXx pins, LEDAx
pins, SUSPEND, SPKROUT, RI_OUT, INTA, INTB, and power switch control pins. Fail-safe pins are A11, B14, C09, G03, H20, U03, W06, and Y03 (card detect and voltage sense pins). Applies to external output buffers
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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recommended operating conditions (see Note 3) (continued)
OPERATION MIN NOM MAX UNIT
Input transition time PCI and PC Card 1 4t (tr and tf) ZV, miscellaneous, and fail safe 0 6
TA Operating ambient temperature range 0 25 70 C
TJ Virtual junction temperature 0 25 115 C
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT
3.3 V IOH = 0.5 mA 0.9 VCCP I
5 V IOH = 2 mA 2.4
3.3 V IOH = 0.15 mA 0.9 VCCOH High-level output voltage (see Note 4) PC Card
5 V IOH = 0.15 mA 2.4
ZV IOH = 4 mA VCC0.6
MISC IOH = 4 mA VCC0.6
3.3 V IOL = 1.5 mA 0.1 VCCP I
5 V IOL = 6 mA 0.55
3.3 V IOL = 0.7 mA 0.1 VCC
VOL Low-level output voltagePC Card
5 V IOL = 0.7 mA 0.55 V
ZV IOL = 4 mA 0.5
MISC IOL = 4 mA 0.5
SERR IOL = 12 mA 0.5
3-state output, high-impedance statep p
3.6 V VI = VCC 1OZL current (see Note 4)
u pu p n s5.25 V VI = VCC 1
3-state output, high-impedance state
p p
3.6 V VI = VCC 10
OZH current u pu p n s 5.25 V VI = VCC 25
Input pins VI = GND 1
IIL Low-level input current I/O pins VI = GND 10 A
Latch VI = GND 2
p p3.6 V VI = VCC
10npu p ns
5.25 V VI = VCC 20
IIH High-level input current (see Note 5)p
3.6 V VI = VCC 10 A
p ns5.25 V VI = VCC
25
Fail-safe pins 3.6 V VI = VCC 10
For PCI pins, VI = VCCP. For PC Card pins, VI = VCC(A/B). For ZV pins, VI = VCCZ. For miscellaneous pins, VI = VCCI. For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.
NOTES: 4. VOH and IOL are not tested on SERR (pin U19)and RI_OUT (pin Y13) because they are open-drain outputs.5. IIH is not tested on LATCH (pin W12) because it is pulled up with an internal resistor.
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PCI clock/reset timing requirements over recommended ranges of supply voltage and operatingfree-air temperature (see Figures 20 and 21)
PARAMETERALTERNATE
SYMBOL
TEST
CONDITIONSMIN MAX UNIT
tc Cycle time, PCLK tcyc 30 ns
twH Pulse duration, PCLK high thigh 11 nstwL Pulse duration, PCLK low tlow 11 ns
v/t Slew rate, PCLK tr, tf 1 4 V/ns
tw Pulse duration, RSTIN trst 1 ms
tsu Setup time, PCLK active at end of RSTIN trst-clk 100 m s
PCI timing requirements over recommended ranges of supply voltage and operating free-airtemperature (see Note 4 and Figures 19 and 22)
PARAMETERALTERNATE
SYMBOLTEST CONDITIONS MIN MAX UNIT
Propagation delay time,
PCLK-to-shared signal
valid delay timetval
p
11
pd See Note 6 PCLK-to-shared signal
invalid delay timetinv
L = p , ee o e2
ns
tenEnable time,
high impedance-to-active delay time from PCLKton 2 ns
tdisDisable time,
active-to-high impedance delay time from PCLKtoff 28 ns
tsu Setup time before PCLK valid tsu 7 ns
th Hold time after PCLK high th 0 ns
6. PCI shared signals are AD310, C/BE30, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
NOTES: 7. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the
type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time,
tsu = setup time, and th = hold time.
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PARAMETER MEASUREMENT INFORMATION
CLOAD includes the typical load-circuit distributed capacitance.
CLOAD
Test
Point
Timing
Input
(see Note A)
Out-of-Phase
Output
tpd
50% VCC
50% VCC
VCC
0 V
0 V
0 V
0 V
0 V
VOL
thtsu
VOH
VOH
VOL
High-Level
Input
Low-Level
Input
tw
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
tpdtpd
tpd
VLOAD
IOH
IOL
From Output
Under Test
90% VCC10% VCC
tftr
Output
Control
(low-level
enabling)
Waveform 1
(see Notes
Band C)
Waveform 2
(see Notes B
and C)
VOL
VOHVOH 0.3 V
tPZL
tPZH
tPLZ
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOL + 0.3 V
0 V
0 V
50% VCC
50% VCC
ten
tdis
tpd
tPZH
tPZLtPHZ
tPLZ
CLOAD
(pF)
IOL(mA)
TIMING
PARAMETER
50 8 8
0
3
1.5
50 8
8
8
8
LOAD CIRCUIT PARAMETERS
= 50 , where VOL = 0.6 V, IOL = 8 mAIOL
50
VLOAD VOL
IOH(mA)
VLOAD(V)
Data
Input
In-Phase
Output
Input
(see Note A)
VCC
VCC
VCC50% VCC
50% VCC 50% VCC
50% VCC
VCC
VCC
50% VCC 50% VCC
50% VCC
50% VCC
VCC50% VCC 50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, ZO
= 50 , tr
= 6 ns.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For tPLZ and tPHZ, VOL and VOH are measured values.
50% VCC
Figure 1. Load Circuit and Voltage Waveforms
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PCI BUS PARAMETER MEASUREMENT INFORMATION
thigh
2 V
0.8 V
tr tf
tcyc
tlow
2 V MIN Peak-to-Peak
Figure 2. PCLK Timing Waveform
trst
tsrst-clk
PCLK
RSTIN
Figure 3. RSTIN Timing Waveforms
1.5 V
tval tinv
Valid1.5 V
ton toff
Valid
tsu
th
PCLK
PCI Output
PCI Input
Figure 4. Shared Signals Timing Waveforms
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PC Card cycle timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory andI/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card addresssetup and hold times and the PC Card command active (low) interval. This allows the cycle generator to outputPC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding
the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.The PC Card address setup and hold times are a function of the wait-state bits. Table 1 shows address setup
time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 2 and Table 3 show command activetime in PCLK cycles and nanoseconds for I/O and memory cycles. Table 4 shows address hold time in PCLKcycles and nanoseconds for I/O and memory cycles.
Table 1. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITSTS1 0 = 01
(PCLK/ns)
I/O 3/90
Memory WS1 0 2/60
Memory WS1 1 4/120
Table 2. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles
WAIT-STATE BITS TS1 0 = 01
WS ZWS (PCLK/ns)
0 0 19/570
I/O 1 X 23/690
0 1 7/210
00 0 19/570
01 X 23/690
Memory 10 X 23/690
11 X 23/69000 1 7/210
Table 3. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles
WAIT-STATE BITS TS1 0 = 01
WS ZWS (PCLK/ns)
0 0 7/210
I/O 1 X 11/330
0 1 N/A
00 0 9/270
01 X 13/390
Memory 10 X 17/510
11 X 23/630
00 1 5/150
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Table 4. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITSTS1 0 = 01
(PCLK/ns)
I/O 2/60
Memory WS1 0 2/60
Memory WS1 1 3/90
timing requirements over recommended ranges of supply voltage and operating free-airtemperature, memory cycles (for 100-ns common memory) (see Note 5 and Figure 5)
ALTERNATE
SYMBOLMIN MAX UNIT
tsu Setup time, CE1 and CE2 before WE/OE low T1 60 ns
tsu Setup time, CA25CA0 before WE/OE low T2 tsu(A)+2PCLK ns
tsu Setup time, REG before WE/OE low T3 90 ns
tpd Propagation delay time, WE/OE low to WAIT low T4 ns
tw Pulse duration, WE/OE low T5 200 ns
th Hold time, WE/OE low after WAIT high T6 nsth Hold time, CE1 and CE2 after WE/OE high T7 120 ns
tsu Setup time (read), CDATA15CDATA0 valid before OE high T8 ns
th Hold time (read), CDATA15CDATA0 valid after OE high T9 0 ns
th Hold time, CA25CA0 and REG after WE/OE high T10 th(A)+1PCLK ns
tsu Setup time (write), CDATA15CDATA0 valid before WE low T11 60 ns
th Hold time (write), CDATA15CDATA0 valid after WE low T12 240 ns
NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
timing requirements over recommended ranges of supply voltage and operating free-airtemperature, I/O cycles (see Figure 6)
ALTERNATE
SYMBOLMIN MAX UNIT
tsu Setup time, REG before IORD/IOWR low T13 60 ns
tsu Setup time, CE1 and CE2 before IORD/IOWR low T14 60 ns
tsu Setup time, CA25CA0 valid before IORD/IOWR low T15 tsu(A)+2PCLK ns
tpd Propagation delay time, IOIS16 low after CA25CA0 valid T16 35 ns
tpd Propagation delay time, IORD low to WAIT low T17 35 ns
tw Pulse duration, IORD/IOWR low T18 TcA ns
th Hold time, IORD low after WAIT high T19 ns
th Hold time, REG low after IORD high T20 0 ns
th Hold time, CE1 and CE2 after IORD/IOWR high T21 120 ns
th Hold time, CA25CA0 after IORD/IOWR high T22 th(A)+1PCLK ns
tsu Setup time (read), CDATA15CDATA0 valid before IORD high T23 10 ns
th Hold time (read), CDATA15CDATA0 valid after IORD high T24 0 ns
tsu Setup time (write), CDATA15CDATA0 valid before IOWR low T25 90 ns
th Hold time (write), CDATA15CDATA0 valid after IOWR high T26 90 ns
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switching characteristics over recommended ranges of supply voltage and operating free-airtemperature, miscellaneous (see Figure 7)
PARAMETERALTERNATE
SYMBOLMIN MAX UNIT
BVD2 low to SPKROUT low 30
pBVD2 high to SPKROUT high 30
pd ropaga on e ay meIREQ to IRQ15IRQ3 30
ns
STSCHG to IRQ15IRQ3 30
PC Card PARAMETER MEASUREMENT INFORMATION
T8
T6
CA25CA0
REG
CE1, CE2
WE, OE
WAIT
CDATA15CDATA0
(write)
T1 T7
CDATA15CDATA0(read)
T2T3
T11
T10
T12
T4
With no wait state
With wait state
T5
T9
Figure 5. PC Card Memory Cycle
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PC Card PARAMETER MEASUREMENT INFORMATION
T16
T23
T19
CA25CA0
REG
CE1, CE2
IORD, IOWR
WAIT
CDATA15CDATA0
(write)
T14 T21
CDATA15CDATA0
(read)
T15T13
T25
T22
T26
T17
With no wait state
With wait state
T18
T24
T20
IOIS16
Figure 6. PC Card I/O Cycle
BVD2
T27
SPKROUT
IREQ
T28
IRQ15IRQ3
Figure 7. Miscellaneous PC Card Delay Times
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MECHANICAL DATA
GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY
4040185/ A 04/95
0,600,90
1
A
Dia Solder Balls
256 Places24,00 SQ
27,00 SQ
16,10 SQ
0,36
1,17
0,60 Seating Plane
2,13
1,435 TYP
45 4 Places
1,27
0,15
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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IMPORTANT NOTICE
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Copyright 1997, Texas Instruments Incorporated