Thomson Chassis-icc19!50!100 Training-manual [Et]
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Transcript of Thomson Chassis-icc19!50!100 Training-manual [Et]
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Code : 3504.93.50 - 07/97 - ICC19 CHASSIS TELEVISION SETS: PRINCIPLES AND MAINTENANCE. No copying, translation, modification on other use authorized. All rights reserved worldwide. Tous droits de reproduction, de traduction, d'adaptation et d'excution rservs pour tous les pays. Smtliche Urheberrechte an diesen Texten und Zeichnungen stehen uns zu. Nachdrucke,Vervielfltigungen - auch auszugsweise - nur mit unserer vorherigen Zustimmung zulssig. Alle Rechte vorbehalten. I diritti di riproduzione, di traduzione, e esecuzione sono riservati per tutti i paesi. Derechos de reproduccion, de traduccion, de adaptacion y de ejecucion reservados para todos los paises.
ICC19 CHASSIS TELEVISION SETS:PRINCIPLES AND MAINTENANCE
50-Hz CHASSIS
100-HzCHASSIS
-
CONTENTS
GENERAL INFORMATION-----------------------------------------------------------------------------------------3
MANAGEMENT------------------------------------------------------------------------------------------------------- 5
POWER SUPPLY ---------------------------------------------------------------------------------------------------23
TIME BASES------- ------------------------------------------------------------------------------------------------- 57
HIGH FREQUENCIES/MEDIUM FREQUENCY------------------------------------------------------------ 73
SWITCHING --------------------------------------------------------------------------------------------------------- 79
50-HZ VIDEO-------------------------------------------------------------------------------------------------------- 89
100-HZ VIDEO----------------------------------------------------------------------------------------------------- 103
VIDEOTEXT AND OSD ----------------------------------------------------------------------------------------- 125
RGB AMPLIFIERS------------------------------------------------------------------------------------------------ 129
AUDIO PROCESSING ------------------------------------------------------------------------------------------ 133
DOLBY PROLOGIC --------------------------------------------------------------------------------------------- 139
1
-
MANAGEMENT
CONTENTS
IR001 POWER SUPPLY AND OPERATIONAL SIGNALS
DATA MANAGEMENT
CONTROLS
RMICROCONTROLLER/EPROM COMMUNICATION
BUSES
BUS EXPANDER
OTHER CONTROLS
SWITCH-ON PROCEDURE
FRONT PANEL LED CONTROL
OFF/ON TIMING DIAGRAM
ERROR CODES
CENTRE DEFORMATION TECHNIQUE
5
5
-
66
IP130DP130 DP133
CP130 CP141
DP134
IP140
REGULATOR5V
CP142
+5V
IR001ST90R92
TDA8139
CR009 CR010
QR00127MHZ
46 48
9
6
3
49
23
RP147
40ms
1
MC7812
LP020
17
18
13V (L)
VCC
RESET
3v
12
3
RESET
CENTRE DEFORMATION TECHNIQUE
-
IR001 POWER SUPPLY AND OPERATIONAL SIGNALS
POWER SUPPLY
The power supply to the microcontroller at Pin 23 is active when the IP130regulator (which produces a 10VSTBY) and the IP140 regulator (whichproduces a 5VSTBY from the 10VSTBY) are on Standby. When they are On,the 13 V (LINE) supply takes over from the 10VSTBY.
CLOCK.
A 27-MHz QR001 quartz stabilises the system clock of the IR001microcontroller (Pins 46 and 48).
RESET.
CP142, Pin 3 of the IP140 is the Reset capacitor. When the voltage at Pin 9 ofthe IP140 has reached 5 V, and after a delay of a few milliseconds given byCP142, Pin 6 of the IP140 goes from 0 to 5 V. Pin 49 of IR001 receives thisReset signal.
NOTES :
CENTRE DEFORMATION TECHNIQUE
7
7
-
88
RESET
+5VSTBY
RIR
STB-LED
CLAVIER
LDR
AFC
AV1
AV2
MUTE
MUTE C
SAT_ON_DEG
FB_DET
TV OFF
ZOOME-FIELD
I2C-1
I2C-2
SND-RESET
INT
BUS M3L
IR001ST90R92
EEPROM
IR003
IR004
BE_STROB
EPROM
IR002
256 Ko
4 Ko
Expander
RAM
REGISTRES
TIMER
SAFETY
Bus p
QR001
M-RESETPOWER-FAILAlim.
VIDEOTEXT
DEFLECTIONVIDEO MATRIXPIP MODULE
DOLBY SOUND
TUNER CCT5000CHROMA 1H / 2HPSI 2H
MEGATEXT
VIDEO MODULE100HZ
MODULE
27MHZ
MARK-E-TING
Data
Addresses
DS
46 4823
51
53
43
42
44
45
62
52
54
27
40
4149
55
28
636465
25
39
29
33
3231
34
VIDEO ADJUSTMENT
CEN
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FORM
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TEC
HN
IQU
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DATA MANAGEMENT
ICC19 chassis are 50-Hz or 100-Hz compatible. They are controlled by an 8-bit microcontroller, the ST90R92.
It communicates via an address and data bus with its external programmemory, an EPROM, IR002, with a basic capacity of 256 KB that can beextended to 1024 KB.
Two I2C buses dialog with the various programmable circuits installed on thechassis.
In conjunction with IR003 (EEPROM), the I2C1 bus saves the parameters andsettings required by the television set.
It manages the ON/OFF command, the line and frame time base circuits, audioand video switching, and settings including the USYST voltage.
In conjunction with the tuner frequency synthesis, the I2C2 bus controls videoprocessing and the 100-Hz digital converter.
It also controls an 8-bit IR004 universal register (EXPANDER), which increasesthe number of control ports.
The M3L bus is intended for the TELETEXT module (MEGATEXT version).
The microcontroller analyses and distributes the commands from peripheraldevices, the infrared receiver, the keypad, and the red LED via several inputand output lines.
The INT line is the HALT input of the microcontroller, and the MAIN RESEToutput of the TELETEX module.
NOTES :
CENTRE DEFORMATION TECHNIQUE
9
9
-
10
10
A
B
C
D
58
59
60
53
VOL+
VOL-
PROG+
PROG-INSTALL EXIT
MENU
MUTE
INFO
RR039
RR040
RR038
RR037
RR045
RR032
RR033
RR034
RR035
RR044
5VSTBY
5VSTBY
RIR
IR001
KEY OUT
KEY IN
RR924OPTION
35
36
37
38
CENTRE DEFORMATION TECHNIQUE
-
CONTROLS
KEYPAD
The keypad is compatible with previous ICC10/11 chassis. It can support fourto 10 control keys. It is laid out in a matrix of rows and columns.Pins 58 through 60 are the function inputs. They are at 5 V when idle. Pins 35through 38, which are labelled A, B, C, and D, are the sweep outputs. Signalswith a period of 20 ms are present on these outputs when idle.During the initialisation phase, Line C (Pin 36) is connected to the input andanalysed. In this way, an option prediction, determined by Resistor RR924, canbe read.The four diodes protect the IR001 circuit inputs.
REMOTE CONTROL UNIT
LRemote control function codes (12 bits) arrive at Pin 53 of IR001. They consistof the following: Four address bits, One call bit, Seven function bits, defined by the key pressed.
These codes are repetitive at 80-ms intervals.
NOTES :
CENTRE DEFORMATION TECHNIQUE
11
11
-
12
12
BS05
BS04
BS01
BS00
15 bits
8 bits
A0 - A14
D0 D715 22
25 24Data strobe line DS
16
17 21
5VSTBY
1 - 32
14
13
3
2
30
3157
56
1 12et
66 68
4 1223
25 29
13 15
IR002EPROM
IR001 C
CENTRE DEFORMATION TECHNIQUE
-
REMOTE CONTROL UNIT
ADDRESSING
The IR002, memory for the software and default values, is an EPROM withcapacity up to 512 KB or 4 Mbits.The 8-bit ST90R92 microcontroller has an address bus (A0-A14) limited to 15bits. This provides addressing of only 32 KB. Page-swapping is thereforenecessary.
Four output port lines (BS00 through BS05) swap the read-only memory for aselection of 16 pages compatible with the use of an 8-Mbit memory capacity,i.e. 1024 KB.
DATA
Data comprising eight bits, labelled D0 through D7, are sent via the data bus.To prevent any conflict of addresses with the microcontroller internal RAM, anenable line, called data-strobe, is activated in the low state when themicrocontroller communicates with its ROM. The rest of the time, the IR002 isin tri-state to free the data bus.
NOTES :
CENTRE DEFORMATION TECHNIQUE
13
13
-
14
14
IR004
REGISTERMC14094
IR003EEPROMM24C32
DR104
9,1VRR010
RR011
+5VSTBY 13V L
M3L-CK
M3L-DA
M3L-ENAB
63
64
65
3231
3433
29BE-STROBE
2
SDA
SCL
SDA
SCL
RR055RR056
+5V
+5VSTBY
RR052RR053
IR001
1
11
8
14
6
3
12
13
16
15
5V
BG_INFO
L1_INFO
I_INFO
IIC2
IIC1
DEGAUSS
NORM
TUNERVIDEO MODULE
PERITELAUDIO
IV001
8 7
5 6
VIDEOTEXT
TR095
c
PIP
MEGATEXT
RR012
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BUSES
The IIC1 bus is charged by pull-up resistors connected to the +5VSTBY. It isactive in Standby and On Modes.It dialogs with the IR003 NVM (M24C32) to store the user parameters.It distributes its commands to the SCART switching circuits, the Audio Module,and the sweep and video processor (IV001).
The IIC2 bus, referenced by pull-up resistors connected to the +5V, is active inOn Mode only.It communicates directly with the PLL built into the tuner. It controls the VideoModule as well as the IR004 expander circuit.
The M3L bus is used in controlling the Teletext or Megatext Module.
BUS EXPANDER
Integrated Circuit IR004 (MC14094) is an 8-bit serial/parallel register thatextends the interface capacity of the microcontroller.It is equipped with a de-serialiser register and an output register. Its BE-STROBE (Pin 1) has the function of transferring a service byte to its outputs.
Pin 6: NORM is used via Transistor TR095 by Integrated Circuit FI II050. Pin 11: DEGAUSS. According to chassis option, this output delivers a relay
command pulse to degauss the tube. Pin 12: I-INFO adjusts the video level to the I standard. Pin 13: L1-INFO is used for switching to Band 1 L'. Pin 14: BG-INFO is used to operate filters to reject the neighbouring channel
(31.9 MHz) and to reject FM sound intercarriers (5.5 MHz or 6.5 MHz).
NOTES :
CENTRE DEFORMATION TECHNIQUE
15
15
-
16
16
40
54
28
52
43
44
45
62
41
27
42
IR01
TV_OFF
RR910TR102
RR103
MUTE CENTER
MARK_E_TING
MUTE
LDR RR042
RR043
13V (L)sensor
AV2 (8)AV1 (8)(A/D)
(A/D)
(A/D) FB_DET
SAT_0N
AFC
DR091
(A/D)
ZOOM /E-FIELD(PWM)
(A/D)
C
SAFE
C MUTE
DR090
CENTRE DEFORMATION TECHNIQUE
-
OTHER CONTROLS
The function of Pin 27 is to switch the power supply separately from the satellitetuner.
Pin 40 is used to switch off the television set using a control independent of thebuses. This is very useful in the event of the buses being blocked.The breathing line is pulled down via Transistor TR102. In addition, this line isanalysed by software to indicate whether the TV is a 100-Hz or 50-Hz model.This is indicated by RR910 (RR910 = 10K, 4 V at 40 = 100 Hz; RR910 = 0,0.6 V at 40 = 50 Hz).Pin 41 has two functions: To control the ZOOM Module if the television set is so equipped. On the 28" SF and 32" 16/9 modules, it delivers a PWM (pulse width
modulation) signal to compensate for the earth's magnetic field.Pin 42 informs and analogue-to-digital converter for the AFC (automaticfrequency control). It operates in Automatic Programming and Manual SearchModes.
Pin 43 informs an analogue-to-digital converter. This is used to regulate thecontrast according to the ambient lighting.
Pins 44 and 45 receive slow switching from SCART sockets AV1 and AV2.They are used to recognise the formats of received images: 4/3 and 16/9.
Pin 52 mutes the audio amplifiers. It is active at low level, and is present eachtime the TV is switched on or off.
Pin 54 is reserved for the DOLBY SURROUND PROLOGIC function only, toperform a software cut-off of the TV internal speakers, to free the centralchannel. It does not act on the auxiliary external output sockets.
Pin 62 indicates the presence of fast switching from SCART socket AV1.
At Pin 28, the input when the microcontroller is initialised by its pull-up wiringspecifies the size of the read-only memory, IR002, by selecting the number ofpages to swap. It is completed by the wiring of Pins 63 and 61 to the 5VSBY.
NOTES
CENTRE DEFORMATION TECHNIQUE
17
17
-
18
18
R V
VCC1
RV001TV002
RV002
20 24 4422
MV19
18
65
31
32
IR00324C32IR001
REGISTER
INTERFACE BUS
65 M3-ENAB
DATA
CLK
43
I-CUT
38 17 37 25
CV246
DR1049,1V
RR010
HORIZONTALDEFLECTION
TR002RR031RR036
RR29
51
REGULATIONCTL
VERTICALCTL
CdeLIGNE
+5vSTBY
10VSTBY
+UVERT
8V
IV001STV2161/STV2162
ST90R92
13v
4534
RV091
RR030
5V
REG.
RP148 RP149
RP142 RP143TP146
+5V
5,8Vde DP140
24
87
IP140
DP134
CEN
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FORM
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TEC
HN
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SWITCH-ON PROCEDURE
The 10VSTBY from the power supply is used. This is limited to 5 V by a Zenerdiode inside the IV001, and powers its IIC1 bus interface.
After its power supply, clock, and reset, the IR001 microcontroller manages thefollowing commands: RAM reading, I/O configuration of ports, Reading EEPROM, IR003. To be programmed, if necessary, using the default
values contained in the IR002 program memory, if it is deprogrammed orblank.
When an ON command is issued, the IR001 microcontroller initialises IV001via its IIC1 bus with values stored in the EEPROM (loading of essentialparameters: on, geometry, etc.). Pin 24 on the IV001 is freed, and leads to thepresence of VCC1 = 8 V via TV002. This voltage powers Pins 22 and 44 of theIV001.
The line time base, secondary regulation, and frame time base are graduallypowered up by the slow-starting capacitor, CV246 (Pin 17 of IV001).
The rising of the line 13 V transmitted by DR104 confirms that the On functionis fully established (5V at Pine 65 of IR001). This 13VL also makes it possibleto obtain a +5V via the IP140 regulator.
The ICUT signal (Pin 43 of IV001) indicates when the tube is warmed up, andfrees the analogue controls. The image and sound appear. Orders routed infrom the outside, e.g. from the keypad or the remote control unit, are thenprocessed.
FRONT PANEL LED CONTROL
In Standby Mode, Pin 51 of microcontroller IR001 is in high impedance.Switching transistor TR002 powers the red LED from the 5 V STBY.In On Mode, the 13 V from the line time base powers the green LED. This is theinitialisation phase, and results in the indicator lamp glowing orange.When the warm tube signal, sent by the I2C1 bus to IR001, is detected, Pin 51of IR001 goes to 0. This blocks TR002 and cuts off the power supply to the redLED.
CENTRE DEFORMATION TECHNIQUE
19
19
-
20
20
Init.IV001
40ms
10v STBY5v STBY
400ms
Reset
IIC1
TV-OFF
H-DRIVE
+13v+5V
IIC2M3L
Interrupt
Powerfail
M-Reset
Mute C
Mute
I CUT
OFF to ON CHRONOGRAM
0V
+1,2V
100ms
RED ORANGE GREENOFF
1s
HDRIVE
ON
4s
100ms 0,5ms
PBNVM
CEN
TRE
DE
FORM
ATI
ON
TEC
HN
IQU
E
-
ERROR CODES
These error codes are displayed by the red LED. They are displayed only if themanagement microcontroller is operating.A maximum of 81 codes (11 through 99) can be signalled. These codes consistof two digits separated by a 0.7-second pause. The error codes are repeatedagain and again, with a pause of 1.7 s between error codes.
SIGNAL RATE AT 2 OF BR001
There are four possible waveforms, according to whether the TV remains inStandby Mode or is switched On, and whether LED pause status is Off, Red,Orange, or Green.
LIST OF ERROR CODES
CENTRE DEFORMATION TECHNIQUE
21
21
pauseorange
pausevert
vert
orange
pauserouge
teint
0,7 sec. 1,7 sec.
2 4
3 4
0,7 sec.
0,7 sec.
1,7 sec.
1,7 sec.
250ms250ms
0,7 sec. 1,7 sec.pauseteint
rouge
CODE ERROR CODE ERROR
ACR MSP3410 26 NO WARM TUBE SIGNALAFTER 15 s11
ACR MSP3400 27 STV216X DETECTED A CASEOF PROTECTION 3 TIMES12
ACR DSP56004 28 MEGATEXT INTERFACENOT RESPONDING13
ACR STV2161/2162 29 MEGATEXT DRAM ISDEFECTIVE14
ACR STV2151ouTDA9143 31
NO RAM AVAILABLE FOR THEREQUESTED FUNCTION15
ACR DMU0 32 TIMER OCCUPIED16
AUDIO MODULE NOTDETECTED 33 ACR STV216517
ACR TEA6415C 34 ACR NVM M24C3218
ACR TUNER 35 13V ABSENT19
IIC1 DATA EARTHED 36 NVM ADDRESS NOTFOUND21
IIC2 DATA EARTHED 37 INCORRECT NMI LEVEL(HALT)22
IIC1 CLOCK EARTHED 38 M3L BUS IS BLOCKED23
IIC2 CLOCK EARTHED 39 MEGATEXT NOT LISTE-NING24
SWITCHED 5 V ABSENT25
-
POWER SUPPLY
CONTENTS
INTRODUCTION
PRINCIPLE
CHARACTERISTICS
LP020 POWER SUPPLY
INTEGRATED CIRCUIT TEA2261
SECONDARY REGULATION
POWER SUPPLY INTERLOCKS
MAINS POWER CUT DETECTION
CENTRE DEFORMATION TECHNIQUE
23
23
-
24
24
+300V
TP060
220V
LP 070
LP020
14
Safety
2
9
IP060TEA 2261
16
DP110
10
11
3
DP109
CP060
Usys
CP061
RP061
76
1
8
15
LogicProcessor
DP130
-US
Osc
PWMSoft start
DP108
Power/Deflectionsafeties
RL81/82
RP054 CP054 +US
+10VSTBY
GNDS
CP063
RP025
IP130 DP133
+13V
+UVERT
RL80
+US-US+5V
IV001(STV2161)(STV2162)
SMPS
SMPS
CP020Regulation/Deflectionsafeties
10VReg.
PFCPFC
(50Hz)
Contr.(100Hz)TP025
RP060
RP059
TP027
(Option)
RP065 RP020CP062
CP064
DP053 DP050
DP052
12DP134
TP161
DP140
IP1405V
STBY
+5V
TDA8139
MIS
BREATHING
+U13DP60
CENTRE DEFORMATION TECHNIQUE
-
INTRODUCTION
The ICC19 power supply comes in two main versions: one operating at 16kHz, and the other operating at 32 kHz. The main difference lies in the choiceof components.
PRINCIPLE
IThe power supply is a fixed-frequency flyback-type switching power supplyunit. Two specific regulating loops come into action according to the statusof the TVC.
In Standby Mode, the frequency is determined by an oscillator located on theprimary. This is also where regulation occurs. To do this, a signal indicating theoverall consumption of the secondaries, picked up on a primary winding, isused.In Steady-State Mode, the line frequency synchronises the signal.Regulation then takes place at the secondary, and is based on stabilising thevoltage USYS applied to the line time base.
CHARACTERISTICS
TMains voltage: 190 to 264 volts.Secondary voltages:
U SYS 127 to 136 V for 50-Hz chassis.130 to 142 V for 100-Hz chassis.
+ US approx. +18 V for stereo chassisapprox. +14 V for Dolby chassis.
- US approx. -18 V for stereo chassisapprox. -14 V for Dolby chassis.
UVERT 26 V on 50-Hz chassis23 V on 100-Hz chassis.
U 7V 6 to 7 V5 according to chassis.
NOTES :
CENTRE DEFORMATION TECHNIQUE
25
25
-
26
26
CENTRE DEFORMATION TECHNIQUE
Im
- +Um
Uc
R
RLC
220VAC
Um
Uc
Im
Narrow current pulse includinga high harmonic level
Im
- +Um
R
C1
220VAC
Um
Ub
Im
C2L1 D1
n
2n
T1
Ua
Um
ID1
D1 conductionlevel whenT1 is ON
With PFC
Without PFC
a
b
c
WITHOUT PFC CIRCUIT WITH PFC CIRCUIT
-
LP020 POWER SUPPLY
The new European standard, EN60555-2, limits pollution of the mainsvoltage by harmonics. For this purpose, the main primary winding isconnected to the bridge rectifier via a power factor correction circuit.
PRINCIPLE
Harmonics are generated by the filter capacitor charging current.The narrower the charge pulse, the higher the amplitude of the harmonics(this occurs with a weak voltage residual and therefore a high capacitorvalue).The layout used for this chassis therefore operates on the principle ofwidening these charging current pulses to reduce the amplitude ofharmonics. To do this, a condenser C1 is inserted between the diode bridgeand filter condenser C2 (C1 < < C2). It decouples the dc voltage betweenCondenser C2, charged to 300 V, and the diode bridge, providing full-waverectification of the mains voltage.An intermediate tap on the primary winding divides the winding so that whenTransistor T1 conducts, the voltage at Point C is about 2/3 the value of thevoltage at Point B. This, as soon as the rectified mains voltage exceeds thisvalue (Point A), Diode D1 conducts, and the current is tapped directly off thediode bridge.Because of this, a lower load is applied to Capacitor C2 (resulting in a lowercharging current), and the mains voltage takes effect over a longer period.The current pulse taken from the mains therefore generates a lower level ofharmonics.
NOTES :
CENTRE DEFORMATION TECHNIQUE
27
27
-
28
28
DP018
DP10
DP12 DP13
DP11
DP16
DP019
CP114n7
CP124n7
CP15470n
CP13
CP0181
CP017470p CP020
CP019470p
LP019LP15
RP102R7
MIS
CHASSIS
TP060
3/4
1/2
5/6
n
2n
CENTRE DEFORMATION TECHNIQUE
-
APPLICATION
A filter, CP15, CP018, and LP15, eliminates the mains pollution generated bythe line frequency switching of Diode DP019 (D1).Diode DP16 protects CP15 (C1) against voltage spikes on the mains.Diode DP018 limits the collector overvoltage of TP060 (T1) when diodeDP019 is blocked.
NOTES :
CENTRE DEFORMATION TECHNIQUE
29
29
-
30
30
+
-
+
-
+
-
GENERATOR"BURST"
SOFTSTART
STBYOSC.
IS
SOFT
+-
STBYSTARTING
TA SOFTWARECONTROL
TB
REGULATIONORDER
4,5 A
10 A
+ -
0,15 V
+- + -
POSITIVESW
NEGATIVESW
TC
0,9 V0,6 V
2,6 V
OVER VOLTAGEPROTECTION
LIMITATIONI
INNERPOLARISATION
INNERREF.2,5 V
SAFETY
Vcc+-
15,7 V
OVERVOLTAGE
9 11 10 1 2 8 3 4 13 5 12
GND
6
AMPLIFIERERROR
1
2
3
7 16
Vcc
15
V +
14
2,5v
CENTRE DEFORMATION TECHNIQUE
-
INTEGRATED CIRCUIT TEA2261
TEA2261 incorporates the various stages required for control and regulationof a switching power supply unit. It includes the following:
Internal voltage reference and regulation circuitError oscillatorError amplifierPulse width modulator (PWM)Gradual start circuitTransformer degaussing controlCurrent limiting threshold detectionLogic management of limits and interlocksOutput stage for direct drive of a bipolar power transistor.
Because of the automatic switching of SALVES Mode in the event of lowconsumption, this circuit handles a wide range of regulation tasks, from a fewwatts to values in the region of 200 W.
NOTES :
CENTRE DEFORMATION TECHNIQUE
31
31
-
32
32
12VIP050
RECTIFIERPFC
FILTER
220VAC300VDC
LP0203/4
8
10
9
RP05010RDP052
DP053DP051
CP054470
CP054470
RP030
RP032360k
RP02533k
CP020
RP029100k
RP05515R
CP0554n7
CP05647
DP050
TP060
CP05210
14
7809
16
+
-
+ Vcc
REF.2,5 V
15,7 VI
SIGNALRESET
Vcc < 5V5
REGUL.Vcc INT.
5 V
R1
R2
PROTECTIONOVER VOLTAGE
VccVcc MAX.
RESETSafety
V REF. 2,5 V
Vcc OFF
Vcc INT. 5 V
10v3 7v4
15Outputpowersupply
IP060TEA2261
RP054
CENTRE DEFORMATION TECHNIQUE
-
GENERATION OF INTERNAL REFERENCES AND POWER SUPPLIES
The power supply at Pin 16 comes from:
On start-up, half-wave rectification of the mains by the mesh RP025, CP054,and a diode of the bridge rectifier.
In Standby Mode, winding 9, 8 of LP020 (fly-back mode). 12 V obtained byrectification (DP050, CP054) is applied to regulator IP050 (7809 applied toDiode DP051), which supplies 9 V via DP052.In Steady-State, winding 9, 10 of LP020 (fly-back mode). Rectification byDP053 supplies a voltage of about 11 V.
Note that in this case Diode DP052 is blocked, and disconnects circuit IP02.
Resistor RP054 delivers the power supply to the final stage (Pin 15), and setsits maximum current.
The circuit supplies several voltages and service signals according tochanges in the direct current voltage at Pin 16.
As soon as +Vdc reaches approximately 4V5, an internal reference of +2V5is generated.
For +Vdc 5V5, a RESET pulse is produced.
When +Vdc reaches 10V3 (Vdc start), enabling of an internal power supplyVdc int = 5 V. This stabilised voltage allows the circuit to perform well in awide voltage range on Pin 16.This threshold also triggers the passage to high state of Vdc off, thusenabling the interlock and limit management logic, and authorising pulseoutput from Pin 14 (as long as +Vdc remains higher than +Vdc stop, i.e. 7V4typ.).For Vdc of 15V7 typ., passage to high state of Vdc max, and interlocking ofthe circuit by the interlock and limit management logic.
NOTES :
CENTRE DEFORMATION TECHNIQUE
33
33
-
34
34
CENTRE DEFORMATION TECHNIQUE
12VIP050
RECTIFIERPFC
FILTER
220VAC300VDC
LP0203/4
8
10
9
RP05010R
RP02710k
RP026100k
DP052
DP053DP051
CP054470
CP054470
RP030
RP032360kRP028100k
RP02533k
TP026TP025
DP027
CP020
RP029100k
RP05515R
CP0554n7
CP05647
DP050
TP060
CP05210
7809
16
14
IP060TEA2261
DP034
DP0285V1
12VIP050
RECTIFIERPFC
FILTER
220VAC300VDC
DP052
DP053DP051
CP054470
RP030
RP032360k
RP02533k
DP054
CP020
RP029100k
RP05515R
RP035DP035
CP0554n7
CP05647
TP060
CP05210
14
16
7809
IP060TEA2261
POWER STANBY SWITCHING LOW POWER SWITCHING
-
OPTIONS
SWITCHING OF START-UP POWER SUPPLY
On 100-Hz chassis, a thyristor (TP025) is added in series with ResistorRP025.
When mains power is applied, a current from the 300 V via the RP028,RP030 through 32 resistor network energises the thyristor. The thyristor thenchannels the CP054 charging current.When the power supply starts up, a voltage of 9V6 appears at the output ofRegulator IP050 and saturates Transistor TP026. With its gate then earthed,the thyristor de-energises the next time the mains alternation is inverted.
This layout reduces the consumption by 0.7 W.
LOW-POWER SWITCH
A low-power switch can be connected in series with Resistor RP025 toreplace the classic mains switch.
In operation, this switch connects RP025 via Resistor RP55 to Pin 16 of IP60.
In Off position, this switch switches Pin 16 of IP060 to earth via ResistorRP035 and Diode DP035.
Zener Diode DP054 limits the voltage to the terminals of CP54 when Off.
NOTES :
CENTRE DEFORMATION TECHNIQUE
35
35
-
36
36
V REF+VbeQ2
Q1
RP061270k
11
CP0601n
10
THRESHOLDCOMPARATOR
2 KQ3
R1
R2
R33V33 1V66
LP0208
10
DP050RP050
10R
CP051100F
RP05947k
Q1'
DP060
IP050
DP051
CP05210
7809
R4
CP0634n7
8
RP060270k
Safety
CP06210
RP0621M
TP027
Primaryregulation
Selfpower supply
IP060TEA2261
CENTRE DEFORMATION TECHNIQUE
-
OSCILLATOR
An oscillator determines the switching frequency of the switching device inStandby Mode.
It includes the following:
- Current (Q1, Q1', Q2) generator; value of current set by Resistor RP061 (Pin 11).
This current charges Capacitor CP060 (Pin 10).
Threshold detector which analyses the voltage across CP060: 1st threshold (2/3 Vdc int. = 3V33 typ.): switching of transistor Q3 and
discharge of CP060 by internal 2 kW resistor. 2nd threshold (1/3 Vdc int. = 1V66 typ.): blocking of transistor Q3 and
charging of CP060 by the current generator.
The overall result is a sawtooth.
Function of components RP059, RP060, and DP060.
In the start-up phase, because the secondary voltages are low, the timerequired to restore the energy is liable to exceed the nominal period of theoscillator. The oscillator therefore starts up with a low frequency (approx. 5kHz) due to components RP061 and CP060 only (Diode DP060 is blocked).With the increase in voltage at the IP050 output, Diode DP060 begins toconduct, and the current determined by RP060 gradually contributes to anacceleration of the charging of CP060, thus bringing the oscillator frequencyup to 19 or 20 kHz.
Resistor RP059 is connected to earth via the conduction of transistor TP027,and contributes to reducing the charging current of Capacitor CP060 andtherefore the frequency of the oscillator in the event of the primary interlockbeing triggered (refer to paragraph on interlocks).
NOTES :
CENTRE DEFORMATION TECHNIQUE
37
37
-
38
38 Threshold1v5
180A
9A
9
+
-
+
-
PULSESGENERATOR
1
2
CP061470n
U err
OSC PWM
U int
LP020
6-
+
ERRORAMPLIFIER
7
V REF.2,5V
9
RP0664k22
RP0641k
V REF. : 2,5 x 0,9 =
2,25 V SPECIALSOFT1 ; 0,9
14
TAIS
OutputSafeties
300V
T onmin(1s)OSC.
TP060
8DP050RP050
10R
CP051100F
IP050
DP051
7809
CP06422n
Standbyself power supply
DP061
15
Outputpower supply
Safeties3
Info.I TP060
RP065
CENTRE DEFORMATION TECHNIQUE
-
PRIMARY REGULATION LOOP
This includes an error amplifier that compares a fraction of the image of thesecondaries (Winding 8, 9, RP050, DP050, CP051, RP066, RP064) to aninternal reference.Resistor RP065 sensitises the primary circuit in Standby Mode.In Steady State, because the secondary regulations brings the voltage atPin 6 to approximately 4V7, the primary regulation is in a constantovervoltage configuration, and automatically shuts itself off.
A first PWM then compares the error voltage to the sawtooth signal from theoscillator, to produce a command strobe pulse (signal a).A second PWM defines the maximum authorised duty cycle (60%) bycomparing the same sawtooth signal to an internal voltage (signal b).A logical AND operator between these two signals produces the narroweststrobe pulse.
When switching on, and at the beginning of each burst, a soft start is ensuredby controlling the internal voltage and therefore the width of signal b: fromT1 to T2, Capacitor CP061 (Pin 9) is charged by an internal generatorproducing a current of 180 A. There is no signal at the IC output.At T2, the voltage at the terminals of CP061 reaches 1V5. The chargingcurrent goes to 9 A. Strobe pulses appear at Pin 14, corresponding tosignal b which is widening (Tb < Ta).A few milliseconds after T2, the soft start circuit stops limiting strobe pulsewidth, and the primary regulation loop becomes established (Ta < Tb).When the voltage reaches 2V7 typical, it sets the maximum duty cycle(b = 60%).The load on CP061 (maximum value 3V1) is returned to 800 mV at the endof start-up and at the end of each burst.
NOTES :
CENTRE DEFORMATION TECHNIQUE
39
39
-
40
40
IP060TEA2261
2
LP070
RP0681k
Primaryregulator Soft
Vcc int.
Secondaryregulator
-+
0V9 -
+
150mV
Vcc ext.
1500RRP050
10RRP069
22k
DP050
LP020
CP068470p
8
CENTRE DEFORMATION TECHNIQUE
-
LOGICAL IS STAGE.
During the transition between Standby and Steady State, the two regulationloops coexist. Because the signals are not synchronous, there is a risk of aTransistor TP060 command during the energy restoration phase, and of theinterlock being triggered by a current peak.
To avoid this problem, a signal taken from Winding 8, 9 and applied to Pin 1warns the circuit of this critical phase. All commands are then blocked.The first negative front (corresponding to the end of energy restoration =transformer degaussing) enables any new primary or secondary commands.
NOTES :
CENTRE DEFORMATION TECHNIQUE
41
41
-
42
42
-
+
-
+
-
+
Tc
_
Q
R
S2v6
CP0634n7
8
45 A
10A
Q1
_
Q1
S
R
B1
_
Q2
Q2B2
S
R
Vccoff
Tb
1st level
2nd level0V6
0V9
15V7
Vref2V5
(10V3, 7V4)
5V int
3
16 RP0200R1
TP060
Vcc Max
RESET
-
+
CP06210
RP0621M
RP05947k
RP060270k
RP0671k
RP063
7
RP065
- +
614
RESETVcc < 5V5+VccCP056
47
LP020
RP02533k
220V
RP05515R8 DP050 IP050
DP053
7809
TP027
10
DP052
CP054470
OSC
CP0601n
10
DP060
Primaryregulation
RP066
CENTRE DEFORMATION TECHNIQUE
-
AINTERLOCK ACTIVATION AND MANAGEMENT
The TEA2261 has a strobed current interlock at Pin 3 and an interlock relatedto the power supply voltage at Pin 16.
An image of the current is collected at the terminals of emitter resistor RP020,and applied to Pin 3 of TEA2261. The following two thresholds apply:1ST THRESHOLD INTERLOCKWhen the voltage at Pin 3 reaches the first threshold, 0.6 V, TP060 is blockeduntil the next Tb pulse (bit-by-bit limitation). During this time, CP063 ischarged by a current of 45 - 10 = 35 A.When this phenomenon is repetitive, the charge on CP063 reached 2V6 andtriggers an RS-bistable circuit which permanently disables control of TP060.A main reset is then necessary to re-start the circuit (Vdc 5V5).2ND THRESHOLD INTERLOCK In the event of a major overload (short circuit on USYS), a second thresholdis reached (0V9). Control of TP060 is permanently disabled. A main reset isthen necessary to re-start the circuit (V Pin 16 5V5).VOLTAGE INTERLOCKA voltage above 15V7 on Pin 16 blocks TP060. A main reset is thennecessary to re-start the circuit (V Pin 16 5V5).
SPECIFIC FEATURES OF ICC19 CHASSIS
Because the primary interlock is calibrated for U SYS at steady state, thesensitivity of this stage has been increased in Standby Mode to detect faultson the other secondaries.For this purpose, a resistor, RP065, is added between the error amplifieroutput of the primary loop (Pin 7 of IP060) and the interlock input (Pin 3).When capacitor CP063 reaches 0.6 V, Transistor TP027 conducts andreduces the charging current of Capacitor CP060 (RP059), which reducesthe frequency of the Standby oscillator.
NOTES :
CENTRE DEFORMATION TECHNIQUE
43
43
-
44
44
CENTRE DEFORMATION TECHNIQUE
TP060
CP0232n2
CP022470p
CP021150p
RP0500R10
DP0402V7
RP04147R
RP0424k7
CP0411n
CP040470
RP04022R
LP040 LP042
DP041BAT42
CP0421n
RP029100k
RP028RP030 32
460k
LP020
IP060TEA2261
14
15
12/13
DP022FUF4005
RP022100R
3/4
5/6 18
+USYS
DP110
DP112MUR
1100ECP110100
DP113
CP112
LP112
RP1121k2
RP54
-
TP060 ENVIRONMENT
OUTPUT STAGE
The output stage of the TEA2261 consists of a push-pull.It supplies the basic current for control of TP060, and then channels thereverse locking current caused by the discharging of CP040.In the conduction phase, Resistor RP054 limits the polarisation current.
TP060 SWITCHING CIRCUITS
Resistors RP029 through RP032 pre-charge CP040 as soon as power isswitched on, to ensure an adequate reverse locking current during the start-up phase and at the beginning of each burst. Self-induction coil LP040 setsthe dl/dt of the control current reversal.
The circuit DP022, CP023, RP022 slows the rise in collector voltage ofTP060 when it is blocked, to ensure minimum dissipation through switching,and to limit the overvoltage peak. To do this, it is assisted by the secondaryassembly DP113, LP112, RP112, CP112, and DP112.
NOTES :
CENTRE DEFORMATION TECHNIQUE
45
45
-
46
46
CENTRE DEFORMATION TECHNIQUE
LP020DP110
DP109
Usys
DP130
-US
DP108
+US
+10VSTBY
GNDS
IP130
DP133
+13V
+UVERT
7812DP134
DP140
IP140
5V
STBY
+5V
TDA8139
+U13
1
2
317
18
13
16
12
15
14
18
+U7V
Voltage
+USYS
+UVERT
+US
-US
+U7V
+USYS
+UVERT
+US
-US
+U7V
+USYS
+UVERT
+US
-US
+U7V
+USYS
+UVERT
+US
-US
+U7V
Black screensound mute
131,3V
26,1V
18,4V
-18,1V
7,7V
137,3V
26,0V
14,1V
-14,0V
7,52V
134,2V
22,7V
18,6V
-18,4V
5,95V
134,2V
23,5V
13,5V
-13,6V
6,05V
131,2V
26,5V
16,8V
-15,1V
7,87V
137,2V
26,3V
12,7V
-12,8V
7,68V
133,9V
22,8V
15,2V
-15,2V
5,8V
133,9V
23,4V
11,1V
-11,5V
5,78V
White screenmaxi. sound
50Hz stro
50Hz dolby
100Hz stro
100Hz dolby
85,3V
15,1V
10,5V
-10,3V
6,7V
91,6V
14,9V
7,7V
-7,6V
8,5V
108,2V
13,9V
11,1V
-11,0V
6,8V
104,4V
13,9V
8,9V
-9,0V
7,2V
Standby190V
86,7V
15,0V
10,6V
-10,3V
6,9V
91,3V
14,8V
7,7V
-7,6V
8,5V
109,6V
14,0V
11,3V
-11,1V
6,8V
105,9V
14,0V
9,0V
-9,1V
7,2V
Standby230V
-
SECONDARY VOLTAGES
The secondary windings produce five direct voltages:
+USYS which can be between 127 and 140 volts, according to chassis, andaccording to the winding connector selected (19 through 22 via jumpersJP914 through 917).+US and -US, symmetric power supplies with specific earth distributed to theaudio stage via a cable (from BP120).+UVERT, vertical stage power supply voltage. Also applied to the regulatorcircuit, IP30, and causes the polarisation of the base of TV002 (IV001 powersupply).+U7V, voltage supplying the switched 5 V.
In Standby Mode, the 10VSTBY is produced by Regulator IP130 and DiodeDP133. In Steady State, the 13 V from the EHT takes over via Diode DP134.
The switched 5 V is obtained at Pin 8 of IP140 (switched by voltage +U13,Pin 4) on 50-Hz stereo chassis, while a transistor, TP146, handles thisregulation task for 50-Hz Dolby and 100-Hz chassis (see illustrations below).
NOTES :
CENTRE DEFORMATION TECHNIQUE
47
47
-
48
48
VOLTAGES ELABORATION + 5 VSTBY AND + 5 V (50 Hz Stro VERSION)
LP020
CP143470F
DP130
DP134
DL041
DP133IP130
IP140TDA8139
DP140
CP1302200F
CP13110F
CP1412,2F
1
2
9
7
8
4
VI1
VI2
VO1
VO2
5V
Reg
Prog.
Dis
12V
RP14818 k
RP1494k7
CP14410F
RP1432k32
RP1422k21
CL045470F
CL0421000F
LL045LL008(THT)
10
12
RL0400R27 ZL041
CP1404700F
JP911JP910
12
13
17
18
+ 5 VSTBY
+ 5 V
10 VSTBY
+ 13V
+U13
+UVERT
CENTRE DEFORMATION TECHNIQUE
-
49
49
LP020
CP143470F
DL041IP140
TDA8139
DP140
2
7
8
4
VI2 VO2Reg
Prog.
Dis
RP14818 k
RP1494k7
RP1432k32
RP1422k21
CL045470F
CL0421000F
LL045LL008(THT)
10
12
RL0400R27 ZL041
CP1404700F
CP14610F
TP146
VOLTAGE ELABORATION + 5 V (50 Hz Dolby / 100 Hz VERSION)
+ 5 V
+ 13V+U13
CENTRE DEFORMATION TECHNIQUE
-
50
50
+10VSTBY
IP060TEA2261
2
14
U SYS300V3/4
5/6
LP020
TP060
19/20/21/22
18
DP110
CP110
RL081/82
RL080
TP161
LP070
RV2414k7RP1602k2
IV001STV2161/2162
37
31
VCC1
IR001ST90R92
VCC1
RP1622k2
RP0681k
RP13810k
RP13982k
RV2421kCV243
470p CV242470n
CV241100p
RP161330R
SMPS
CV246220n
18/19
//
31/32
17 CSOFT
SMPS INRgulation
ScuritBREATHING
2228
33 RV213
(CL030/038)
DP160RP1632k2
ScuritsAlimentation
Bases de temps
H REF
I2C1
13 DP140
TP162
fl
CENTRE DEFORMATION TECHNIQUE
-
SECONDARY REGULATION
This mode is adopted as soon as Steady-State Mode begins. It regulatesvoltage USYS.
A fraction of USYS, tapped off by divider bridge RL082, RL081, and RL080,is applied to Pin 31 of IV001 (SMPS IN).This information is compared to an internal reference whose value can beadjusted according to operating mode (USYS adjusted in 64 steps within a16-V range).A strobe signal at line frequency with a variable duty cycle is available onPin 37 (SMPS OUT).This signal is applied to galvanic isolating transformer LP070 via TransistorTP161.A soft start circuit is associated with the production of the command strobesignal. (CV246, Pin 17; when power is applied to circuit IV001, it is chargedto 5V5 in 900 ms.
The network RV242, CV242, CV243 limits the pass band of the entireregulating loop to 300 Hz.
On 100-Hz chassis, Transistor TP162 controls transformer degaussing.
In the event of irregularities on the secondaries or in the time bases,the interlock circuit forces the BREATHING line to low state (Pin 28 of IV001).The regulating and time base commands are then stopped. If the errorpersists after two more start-up attempts by IV001, the TV goes into StandbyMode.
NOTES :
CENTRE DEFORMATION TECHNIQUE
51
51
-
52
52
LP40DP40CP40
DP133IP13012V
VCC1
IP140
Deflectionsafeties
SAFE
TP060
LP060 DP110
DP109
DP140
DP130
USYS
TP129
TP190
TP175
TP170
TV002
TP161
VCC1+ 5V
+U13
+UVERT
+UVERT
+10VSTBY
+5VSTBY
+US
-USIP060
142
637
LP070RP068
RP066
RP064
RP067RP065
RP063
DP050
RP05010R
+10VSTBY
DP108
RP17210k
RP1914k7
RP192100k
RP1905k6
DP178
DP190
DP179RP177
RP1764k7
IV001
RP17122k
RP1934k7
RP17010k
RP1751K
CP17122
RP12910k
RP127100k
RP1282k2
RP1300R10
CP126100
RP1262k2
DP126
JL004100R
RP17922k
CP17947
DP175
3
2
1
IR001TR102 RR910
RR1031k
RV003
RV001
RP160
RP162
40
2812/22/442324
37
SMPSOUT
2 84
RP149 RP148
RP161
TV_OFF
CP1704n7
CENTRE DEFORMATION TECHNIQUE
-
POWER SUPPLY INTERLOCKS
Overloads and short circuits are detected by analysing the primary current inthe emitter resistor of TP060 (input at Pin 3 of circuit IP060).
The sensitivity of this stage was increased in Standby Mode to detect errors inthe low-voltage secondaries (RP065, TP027, and RP059). For this reason,when an incident occurs in Steady State on a secondary other than U SYS, itis necessary to go to Standby Mode to trigger the interlock.
- An overload or short circuit on voltages +U VERT or +10 V STBY leads topower supply VCC1 of the regulation and sweep circuit (IV001) disappearing.
- An overload or short circuit on +US causes TP190 and TP170 to conduct.This forces the breathing interlock input of the regulation and sweep circuit(IV001) to be triggered by a low level.
- An overload or short circuit on -US causes DP190 and TP170 to conduct,and triggers the IV001 interlock.
In the event that external speakers with too low an impedance value areconnected (Dolby versions), or when incidents occur on the +5 V, simply shutoff the sweep to remove the overload:- Excessive current in Resistor RP130 causes TP129 and TP170 to conduct,
and triggers the IV001 interlock (audio mute).- A short circuit on the +5 V blocks TP175 through the action of DP178, and
causes TP170 to conduct (see sweep interlocks), causing the IV001 interlockto trigger and the +13 V to disappear.
NOTES :
CENTRE DEFORMATION TECHNIQUE
53
53
-
54
54
DP151
DP134
DP133IP130
CP1302200F CP13110F
CP1412,2mF
1 95V12VCP14410F17
18
+UVERT
IP140TDA8139
+U13
10 VSTBY
+ 5 VSTBY
+ 5 VSTBY
DP152
RP1561k RP157
RP15868k
CP151220n
CP152220n RP159
330k
RP15010k
RP15112k RP152
2k2RP165120k
RP164100k
RP16710k
RP14510k
DP130
TP145
TP167
TR105TR106
TP166
TP150
TP152
TR091
RP1661k
RP1441k
RR1071k8
RR106470
RP1441k8
RR09822k
RR09910k
RR0841k
RR085100R
RR089100R
RR0914k7
POWER_FAIL
RR0934k7
CR08510n
DR090
DR091
55 54 52
IR001
CP15022n
CR092100p
INT
MUTEMUTE C
M RESET
MUTE
C MUTE
CENTRE DEFORMATION TECHNIQUE
-
DETECTION OF MAINS POWER FAILURE
In the event of mains power failure, the microcontroller must be informedpromptly so that the data in the NVM (IR003) can be saved, and to avoid aplop in the speakers (sound mute).To do this, POWER FAIL has a rising edge in the event of mains power failurein ON Mode, and a falling edge in the event of mains power failure in StandbyMode.The signal is received by the management circuit via the INTERRUPTIONinput at Pin 55. Transistor TR091 produces a low mute level when thephenomenon occurs in ON Mode.
The negative voltage rectified in Forward Mode by Diodes DP151/152 is animage of the mains voltage. It blocks TP152 in ON Mode. TP150 and TP145are blocked. TP167 is saturated, and the POWER FAIL line has a low level.When the mains falls below 160 Vac, TP152, TP150, and TP145 conduct,TP167 generates a rising edge on the POWER FAIL line by blocking off.
In Standby Mode, because voltage +UVERT goes from 23-26 V to 14 V, theRP150/151 network saturates TP150, TP145 conducts and blocks TP167,and the POWER FAIL line has a high level.When mains power breaks down, the decrease in 10VSTBY saturates TP166and TP167, and the POWER FAIL line has a falling edge.
NOTES :
CENTRE DEFORMATION TECHNIQUE
55
55
-
TIME BASES
CONTENTS
INTRODUCTION
PRODUCTION OF H-DRIVE COMMAND IN STV2161
SPECIFIC FEATURES OF STV2162
DRIVER STAGE
EHT AND LINE POWER
EW STAGE
FRAME SWEEP
TIME BASE INTERLOCKS
CENTRE DEFORMATION TECHNIQUE
57
57
-
58
58
RegulatorHVCO2MHz
Horiz. PLL Horiz.softPh.1 SeparatorSynchro
Ph.2 AlignementDriver
LL008
SAFETY
Breathing
+10VSTBY
RL0013k3
VCC1
RV222680k
+10VSTBY
Softstart
Frame
+ UVERT
SSC35
V BLK
HFLYBLK
BGMultiplexer
control36
SMPS
I2C
IX900TEA
6415C15 RX950
RX951
TX950ChromaModule
RV202150R
RV203150R
CV201680n
RV201180R 16
TV002TIP122
RV001110k
24 22 23 44/12
RV00324k9
21
CV2074n7
CV2061
CV246220n
CV21347p
CL211470p
CL03927n
CL03827n
CL0301n9
CV216470p
CV22222n
RV216330R
JL004100R
RV2134k7
RL2142k7
RV20618k
TP170
TL062
Powersupply
anddeflectionsafeties
ON/OFF
18 19 33 17
H FLY
38
28
TL030
V SYNC
IV01
+13V LI
DL134
STV2161
CENTRE DEFORMATION TECHNIQUE
-
INTRODUCTION
Time base commands are produced by the IV001 video processor:STV2161 for the 50-Hz chassis.STV2162 for the 1006Hz chassis.Apart from the difference in frequency, the difference between these twocircuits is in the internal oscillator, which is used constantly in the STV2161,but only for start-up in the STV2162 (an external 27-MHz signal then takesover).In Standby Mode, only the I2C interface of IV001 is powered. This allows themicrocontroller to manage start-up by freeing the transistor regulating controlTV002 (Pin 24), which then supplies the main power supply voltage to theVCC1 circuit.
PRODUCTION OF H-DRIVE COMMAND IN STV2161
A VCO (sawtooth signal generator) operates at 2 MHz. It calls on a referencecurrent supplied by Resistor RV003 (Pin 23). Its free frequency can beadjusted in 125-Hz steps in the 15,500-15,750 Hz range according tooperating mode.The video signal is applied to the synchronisation separation stage by Pin 16(SYNC-IN).The resulting signal is brought to the first phase detector which generates anerror voltage on filter RV206, CV206, CV207 (Pin 21).A HORIZONTAL-LOGIC stage then divides the frequency from theautomatically controlled VCO to apply it to the second phase detector.The second phase detector also receives the HFLY line return (Pin 33). Thisis where the horizontal phase adjustment takes effect; this also takes placevia Operating Mode.A signal shaping stage increases the H-DRIVE signal on the open-collectoroutput (Pin 38). On start-up, this signal appears with a duration of 5 s typ.(low level), and then widens to 38 s as the charging of CV246 progresses(related to the soft start, Pin 17).
NOTES :
CENTRE DEFORMATION TECHNIQUE
59
59
-
60
60
Regulator
Ph.2 AlignementDriver
LL008
SAFETY
Breathing
+10VSTBY
RL0013k3
VCC1
RV222680k
+10VSTBY
Softstart
Trame
+ UVERT
SSC35
V BLK
HFLYBLK
BGMultiplexer
control36
SMPS
I2C
6
TV002TIP122
RV001110k
24 22 23 44/12
RV00324k9
21
CV207220p CV206
220n
CV246220n
CV21347p
CL211470p
CL03927n
CL03827n
CL0301n9
CV216470p
CV22222n
RV216330R
JL004100R
RV2134k7
RL2142k7
RV206270k
TP170
TL062
Powersupply
anddeflectionsafeties
ON/OFF
18 19 33 17
H FLY
38
28
TL030
V SYNC
8
7
SLPF
Startoscillator
HDFL
VDFL
LDFL
Frame
BV01110
8
9
UpConvertor
CV247220p
13
Horizontalcounter
IV01
+13V LI
DL134
STV 2162
CENTRE DEFORMATION TECHNIQUE
-
SPECIFIC FEATURES OF STV2162
For the STV2162, the separation of synchronisation pulses has already beenperformed by circuit TDA9143 of the video module (50/100 Hz). This modulesupplies line and frame synchronisation signals, after conversion, witha clock:VDFL Pin 6 of IV001, 64-s square signal for a period of 10 ms.HDFL Pin 7 of IV001, positive 2.2-s pulse for a period of 32 s.LDFL Pin 8 of IV001, 27-MHz clock with amplitude 2Vpp.
The STV2162 incorporates an oscillator whose frequency depends on areference current (RV003, Pin 23) and regulation handled by Operating Mode(free frequency).This oscillator starts up the line time base, and is then synchronised by theHDFL pulses.After division, a counter then supplies a frequency of 31250 Hz, which isapplied to the second phase detector. This operates in exactly the same wayas in the STV2161.
The HDRIVE command is available on Pin 38. This gives a 2.9-s active lowlevel on start-up (soft start via CV246), and then 19 s at steady state.
NOTES :
CENTRE DEFORMATION TECHNIQUE
61
61
-
62
62
+10VSTBY
IV001
RV216330
38
HDRIVE
RL0013k3
RL0023k3 RL003
2k2
RL004
RL013
RL015
CV216470p
CL002560p
CL0011000
CL0084n7
CL00410
CL005
CL003220p
TL001BC847
TL005MPS750
DL003(*)
DL004(*)LL00633
CL00627p
TL004MPSW01R
RL014RL016RL017RL018
TL030LL001
(*) only for chassis 50Hz
DL001
CENTRE DEFORMATION TECHNIQUE
-
DRIVER STAGE
At the IV001 circuit output, the H DRIVE command goes through a low-passfilter that reduces interference caused by steep edges (RV216/CV216).
The line transistor command is issued via a driver transformer operating inForward Mode. A positive or negative current constantly passes through itsprimary.To do this, the base of the LL001 primary relies on a positive voltage ofabout 8 V (Capacitor CL005 charging) related to the duty cycle of theH DRIVE command.Driver Transistor TL001 is switched by this signal, and controls push-pullTL004/TL005.
The differences between the 100-Hz chassis and the 50-Hz chassis are thevalue of Resistor RL013 (10R for the 50-Hz version, and 4R7 for the 100-Hzversion), and the driver transformer, which has a lower leakage inductancefor the 100-Hz model (basic reverse current of TL030 goes to -4 A (-2 A forthe 50-Hz model)).In the event of a collector/emitter short circuit in TL004, Diodes DL003 andDL004 can be used to short-circuit the driver transformer primary also, whichtriggers the BREATHING input by sweep stop. From then on, TL005constantly conducts, and causes the rapid destruction of RL013.
NOTES :
CENTRE DEFORMATION TECHNIQUE
63
63
-
64
64
TL030
DL041
CL038//
CL039
DL043
HTR1
+USYS
HTR2
+USYS
LL032
LL029LL031
DL032
DL030CL031
CL032
RL030
DH
DL057
DL157
DL046
11
10
9
5
2
3
12
ZL041RL0400R27
CL041
CL0421000
CL045470
LL045+
U13
LL043
RL0432R2
CL043CL044100
RL045100k
+13V
+ UVFB
LL046
RL046 + RL048 CL146CL046
10
+ UVido
LL047 RL04747R
1
DL050
DL052
DL051
BREATHING
BEAM INFO
PKS
RL051RL052
+RL053RL044
//RL050
LL008
CL05210n
LL084
CL084 RL084
LL037RL124 RL127RL134 RL137
CL037
CL034LL034
CL036
DL034
DL036
RL0371k
safetycircuit
CL030
CL057100n
RL15547R
E/W
4
6
VCC1
RL092
DL092
7
8TEMPABL
CENTRE DEFORMATION TECHNIQUE
-
EHT AND LINE POWER
The primary of LL008, which is powered by voltage +USYS, is associatedwith line power transistor TL030 and diode modulator DL030, DL032, CL031,CL032.These switching elements also channel the current from the horizontaldeflector connected in series with the capacitor of S, CL037, and linearityself-induction coil LL037.A damper circuit connected in parallel with the capacitor of S suppresses theoscillations that are generated whenever the beam current varies at highspeed.For flat-screen tubes, resonating circuit LL034, CL034, which is tuned todouble the line frequency, provides dynamic correction of S.
The following are picked up on the secondaries of LL008:- Pins 2 and 3: a 27-Vpp pulse to heat up the filament, for 50-Hz tubes, or a
45-Vpp pulse for 100-Hz tubes.- Pin 5: 500-Vpp negative trigger pulse which supplies a voltage +U VIDEO
(200 V) after rectification in Forward Mode (DL046).- Pin 9: 400-Vpp negative trigger pulse which supplies a voltage +UVFB
(52 V) after rectification in Forward Mode (DL043).- Pin 10: 120-Vpp negative trigger pulse which supplies 13 V after
rectification in Forward Mode (DL041).- Pin 11: 35-Vpp positive trigger pulse which supplies an EHT control voltage
of 29 V after rectification in Flyback Mode (50-Hz chassis only). For 100-Hzchassis, this signal is obtained from capacitance bridge CL030, CL038,CL039 via DL157.
- Pin 1: The image of the instantaneous beam current, BEAM INFO andBREATHING (12 V for If = 0).
NOTES :
CENTRE DEFORMATION TECHNIQUE
65
65
-
66
66
VCC1
RL020
RL024
-
+PARABLE
GENERATORE/W
VERTICALSIGNAL
GENERATOR
+USYS LL008
RL052+
RL053
RL044//
RL050
1DL023
CL023RL023
RL025470R RL026
30
32
CL028RL027470R
CL0271n
EW BACK
EW DRIVE
RL129 CL029
LL029DL030
DL032
CL031
CL032
BEAM INFO
IV001
CENTRE DEFORMATION TECHNIQUE
-
EW STAGE
Circuit IV001 incorporates the E/W parabolic signal generator which issynchronised by the vertical ramp generator.Adjustments are therefore made via Operating Mode, and are routed viaBus I2C.
An amplifier also incorporated in IV001 delivers an EW DRIVE command inthe form of a current on Pin 32. This is applied to the Darlington transistor.It takes energy from the modulator via self-induction coil LL029.
The general negative feedback and the operating point are supplied bynetwork RL026, RL025, RL020, RL024, and VCC1. They correspond to theEW BACK signal on Pin 30. On the 50-Hz chassis, there is also a dynamicpulse width correction, performed by network DL023, CL023 and the BEAMINFO signal.
NOTES :
CENTRE DEFORMATION TECHNIQUE
67
67
-
68
68
-+
DV
RF015
RF012RF013
RF0234R7
RF0244R7
RF025
RV232100R
RV231100R
CV2321n
CV2311n
CF002
RV2331k
RF002
DF002
DF001
RF0032k7
RF00710k
FRAME DR25
DF00715V
+ UVERTCF029470
CF031100n
62 3
5
4
1
7
DF033
DF031
CF027100n
+ UVFB
DF011
RF0111R5 RF020
RF0361kDF028
CF0281
CF011470n
CF021100n
CF0152200
+13V
IF001TDA8177F
SENSEP
SENSEM
VERTICALSIGNAL
GENERATOR
PLLSOFT HSOFT V
CV23433n
262729C
VERT
DEFLECTIONAND
POWER SUPPLYSAFETIES
28
SAFETY
busI2C
IV001
JL004100R
RV222270k
CV2223n3
+USYS LL008
RL052+
RL053
RL044//
RL050
1TP170RL051
BREATHING
-+
CENTRE DEFORMATION TECHNIQUE
-
FRAME SWEEP
Two circuits are involved in the frame sweep.IV001 (STV2161 or STV2162) produces a frame sawtooth signal.IF001 (TDA8177F) amplifies this signal, and delivers the current to the framedeflector.
Video scanning processor IV001 includes a vertical ramp generator that usesCapacitor CV234 (Pin 29).The amplitude of this ramp is adjusted according to the BREATHING signalapplied to Pin 28 (dynamic height correction):
V Pin 28 = 8 V (VCC1) no correctionV Pin 28 = 1V5 maximum correction (5%)
This input is multiplexed with the interlock circuit so that, for a voltage below1 V, the sweep and power supply commands disappear (TP 170 saturated).Linearity and amplitude correction are also provided by IV001. They can beadjusted via Bus I2C in Operating Mode.An integrated op-amp delivers the FRAME DR signal on Pin 25. It receivesthe ac negative feedback (SENSEP, Pin 26) and dc negative feedback(SENSEM, Pin 27) signals. Its operating point is set by an internal dc framingvoltage which is adjustable in Operating Mode.
Circuit TDA8177F receives the previous command on its Pin 1. It is polarisedby bridge RF007/RF003 and Zener DF007.Voltages +UVERT (Pins 2 and 6) and +UVFB (Pin 3) power this circuit.The output at Pin 5 supplies current to the deflector. Resistors RF012,RF013, and RF023 through RF025 develop an image of the current at theirterminals for the negative feedback (SENSEP).
This stage is monitored by the interlock circuit. To do this, the signal pickedup from the deflector is rectified by the cell DF028, RF036, and CF028. A fallin the voltage obtained triggers conduction of TP170 and produces a levelbelow 1 V on the BREATHING pin of IV001 (Pin 28). The result of this is tostop sweeps and secondary regulation (see section on interlocks).
NOTES :
CENTRE DEFORMATION TECHNIQUE
69
69
-
70
70
VCC1
SAFE
TP175
TP170
TV002
VCC1
+10VSTBY
RP17210k
DP179
RP17722k
RP1764k7
IV001
RP17122k
RP17010k
RP1751K
CP17122
JL004100R
RP17922k
CP17947
DP175
IR001TR102
RR910
RR1031k
40
28
24
37SMPSOUT
TV_OFF
CP1704n7
38
DL057
-+
VCC1
CL038//
CL039
25
FRAMEDR
DL041IX001 + 9VREG
HTR1
+USYS
HDRIVE
TL01TL004/005
LL01
TL030
HTR2DH
TL063
RL0731k-
+
FRAMEDR
IF001
DV
CL0621n
9VREG
DF028RF0361k
CF0281
DL07111/24/33V
RL07143k
RL17113k
RL0721k
DL072
RL07027kDL070
BEAM_INFO
RL1491k
RL146470R
RL1472k2
DL147 DL148
11 CL148470n
CL0731
RL051 BREATHING
VCC1
RV221120k
RV223270k
DL221
RV222270k
CV2223n3
TL062 RL05610k
RL1601k RL058
10k5
RL0635k23
CL0631n
2
3
CL0611n
RL065100R
RL067/68/693 * 3k3
RL066
DL06647V
5VDP178RL0551k
RL0548k2
DL0603V3
RL06410k
CL0661n
DL157CL030
RL15547R
CL057100n
RL057
CL067
IL062TL082
5
67
DL30
DL32
CL031
CL032
1
Power supplysafeties
(+ US, - US)
BREATHING
IL062TL082
UPROT
13V
CENTRE DEFORMATION TECHNIQUE
-
TIME BASE INTERLOCKS
The interlock circuit detects short circuits in the line voltages or sweeps,disconnection of the deflectors, or racing of the beam current or EHT voltage.
The frame deflector signal supplies a voltage that polarises Zener DiodeDL071 and saturates Transistor TP175 via the SAFE line. Transistor TP170is therefore blocked.The following irregularities force a low level on the SAFE line, thus freeing thecharge from CP171 and saturating TP170.- Frame error by DL071,- Error on 9 volts REG (from +U13) by DL072 or 5 volts (from the power
supply, IP140) by DP178,- Filament error on 100-Hz tubes by DL147/148,- Racing of beam current by DL070 (I > 3 mA),- Increased line return value on diode modulator by Zener Diode DL066
and TL063,- Line deflector disconnection. This is detected through a decrease in
voltage UPROT (11 on LL008, DL157 (50-Hz chassis), CL030/38/39,DL157 (100-Hz chassis)) and a high level at 7 on IL062 (saturation ofTL063).
Using TR102, the microcontroller can force the interlock via the SAFE line.Two time constants delay the action of TP170 (CP179/RP179 andCP171/RP172).
The EHT voltage image is also controlled by the UPROT signal. In the eventof an increase in EHT voltage (35 to 40 V according to chassis), Output 1 ofIL062 goes to high state and saturates Transistor TL062.
With the BREATHING input forced to the low level, IV001 shuts off its powersupply and blocks the secondary regulation and sweep commands.If the error persists after two re-start attempts (three interlock triggerings), thetelevision reconfigures itself in Standby Mode and displays an error code.
NOTES :
CENTRE DEFORMATION TECHNIQUE
71
71
-
HIGH FREQUENCYINTERMEDIATE FREQUENCY
CONTENTS
CTT5000T TUNER
INTERMEDIATE FREQUENCY
CENTRE DEFORMATION TECHNIQUE
73
73
-
74
74
1
4
5
6
7
9
11
RH010
RH007RH008
DH001
5V
5V
CAG
CL2
DA2
USYS
FI
From 19 toII050
From 33/34to IR001
to TI020
FromPower supply
33V
TUNER
CENTRE DEFORMATION TECHNIQUE
-
CTT5000T TUNER
The CTT5000T tuner is equipped with a frequency synthesiser. It covers thefollowing frequency bands:
Band 1: 48.25 MHz to 112.25 MHz Band 3: 119.25 MHz to 399.25 MHz Bands 4 and 5: 407.25 MHz to 863.25 MHz
The following table gives information about the pins of this tuner.
NOTES :
CENTRE DEFORMATION TECHNIQUE
75
75
PIN COMMENT
HF AGC input
CL2IIC2 BUS
DA2
5 V
33 V
IF output
1
4
5
6/7
9
11
-
76
76
4k7RI003
10RRI001
15kRI005
180RRI004
330RRI05027R
RI023820R
RI021
1k8RI020
15RRI022
4k7RI040
4k7RI042
2k7RI041
2k7RI043
47RRI025
1kRI024
220RRI053
3k3RI054
1kRI055
1nCI072
15kRI006
B
H
0
0
1
*
3
47RRI076
1k5RI031
330RRI070
22kRI077
1kRI078
22kRI079
B
H
0
0
1
*
2
15kRI008
15kRI007
47RRI026
B
H
0
0
1
*
1
4n7CI022
5k6RI058
0RRI065
1k5RI083
6k8RI082
180RRI084
6k8
RI0596k8
RI061
5k6RI056
3k3RI074
3k3RI075
2k7RI073
2k7RI072
27RRI071
4n7CI078
100nCI050
100nCI008
4n7CI045
4n7CI052
100nCI071
15pCI009
6p8CI003
6p8CI005
100nCI053
4p7CI004
5p6CI002
1nCI001
10nCI020 1n
CI0401n
CI041
1nCI021
4n7CI056
39pCI055
4n7CI063
1uCI032
4n7CI077
27pCI007
56pCI010
22nCI011
4n7CI051
6
8
0
n
C
I
0
4
8
68pCI066
120p
CI064
4n7CI065
4n7CI073
4n7CI074
BA782SDI040
TI020BF799
JI910
BCR141NTI045
V
i
S
I
F
n
.
c
.
M
u
t
e
n
.
c
.
n
.
c
.
n
.
c
.
n
.
c
.
V
o
A
F
L
S
W
I
C
B
L
T
A
G
C
V
o
Q
S
S
V
o
v
i
d
V
i
v
i
d
A
F
C
V
C
O
1
V
C
O
2
C
V
P
/
2
G
N
D
C
V
A
G
C
V
p
I
N
S
W
I
V
i
S
I
F
V
o
C
V
B
S
S
T
D
C
S
A
G
C
T
P
L
L
T
A
D
J
V
i
V
I
F
V
i
V
I
F
V
i
V
I
F
V
i
V
I
F
TDA9811/V3II050
2u2CI060
GNDO2
O1
I2
I1
OFWK9453MFI020
BCR141NTI040
BA782SDI001
100nCI046
82RRI039
1k8RI038
BA782SDI041
BA782SDI051
BA782SDI002
JI928
TI070BC848BBA782S
DI070
BA782SDI071
u33LI020
22kPI050
68RRI035
JI90647p
CH009
GNDO2
O1
I2
I1
OFWK3954MFI010
GNDO2
O1
I2
I1
38M9FI015
JI901
2
u
2
C
I
0
6
1
47uCI062
22uCI031
2u2CI054
6
u
8
L
I
0
5
3
6,5MHzQI070
FI040
FI030
4n7CI070
BCR141NTI050
6u8LI070
10nCI030
2k2PI030
BCR141NTI010
B
H
0
0
1
*
4
B
H
0
0
1
*
5
B
H
0
0
1
*
6
B
H
0
0
1
*
7
B
H
0
0
1
*
8
B
H
0
0
1
*
9
B
H
0
0
1
*
1
0
B
H
0
0
1
*
1
1
1kRH001
1nCH001
22pCH002
2k7RH002
22pCH003
1
0
0
R
R
H
0
0
3
40,4MHzFI001
15kRH01022u
CH010
4n7CI033
31,9MHzFI002
100nCH004
100nCH005
12kRH007
4u7CH007
33VDH001
1nCH006
0
R
R
I
0
5
1
0
R
0
J
I
9
1
5
68RRI045R
H
0
0
4
0
R
4u7CH008
470RRI027
6MHzQI053
470RRI037
1k8RI032
BCR141NTI033
47uLH004
BC848BTI031
15RRI019
TI030BC858B
22kRI029
1k5RI034
2k2PI035 BC848B
TI032
22kRI028
BCR141NTI034
1kRI033
12kRH008
A
F
C
S
I
F
L
1
_
I
N
F
O
A
G
C
A
G
C
I
I
C
_
D
A
_
2
T
1
_
C
V
B
S
A
M
_
A
F
U
S
Y
S
B
G
_
I
N
F
O
+
5
V
+
5
V
+
5
V
I
_
I
N
F
O
I
I
C
_
C
L
_
2
N
O
R
M
GND_IF
(
P
)
L
BG
I
F
+
3
0
V
+
5
V
+
5
V
D
A
C
L
A
G
C
NH001
CTT5000
(
P
)
(
R
)
(
R
)
(
H
)
1110987654321
PLL
OSC
MIX
I
F
B1
B2
B3
(
X
)
(
H
)
(
P
)
(
P
)
(
A
)
(
A
)
17
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
31 30 29 28 27 26 25 24 23 22 21 20 19 18
15141312111098765432
6
8
p
1
23
6
8
p
5
5
4
4
3
3
2
2
1
1
32
161
5
4
2
1
3
CENTRE DEFORMATION TECHNIQUE
-
INTERMEDIATE FREQUENCY
Created using three surface wave filters and an integrated circuit:
FI010, two-sided Nyquist filter for picture selectivity in L' Band 3, L, D, K,and I (38.9 MHz) and L' Band 1 (33.9 MHz).
FI015, for picture selectivity in B and G. FI020, switchable filter, for sound selectivity in L' Band 3, L, D, K, I, B, and
G (32.4 MHz), and L' Band 1 (40.4 MHz). II050, TDA9811.
After leaving the tuner, the IF signal passes through two traps (40.4 MHz, outof operation in Band 1 L', and 31.9 MHz, in operation in B/G), is amplified byTI020, and informs Circuit II050 via the selectivities. The picture IF is injectedat 1/2 and at 3/4 of II050. The sound IF is injected at 31/32 of II050.Transistors TI040 and TI045 and Diodes DI040 and DI041 select the audioselectivity (DI040 passes in Band 1 L').
Integrated Circuit II050 performs the following functions: Picture IF amplification and demodulation (FI030 is used), FM sound and NICAM amplification, IF and HF AGC.
The demodulated video signal is available on Output 21 of II050. It passesthrough the FM audio intercarrier trap (FI040, 5.5 and 6.5 MHz) and isreinjected at 22 on II050. After amplification, this video signal is output at 10of II050. It passes through the FM audio intercarrier trap (QI053, 6 MHz), andis sent to the switching stage via PI035, TI032, TI030, or PI030, TI031, TI030.
PI035 adjusts the video level for L, L'.PI030 adjusts the video level for B, G, D, K, and I.TI033 and RI032 attenuate the video level for I.
The demodulated audio signal (from AM) is available on Output 12 of II050.
The NICAM and FM audio intercarriers are available on Output 20 of II050.They are amplified by TI070 via Switching Diodes DI070 (NICAM 5.85 MHz)and DI071 (FM), and are sent to the demodulation stage (MSP3410).
The HF AGC voltage is available on Output 19 of II050. PI050 adjusts it.
CENTRE DEFORMATION TECHNIQUE
77
77
-
SWITCHING
CONTENTS
VIDEO SWITCHING
AUDIO SWITCHING
RGB SWITCHING
CENTRE DEFORMATION TECHNIQUE
79
79
-
80
80
19
15
3
20
16
1086
21
19153
20
10
862
1 19153
20
10
862
1
TX620
TX622AMPLI
TX650
TX652AMPLI
TX505ES
RX403
RX330
RX406
RX331
BX400 BX50042 5
1513 17 11 9 19 12 17 15BX002BX001
206 5 3 1 8 10 11
18 17 16 14 15 13
TX965EF
TX955EF
TX960EF
TX950EF
TX920EF
TX910EF
FI
IX900
12 6 17 19 BV011BV021
AV2 AV1
AV3
from front panel sockets sat.
Y/V
V
C
C
Y/V
Y/V
Y/V
Y/VC C Y/V
V
Y/V C2 C1Y/V2 Y/V1 Y/V
to vido module
2
4
DA1
CL1
77
TX830
TX833
8
BX803IR - LINK
RX803
RX801RX802
45
61
44
32
31
AV1- 8
AV2- 8
EXT- LINK
IR001
SCI MODULE
MAINBOARD
CEN
TRE
DE
FORM
ATI
ON
TEC
HN
IQU
E
-
VIDEO SWITCHING
Integrated Circuit IX900 performs the switching of eight input sources(VIDEO or Y/C) to six outputs. Microcontroller IR001 controls this switchingvia Bus IIC1.
The values of the voltages from Pins 8 of the SCART connectors, arriving atPins 44 and 45 of Microcontroller IR001, indicate whether the source is 4/3or 16/9:
1.7 V < V < 3 V = 16/9 source 3.6 V < V < 5 V = 4/3 source
The table opposite summarises the video switching.
CENTRE DEFORMATION TECHNIQUE
81
81
FUNCTION INPUT OUTPUT
TV 20 of IX900
13 of IX90015 of IX90016 of IX90018 of IX900
AV1
11 of IX900
20 of IX900
15 of IX90016 of IX90018 of IX900
13 of IX900
AV2
5 of IX900 13 of IX90015 of IX90016 of IX900
AV3
1 of IX900
20 of IX900
15 of IX90016 of IX90013 of IX900
18 of IX900
-
82
82
3
86
21
3
862
1 3
862
1
1 3BX401from front panel sockets
RX737RX733
RX736
RX732
2 5 7 6 8 4 2 1 2 4 5 7BX002 BX700 BX001
4445 IR001
AV1AV2
AV3
BS0110 2 8 7 BS02
BA002BA001BS11 3 1 5 7 10 511 4 BS02
BA002
SIF
AM - AF
58 55 50 49 33 34 47 46 36 37 53 529
10
CL1
DA1
31 32
23BA001BS01
28 29 25 26
3 5
1 7
5 3
7 1IS60
AMPLIIS01
ADAPT.
15 13 BS02 1 3 BS03to headphone socketsto ampli and hps
BS04
IS40
GD GD D G
D D D D DG G G G G
SCI MODULE
AUDIOMODULE
MAINBOARD
CEN
TRE
DE
FORM
ATI
ON
TEC
HN
IQU
E
-
AUDIO SWITCHING
This switching takes place in the audio processor, IS40 (MSP3410).This audio processor is controlled by Microprocessor IR001 via Bus IIC1.The following table summarises the audio switching:
NOTES :
CENTRE DEFORMATION TECHNIQUE
83
83
FUNCTION INPUT OUTPUT
TV
55 of IS40or
55 / 58 of IS40or
58 of IS40
25 / 26 of IS4028 / 29 of IS4033 / 34 of IS4036 / 37 of IS40
AV1
25 / 26 of IS4028 / 29 of IS4033 / 34 of IS40
36 / 37 of IS40
AV2
49 / 50 of IS40 25 / 26 of IS4028 / 29 of IS4036 / 37 of IS40
AV3
46 / 47 of IS40
55 / 58 of IS40
25 / 26 of IS4028 / 29 of IS4036 / 37 of IS40
33 / 34 of IS40
52 / 53 of IS40
55 / 58 of IS40
-
84
84
3
86
21
3
862
1 3
862
1
1 3BX401from front panel sockets
RX737RX733
RX736
RX732
2 5 7 6 8 4 2 1 2 4 5 7BX002 BX700 BX001
4445 IR001
AV1AV2
AV3
BS00110 2 8 7 BS002
BA002BA001BS009 3 1 5 7 10 511 4 BS002
BA002
SIF
AM - AF
25 28 33 34 51 50 36 37 48 47 30 319
8
CL1
DA1
31 32
23BA001BS001
57 56 60 59
5 3
7 1IS220AMPLI
15 13 BS002 1 3 BS003to headphone socketsto ampli and hps
IS150
GD GD
D G GD GD D GGD
SCI MODULE
AUDIOMODULE
MAINBOARD
CEN
TRE
DE
FORM
ATI
ON
TEC
HN
IQU
E
-
AUDIO SWITCHING (DOLBY PROLOGIC)
This switching takes place in the audio processor, IS150 (MSP3410).This audio processor is controlled by Microprocessor IR001 via Bus IIC1.
The following table summarises the audio switching:
NOTES :
CENTRE DEFORMATION TECHNIQUE
85
85
FUNCTION INPUT OUTPUT
TV
28 of IS150or
28 / 25 of IS150or
25 of IS150
59 / 60 of IS15056 / 57 of IS15050 / 51 of IS15047 / 48 of IS150
AV1
59 / 60 of IS15056 / 57 of IS15050 / 51 of IS150
47 / 48 of IS150
AV2
33 / 34 of IS150 59 / 60 of IS15056 / 57 of IS15047 / 48 of IS150
AV3
36 / 37 of IS150
28 / 25 of IS150
59 / 60 of IS15056 / 57 of IS15047 / 48 of IS150
50/51 of IS150
30 / 31 of IS150
28 / 25 of IS150
-
86
86
15
11
7
20
16
8
1312
10
79
98
7
6
15 21
14
13
12
20
19
18
8
44
62
TV601
RV615
9VM
RV614
TV600
RV612
BV006
BV011
BX001
IV001
IV601
IR001
50HzVERSION
100HzVERSION
VIDEO MODULESCI MODULE
MAIN BOARD
R
V
B
FB
FB DET
CENTRE DEFORMATION TECHNIQUE
-
RGB SWITCHING
RGB and FB signals from SCART connector AV1 are sent to:
The video processor, IV001, for a 50-Hz television set. The demodulator, IV601, for a 100-Hz television set.
DETECTING A FAST SWITCH, FB (100-Hz MODEL)
The microcontroller must be informed of the presence of a fast switch toperform all switching of TV interfaces (RGB switching, mode display andinlay). The fast switch can, however, be in pulse form. This is what happensfor inlays. The fast switch occurs only when characters need to be displayedon screen. The microcontroller cannot constantly test for presence of a fastswitch; it does so periodically, at the rate allowed by its software. This is whythe appearance of a fast switch must be stored in memory. This is thefunction of TV600 or TV601, whose layout is equivalent to a pseudo-thyristor.
APPLICATION:
Pin 16 = 0 -> TV600/TV601 blocked -> input Pin 62 of MicrocontrollerIR001 = 4.5 V. The microcontroller interprets this as absence of fastswitching.
Pin 16 = 1.5 V -> TV600/TV601 saturated -> Pin 62 of microcontroller =0.8 V. The microcontroller identifies the presence of a fast switch.
If the fast switch disappears, Pin 16 = 0. Pin 62 of the microcontroller remainsat 0.8 V, because the thyristor effect keeps TV600 and TV601 saturated.This is a memory effect that allows the sequence to be completed.
As has already been mentioned, the microcontroller performs cyclicalresetting of Pin 62, which inhibits the thyristor effect. A few seconds after thefast switch disappears from Pin 16, Pin 62 of the microcontroller goes to 0,the thyristor effect disappears, 5 V at Pin 62. The microcontroller can detecta new fast switch at Pin 16.
NOTES :
CENTRE DEFORMATION TECHNIQUE
87
87
-
50HzVIDEO PROCESSING
CONTENTS
GENERAL INFORMATION
IC001, STV2151
GROUP DELAY COMPENSATION
IV001, STV2161
CENTRE DEFORMATION TECHNIQUE
89
89
-
90
90
SUBCARRIERTRAP
PAL/SECAM/NTSCIDENTIFICATION
PAL/SECAM/NTSCDEMODULATION
Y DELAY
R-Y/B-Y TRANSITION
RVB PROCESS
SWITCHING
RVB MATRIX
CRTCUT-OFF SERVO
BEAM LIMITER
BRIGHTNESSCONTRAST
SATURATION
IC001IV001
24
22
V/Y
C
20
6
7
Y 4
3
2
42
41
40
R
V
B
6 to 9RVB,FB
50,46 to 48RVB,FB
Y
R-Y
B-Y
TC002/003/004/008/041DELAY
COMPENSATION
(APX) CONTRASTCOMPENSATION
Y TRANSITION
CENTRE DEFORMATION TECHNIQUE
-
GENERAL INFORMATION
Two integrated circuits, controlled via Bus I2C, are used for video processing.
IC001, STV2151. This performs:
- Rejection of colour subcarriers,- Identification of colour: PAL/SECAM/NTSC,- Demodulation of colour: PAL/SECAM/NTSC.
IV001, STV2161. This performs:
- Luminance delay,- Improvement of R-Y and B-Y transitions,- Dematrixing of Teletext/OSD/SCART RGBs into Y, R-Y, and B-Y,- Switching of Y, R-Y, and B-Y,- Light, contrast, and saturation commands,- Automatic contrast compensation (APX),- Beam lock,- RGB matrixing,- Automatic control of tube cutoffs.
NOTES :
CENTRE DEFORMATION TECHNIQUE
91
91
-
92
92
IC001
AGC
OSCILLATOR O / 90
IDENT.B-Y
IDENT.R-Y
BUSINTERFACE
SOFTIDENT.
REFERANCEand
REGULATION
22
24
17 25 23
5
4
29981812
13
19
27
28
30
CVBS
SVHS
RC021
CC011
LC001
RC002
CC003
RC003
CC002
D
CK
DC001RC024
TC001
RC010RC011
9VREG
RC007CC012CC013
RC001
CC05CC004
QC0014,43MHzQC002
3,58MHz
V/Y
C
I. REF.
V. REF.
ID1 ID3
8,8V 7,7V 7V
3,85V
1,1V
0,5Vc/c
0,4Vcc
0,15Vcc
PAL
SECAMT=20ms
0,9Vcc
0,9Vcc ID2
4V
SECAM: 0,8VccPAL: 70mVcc
21
CENTRE DEFORMATION TECHNIQUE
-
IC001, STV2151
POWER SUPPLY
9VREG is the IC001 power source. Through a regulator built into IC001 andpower Transistor TC001, it powers the IC001 (Pin 18) with a typical voltageof 7.7 V. Resistor RC007 sets the reference current required for thisregulation.Diode DC001 brings this voltage down to a typical value of 7 V, which powersthe internal logic circuits of the IC001.A reference voltage value of 3.85 V typical (VCC/2) is obtained from theregulation stage.
IDENTIFICATION
During a colour standard search phase, IC001 is configured in PAL, SECAM,and then NTSC successively, until the standard is identified (four frameseach).The SECAM colour standard is identified by the frequency demodulation ofthe subcarrier bursts.The PAL/NTSC colour standards are identified by the amplitudedemodulation of the bursts.The dc voltages obtained are memorised in Capacitors CC002 and CC003(Pins 23 and 25), and supply the identification criteria.
CENTRE DEFORMATION TECHNIQUE
93
93
25 IC01ID1 ( B )
3.8V
4.85V
5.15V
5.25V
23 IC01ID3 (+R ) STANDARD
NO BURSTS
PAL
SECAM
NTSC
3.8V
2.75V
2.85V
3.75V
-
94
94
IC001
AGC
OSCILLATOR O / 90
BUSINTERFACE
22
24
17
5
4
19
27
28
30
CVBS
SVHS
RC021
CC011
LC001
D
CK
RC001
CC005CC004
QC0014,43MHzQC002
3,58MHz
V/Y
C
V. REF.
3,85V
4V
0,5Vcc
0,4Vcc
0,15Vcc
PAL
SECAMT=20ms
0,9Vcc
0,9Vcc
CLAMPCVBS
SVHS
26
20
21
1615
6710
DEMOD.R-Y
DEMOD.B-Y
PLL6MHzDETECTOR
COLORCONTROL
DELAY64s
DELAY64s
++
CC006
CC019
CC014
CC020
CC015
RC006
RC005
SSC R-YB-Y
V/Yto 19
BC011
to 17BC011
to TC002
to 6BC011
to 5BC011
to 2BC011
FH
0,3Vcc
4,4V
0,95Vcc1,1Vcc
2,9V 3V
3V
2,9V
20ms
40ms3,5V
3,5V
PINS 1, 2, 15, 16 :- SECAM SIGNALS ON- PAL/NTSC SIGNAL OFF (0)
4V
1,8V
1V12s
4s
1,4ms
SECAM:0,8VccPAL:70mVcc
CENTRE DEFORMATION TECHNIQUE
-
DEMODULATION
The video or luminance signal from the SCART switching part arrives at 24of IC001. The separate colour from the SCART switching part arrives at 22of IC001.
In IC001, the separate colour or video signals are sent to the input colour filter(bell or band pass). The tuning of this filter is automatically adjusted by a PLLloop. In PAL and NTSC, the PLL reference signal comes from the 4.43 MHzor 3.58