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DOI: 10.1109/APEC.2019.8721907

Citation: Z. Tong, S. Park, and J. Rivas-Davila,

"Empirical Circuit Model for Output Capacitance Losses

in Silicon Carbide Power Devices," in App. Power

Electronics Conf. and Expo. (APEC), Mar. 2019.

IEEE Xplore URL:

https://ieeexplore.ieee.org/document/8721907

Empirical Circuit Model for Output CapacitanceLosses in Silicon Carbide Power Devices

Zikang TongElectrical Engineering

Stanford UniversityStanford, CA 94305ztong@stanford.edu

Sanghyeon ParkElectrical Engineering

Stanford UniversityStanford, CA 94305

spark15@stanford.edu

Juan Rivas-DavilaElectrical Engineering

Stanford UniversityStanford, CA 94305

jmrivas@stanford.edu

Abstract: In recent reports, a variety of power devices,including wide-bandgap transistors, SiC diodes, and Sisuperjuction MOSFETs, exhibit losses occurring fromhysteretic charging and discharging of their output capac-itance (COSS for MOSFETs and CJ for Schottky diodes).In many instances and soft-switching power converterapplications, these losses are comparable to conductionlosses, especially for HF/VHF switching frequencies. Man-ufacturer SPICE models and datasheets do not reportthese losses, and are why device power dissipation insimulation significantly contrasts with that in actual con-verters. However, we propose a viable empirical circuitmodel that incorporates these losses, with capabilities tointegrate into circuit simulation tools such as SPICE. We,in addition, demonstrate the model by comparing devicepower dissipation in a class-E inverter and class-E rectifierbetween simulation and implementation.

I. INTRODUCTIONHigh-frequency (3-30 MHz) power converters have drawn

much attention because they are especially suitable for appli-cations such as plasma generation and wireless power transfer[1], [2] that demand power transfer at these high radio frequen-cies. Additionally, power electronics engineers are pushingswitching frequencies to the MHz range for dc-dc systemsas a means to reduce passive sizes [3]–[5]. For these fre-quencies, circuit designers implement soft-switching resonanttopologies to eliminate the frequency dependent switchinglosses exhibited by the semiconductor device while operatingat zero voltage switching (ZVS) [6]. The losses exhibited bythese power switches, whether a MOSFET or a diode, aretraditionally assumed to be dominated by conduction of the on-state resistance (RON ) and the forward voltage drop (VFWD)(for a diode). However, recent reports from [7]–[9] confirmthat SiC MOSFETs and Schottky diodes experience lossesfrom hysteretic charging and discharging of their paralleloutput capacitance (COSS or CJ ), observed in high voltageand high frequency applications [10]. These losses are notreported in manufacturer datasheets and SPICE models, andexplain why papers such as [11] and [12] display significantdifference in efficiency and device power dissipation between

simulation and implementation of converters. Although papershave reported COSS losses in other device technologies suchas Si superjuction (SJ) MOSFETs [13] and GaN HEMTs [14],their loss characteristics are rather complex and have nonlineardependencies with frequency, unlike SiC [7]–[9], which makesthem difficult to model. The actual device physics and mech-anisms for the output capacitance hystersis is not well studiedin literature. For Si superjunction (SJ) MOSFETs, one paper[15] reports that stranded charges trapped along the edge ofthe SJ trenches is the cause of COSS energy loss. However,at the current moment, very few literature analyze the lossorigins for GaN and SiC devices, and thus, there are no provenexplanations on why the COSS losses for these wide-bandgap(WBG) have different voltage and frequency dependencies.Much like how magnetic core losses are characterized bySteinmetz equations [16], hysteretic COSS and CJ lossescan also be fitted by a PLOSS = kfαV β equation. ForGaN devices the frequency dependency is typically with αequal to 1.6, where for SiC devices, the power losses arelinear with frequency [9]. Thus, there is a possibility and realuse for a circuit model that captures the losses from COSSand CJ in SiC parts, especially because these losses cannotsimply be modeled by an equivalent series resistance (ESR)[17]. In Section III, we explain how we develop the circuitmodel that represents these losses, and lastly we comparethe device power dissipation between a class-E inverter andrectifier to their SPICE simulations using our model and themanufacturer-provided model.

II. MEASURING COSS AND CJ LOSSES

COSS and CJ losses are measured using the Sawyer-Tower circuit shown in Figure 1. The measurement procedureis done similarly and explained in detail in [7]–[9], [13],[14]. The circuit charges and discharges the COSS or CJ ofthe device under test (DUT) using a large sinusoidal input.We obtain the instantaneous voltage across the device fromVDEV = VY − VX , as well as the the charge stored in theoutput capacitance from QDEV = CREFVX for each cycle.From Figure 2, we can calculate the net energy dissipated per978-1-5386-5541-2/18/$31.00 c©2018 IEEE

Figure 1: Schematic of Sawyer-Tower circuit used to measurethe large-signal charge-voltage hysteresis as shown in Figure2.

Figure 2: Voltage vs. charge curve of a sample device for onecycle on the Sawyer-Tower circuit swinging from 0 to 350 V.

cycle from the hysteresis through Equation 1.

EDISS =

∫ Q1Q0

VDEV dQDEV −∫ Q0Q1

VDEV dQDEV (1)

For this experiment, we studied two devices:IDM08G120C5 (1200 V, 8 A rated Schottky diode fromInfineon) and C3M0280090J (900 V, 11 A rated MOSFETfrom Cree). We swept our measurements from 200 to 600 Vin 50 V increments at 5, 10, and 15 MHz for the MOSFETand 5, 10, and 20 MHz for the diode. Since there is negligiblefrequency dependency, we fit the energy dissipated per cycleresults with a kV β equation displayed in Figures 5a and 5bin Section III. This results in a power dissipation linearlyproportional with frequency.

III. SPICE MODEL DEVELOPMENT

Figure 3 displays the circuit model for the COSS /CJ lossesin the dashed green box. The operation of the circuit is as

Figure 3: Schematic of the developed SPICE model. Ourfull model uses the manufacturer developed SPICE modelconnected in parallel to the COSS loss model which includes2 ideal diodes, a capacitor, and a dependent voltage sourcethat tracks VDS (or VKA for a diode).

follows: when the COSS or CJ of the device is charging,diode D1 turns on and delivers energy to charge CEXTRA.Once VDS begins to decrease, diode D1 turns off and D2turns on. When D2 is on, CEXTRA releases it’s stored energyto be dissipated by E1. The voltage across E1 is VDS becausethis allows CEXTRA to experience the same voltage swing asCOSS , even when D1 is turned off. Furthermore, D1 and D2are both ideal diodes. To highlight the operation of this circuit,we plot in Figures 4a and 4b the current through both idealdiodes, the voltage VDS , and the power dissipated by E1 aswe apply a sinusoidal voltage across the drain and the sourcewith the MOSFET off.

In general CEXTRA is a nonlinear capacitor that is lessthan 1% the size of the COSS or CJ , meaning that it will notsignificantly impact the operation of the device in a circuitapplication. In order to size the capacitance, we develop theSawyer-Tower circuit in LTSPICE by using a 1 nF capacitor asCREF and sweeping the peak voltage across the DUT from100 to 600 V in 50 V increments. To calculate the energydissipation per cycle in LTSPICE, we integrate the powerexhibited by E1 for one cycle.

To select the value for CEXTRA, we first follow Equation 2,where the energy loss of CEXTRA is defined as the integral ofthe capacitance times the voltage and set equal to the powerlaw fitting obtained from Sawyer-Tower measurements.

ELOSS =

∫ VPK0

CEXTRA(V ) · V dV = kV βPK ,

CEXTRA(V ) = κVγ

(2)

Because ELOSS is proportional to V β , CEXTRA must alsobe proportional to V κ where κ is another constant in order tosatisfy and simplify the relationship in Equation 2. Equation 3is then a reduced version of Equation 2, where the CEXTRA

(a)

(b)

Figure 4: (a) Voltage swing of the DUT and the powerdissipated by E1. (b) Currents through D1 and D2.

term is substituted.κ

2 + γV 2+γPK = kV

βPK (3)

From Equation 3, we can then solve for κ and γ, which arethe unknown parameters for CEXTRA.

γ = β − 2, κ = βk, CEXTRA(V ) = βkV β−2 (4)

Equation 4 expresses CEXTRA using k and β by solvingfor κ and γ. Equations 5 and 6 calculate the CEXTRA forthe IDM08G120C5 SiC diode and the C3M0280090J SiCMOSFET in units of pF respectively.

CEXTRA(V ) = 2.6V−0.068 (5)

CEXTRA(V ) = 39.5V−0.5 (6)

Figures 5a and 5b compare our model’s per cycle energy

dissipation in LTSPICE (labeled as green diamonds) with thekV β fit and Sawyer-Tower measurements.

(a) IDM08G120C5

(b) C3M0280090J

Figure 5: Energy dissipation per cycle vs. peak voltage swingacross three test frequencies for (a) IDM08G120C5 and (b)C3M0280090J.

IV. HARDWARE DEMONSTRATION OF MODEL

A. Converter Designs

We lastly demonstrate the accuracy of our model in con-verter applications by building a large choke inductance class-E inverter operating at 10 MHz and a class-E rectifier at both10 and 30 MHz.

For the inverter design, we use the procedure and equationsoutlined in [18] to select the component sizes for the inductorsand capacitors. Equation 7 is used to select the values of thecomponents.

LS =QRL2πfS

, CS =1

2πfSRL(Q− 1.1525), LF ≈ 10LS

(7)

Figure 6: Schematic of large choke inductance class-E inverter.

We also include a low-pass L matching network using LM andCM to lower the equivalent output impedance, allowing morefreedom in selecting CP . Equation 8 calculates the values forLM and CM based on the desired source impedance ZS andload impedance ZL [19].

LM =QZS2πfS

, CM =Q

2πfSZL, Q =

√ZLZS

− 1 (8)

Figure 7: Schematic of class-E rectifier with a power amplifierconnected to a notch filter serving as a sinusoidal currentsource.

Similarly for the current source-driven class-E rectifier, wefollowed the design procedure listed in [20]. We tuned therectifier for resistive impedance at the switching frequency andcontrolled the output power by controlling the sinusoidal inputcurrent level. To model the input current source, we drove therectifier with a 50 Ω power amplifier in series with a highquality factor notch filter to remove the harmonics outside thefundamental frequency. For this experiment we designed tworectifiers, one operating at 10 MHz and the other operating at30 MHz.

Table I: List of components for inverter.

Parameter Value

QSW C3M0280090J, Cree 900 V, 280 mΩ SiC MOSFETGate Drive LM5114, TI low-side gate drive IC

RG 2.5 ΩLF 52 µH, 5981002701 ferrite core

LM + LS 2.07 µHCIN 10 µFCP 39 pFCS 210 pFCM 400 pFRL 50 Ω RF dummy load

Table II: List of components for rectifier.

Parameter Value @ 10 MHz Value @ 30 MHz

DSW IDM08G120C5, Infineon 1200 V, 8 A SiC Schottky DiodePower Amplifier ENI A1000 RF PA, 0.3-35 MHz

CO 30 nF 30 nFCDEX 40 pF –CF 50.7 pF 247 pFLR 2.5 µH 350 nHLF 5 µH 1 µHRL 200 Ω (@ 50 W), 1 kΩ (@ 25 W) 1 kΩ

Figures 8a and 8b show the PCB photographs for theinverter and rectifier boards and Tables I and II list thecomponents’ values.

(a) Class-E Inverter PCB

(b) Class-E Rectifier PCB

Figure 8: (a) Photograph of PCB of class-E inverter. (b)Photograph of PCB of class-E-rectifier.

B. Validation of Model

To validate that the loss model does not impact the tuning ofthe circuit nor alter the voltage and current characteristics, weshow in Figures 9a, 9b, and 9c the comparison of the VDS andVAK waveforms of the simulation using the loss model and ofthe running converters. The overlapping and close similarities

(a) Inverter VDS Waveform (b) 10 MHz Rectifier VKA Waveform (c) 30 MHz Rectifier VKA Waveform

Figure 9: (a) VDS of MOSFET in class-E inverter; (b) reverse-bias voltage across diode in 10 MHz class-E rectifier; (c)reverse-bias voltage across diode in 30 MHz class-E rectifier

Figure 10: Comparison of device power dissipation in class-E inverter (left) and class-E rectifier (right) with manufacturersimulation model, our developed model, and thermal measurements.

between the lines in these plots confirm that our model doesnot impact circuit behavior.

C. Power Dissipation Accuracy of Model

Lastly, we compare the power dissipation exhibited bythe devices on the converters with what is observed in oursimulation models. In order to measure the device powerdissipation, we obtain the thermal impedance of the MOSFETand diode by sweeping the injected DC power and recordingthe device steady-state temperature after a 5 minute thermalsoak. We then obtain a linear fitting of the dc measurementsand the power dissipation of the device on the converter usingthe linear equation when measuring the temperature of thedevice with a FLIR thermal camera. From Figure 10, theSPICE model that incorporates COSS and CJ losses correlatesmuch closer to the power dissipation seen on the implementedconverters than that of the manufacturer SPICE model alone.Furthermore, we also observe from Table III that the errorin power dissipation between our simulation model and thethermal measurement is very small and only a few percent off.These results validate that the COSS /CJ loss model maintainsproper current-voltage behavior and accurately captures thedevice total loss.

Table III: Comparison of power dissipation seen fromsimulation with thermal measurement obtained fromTDEV ICE−TAMBIENT

RTHwhere RTH is the thermal impedance

obtained from the slopes in Figure 10.

Converter Conduction (& Gating) COSS/CJ Total Thermal Error

Inverter 3.13 W 0.67 W 3.80 W 3.71 W 2.64%10 MHz Rectifier 0.55 W 1.07 W 1.62 W 1.72 W 5.36%30 MHz Rectifier 0.45 W 1.52 W 1.97 W 1.94 W 1.73%

V. CONCLUSION

Previous literature has shown large differences in losses forSiC power devices between simulation and implementation ofHF/VHF converters because losses from capacitive chargingand discharging are not modeled in manufacturers’ simulationmodels. Thus, this paper develops an empirical circuit model,capable of being integrated in SPICE simulations, that repre-sents the COSS and CJ losses by tuning parameters for energydissipation to match with that of Sawyer-Tower measurements.Our developed model accurately matches device power dissi-pation recorded in simulation with what is also observed fromthermal measurements of our converters.

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