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Third-generation high-performance, programmable

universal frequency translator

Steven Shi, Jun 26th

© Integrated Device Technology

Agenda

• IDT Introduction• Timing Requirement in Communication• IDT Timing Portfolio and Evolution• UFT 3rd Generation Overview• UFT Family Technical Concepts• UFT 3rd Gen Device Key Features• Warp up

Snapshot Founded 1980

Workforce Approximately 1,700 employees

Headquarters San Jose, California

Core ExpertiseTiming, high speed mixed signal design, serial interconnects, memory interfaces, power management,and radio frequency (RF)

Sales Channels Worldwide network of direct, manufacturing representatives and distribution sales

FinancialsFY14 revenue - $484.8MMarket cap approx. - $1.78B Cash investments - $454M

Research and Development

Over $100M+/ year, leading to 900+ issued or pending patents

Mixed-signal, application-specific solutions

Timing and Synchronization Timing TimingTiming

Analogand Power Power ManagementPower ManagementWireless Power

Power Management

RF, Compression,Data Conversion

CommunicationsInfrastructure

EnterpriseComputingConsumer

Analog+Digital Solutions for Mobility, 4G & the Cloud

Interface and Connectivity

Memory InterfacePCI Express

Signal IntegrityRapidIO

PCI Express®

Timing Requirement in

Communication System

Personal View to Timing Market

1. Timing market is very fragmented, this market will be gradually dominated by a few company in several categories:

– Frequency translator (OSC, Crystal, MEMS) – Local timing (clock generator/synthesizer, buffer for CPU, I/F, Memory, …)– Programmable timing (lower cost),– Synchronized timing (including WAN PLL, Syn-E, 1588),

2. Key factors which influence the success for a timing company:– Performance (low rms jitter, spur free, high PSRR)– Cost– Power– Time to market– Programmable and Universal (i.e. VC5)

3. The trend of higher integration (SOC) will dilute the demand of timing;– Especially for local silicon timing

Communication Timing

• Timing technology/evolution in communication system are mainly driven by 3 markets in 3 application panels: 3 Markets:1. Wireless Base Station : ~30+% of CLK TAM

2. Datacom (Edge/Core, Enterprise/Carrier) : ~40% of CLK TAM

3. Optical Transportation (SDH, MSTP, DWM ,OTN): ~30-% of CLK TAM

3 Panels:1. Sync Panel (Sync-E, 1588)

2. Data Panel (PBO, Hitless Switch, Jitter Attenuator, i.e. WAN-PLL)

3. Control Panel (Local timing for CPU, I/F, and peripheral )

Example: Timing Solutions In Base Stations

CPRIOBSAI

PA

LNA

ADC LNA

Device clock (e.g. 122.88MHz)SYSREF (pulse)RF clock (700 MHz...3+ GHz)Recovered (e.g. 122.88MHz)

Base-band (Digital unit)Typ. 1 per BTS. Digital signal processing

DFE

JESD204BBufferJESD204B

Buffer

Distribution, Dly.

RFSynthesizerRF

Synthesizer

RF-Frequency Synth.0.8…3+GHz

Radio (TRx - transceiver)Typ. 3 per BTS. De-/Modulates thedigital signal, owns the air interface

DSPDSPDSP

NINPU

CPCPU

PHY

VCXO-PLLJESD204B

RF-PLL JA, Freq-Gen. Dly.(122.88, 153.6)*N …3GHz

Base station clock (3.84MHz x N)CPRI Domain (122.88MHz)DSP/Ethernet/Switch domain (156.25MHz)Recovered network clock

OCXOGPS

Sync to NetworkTransport I/F Clocks

Holdover

Network PLLSynchronization

CPRI-PLL

Freq. X-lator, JACPRI Clock Domain

Buffers

ASIC/FPGA

DSP and CPU PLLs

GeneratorsDSP, Proc. Clock domain

Buffers

DAC

ADC

IDT Timing Portfolio and Evolution

IDT Silicon Labs

On TI ADI Microsemi

Semtech Cypress Vectron Epson

RF Card PLL

RF Synthesizer

SyncE

IEEE 1588

Line Card WAN PLL

Prog Freq Translators

Synthesizers

Buffers

ZDB/ClockGen

Oscillators (XO)

VCXO

MEMS oscillators

TCXO/OCXO

One-Stop Timing Shop

IDT Timing Technology Evolution

0

2

4

6

8

10

12

14

2001 2003 2004 2009 2011 2012

RMS Phase Jitter, 12 KHz – 20 MHz

Ring OscillatorVCO (RO)

Improved RO2 ps LC VCO

“Femto”1 ps

LC VCO“FemtoNG”

0.5 ps

LC VCOImproved

“FemtoNG” 0.3 ps

LC VCORF SiGe0.056 ps

Performance ImprovementSince 2001: 214X!!

IDT Timing Performance Evolution

UFT 3rd Gen Overview

Universal Frequency Translator Family• Designed to solve the problems of Communications Line Cards

- But used in many different applications

• Many different frequencies required- Translates any input frequency to any unrelated output frequency- Frequencies from 8kHz to 1.0GHz

• PHYs and Switches for high-speed links need very low phase noise- RMS jitter as low as 0.25ps (12kHz – 20MHz)

• Redundancy support- Automatic hitless switching between 2-4 input references- Holdover for when all inputs lost- Alarm outputs for signaling to system software

• High integration- 1, 2, 3 or 4 PLLs per device (8 PLL device planned)

• Minimize need for SW interaction- Powers-up in desired configuration

Line Card (Rx Path)Timing Card

Line-Card Interface PLL• Communications systems will derive their timing from one of several sources

- Timing Card monitors / qualifies all sources & generates 1 master clock• Sources may include recovered clocks from one or more line cards, translated to lower frequency for backplane• Master clock is sent across backplane to many cards, so is usually fairly low freq: 8kHz, 19.44M, 25M

- Most other system clocks will be generated locally from this master clock- There is usually an Active & a Stand-by Timing Card that all other cards monitor

Timing CardTCXO

Timing Card

WAN-PLLGPS

LIUT1 / E1

Line Card (Tx Path)

Line Card (Rx Path)

Line-Card PLL

PHY

PHY

Line-Card PLL

PHY

PHY

Master Clock

Recovered ClocksActive

Stand-by

UFT 3rd GenCombines

these into 1 part

Universal Frequency Translator RoadmapProductionSampling NowCommittedPlanned

2nd Generation 3rd Generation

8T49N2032-in / 1-PLL

2 @ 1-freq outLVDS / LVPECL

40QFN

8T49N2222-in / 1-PLL2 freqs out

LVDS / LVPECL48QFN

8T49N2052-in / 1-PLL

PBO2 @ 1-freq out

40QFN

8T49N1051-in / 1-PLL

1 @ 1-freq out40QFN

8T49N2444-in / 2-PLL

4 @ 2 freqs outLVDS / LVPECL

80BGA8T49N3666-in / 3-PLL






80BGA


LVDS/PECL/CMOS56QFN8T49N2832-in / 2-PLL8 freqs out

LVDS/PECL/CMOS56QFN8T49N2824-in / 2-PLL8 freqs out

LVDS/PECL/CMOS72QFN


LVDS/PECL/CMOS88QFN

Sample: Q2’14

Low Cost1Small Footprint

LVDS/PECL/HCSL/CMOS

40QFNSample: Q3’14


LVDS/PECL/HCSL/CMOS


Low Cost2Small FooprintLVDS/PECL/HCSL/CMOS



LVDS/PECL/HCSL/CMOS



LVDS/PECL/HCSL/CMOS


Universal Frequency Translator 3Gen -Extending the Family

• Any Input to Any Output• Programmable FemtoClock® NG Universal

Frequency Translators (UFT) support 1, 2, 3 or 4 PLLs in a single package

• When used as a frequency synthesizer, accepts input from low-cost readily-available quartz crystals

• When used as a frequency translator, accepts up to four input reference clocks per PLL from 8 kHz up to 875 MHz

Benefits Fully programmable clock source adds flexibility to the design cycle Up to 4 clock inputs with automatic hitless switching Multiple options for full functionality at power-up without complex user programming Extremely low RMS jitter on all outputs for high-end communication applications

演示者

演示文稿备注

The IDT FemtoClock® NG Universal Frequency Translator (UFT) is a fully programmable clock source that adds flexibility to a customer’s design and design cycle. Family members are available that support 1, 2, 3 or 4 PLL’s in a single package. As a frequency synthesizer, the device can use a low-cost crystal from 16 to 40M and produce any frequency from 1Mhz to 1.3GHz, regardless of the crystal frequency used. As a frequency translator, the devices accept 1 or 2 input reference clocks per PLL from 8 kHz to 710 MHz, switching between them as necessary and generate any output frequency from 1 MHz to 1.3 GHz with no accuracy error in most cases. Each output is individually programmable as LVPECL or LVDS. Versions of the UFT with single-ended outputs are also available.

Solve Complex Clocking Problems Simply

The 1st integrated, programmable solution on the market that can generate up to 8 different output frequencies and provide jitter attenuation performance of less than 0.3ps (12kHz to 20MHz).

8T49N282i shown

• Generates high-performance clocks from inexpensive sources

- RMS jitter <0.3ps (12kHz to 20MHz)

• High-flexibility supports multiple configurations and applications

• High integration combines numerous functions into a single small package

• IDT Timing Commander makes programming setup simple

EXAMPLE APPLICATIONS

●Optical Transport Network muxponders●10/40/100GE routers●Wireless base-stations

演示者

演示文稿备注

Product positioning statement �UFT++ is a flexible synthesizer / jitter attenuator that provides communication line cards and other high performance applications with required phase noise, redundancy, frequency diversity, and integration features by building upon the existing UFT family and leveraging proven high performance timing technology from IDT.

Generate High-Performance Clocks• Generates references clocks suitable for

high-speed PHYs, switches and other demanding applications

- <0.3ps RMS (12kHz – 20MHz)

• Output frequencies can be synthesized using an inexpensive, fundamental-mode crystal

- Any frequency from 10MHz to 40MHz

• Output frequencies can also be synthesized from one of up to 4 input references

- High-jitter or gapped inputs can be used

• Break-through fractional output divider technology generates independent clock frequencies with <0.7ps RMS jitter

• Generate outputs with or without input references

- Synthesizer or Jitter Attenuator• Reliable operation via input monitors,

switchover and holdover• Gapped clock support inter-operates

with OTN mappers and PHYs• Programmable loop bandwidth

enables different scenarios without changing external components

• Signal path options support whatever the user wants to do

• Independent dividers on each output allow up to 8 different frequencies from a single device

• Self-configuration provides clocks before software is running• Unused blocks can be turned off to save power

Same Device / Many Configurations

IDT Timing Commander view of 8T49N282i

IDT Timing Commander SoftwareMaking complex configuration simple!

Accompanied with World-Class Support

COMPLETE PRODUCT SUPPORT●Product Brief

●Short-form & long-form datasheets

●Evaluation board with user manual

●Timing Commander Software with User Manual

● Stand-alone and evaluation board configuration

● Phase noise & power estimation

● PLL Gain & Phase Transfer plots

● Input & output termination generator

●Instructional video(s)

●Reference schematic & Layout guidelines

●IBIS Models

●EEPROM load generator

www.idt.com/go/UFT

UFT Family Technical Concepts

Hitless Switching• Hitless Switching – Red Line

- Sometimes also called Phase Build-out or Fully Hitless Switching.

• When a switchover occurs, there will be no change to the phase of the output. In transition, there is a very small disturbance (Initial Frequency Offset) UFT+ 8T49N205: 4.5ns UFT 3rd Gen: 50ppb

• Output will track changes in phase on new input

Q0

Switchover

-9.80E-05

-9.79E-05

-9.79E-05

-9.78E-05

-9.78E-05

-9.77E-05

-9.77E-05

000.0E+0 10.0E-3 20.0E-3 30.0E-3 40.0E-3 50.0E-3 60.0E-3 70.0E-3 80.0E-3

Output Phase PlotSwitchover

Hitless Switching: Output phase is no change.

Without Hitless Switching. (Phase-Slope Limit)

Phase-Slope Limit• Phase-Slope Limit - Blue line• Rate of change of output phase kept below specific value (e.g. 62µs/s)Output will

track changes in phase on new input UFT+ 8T49N205: 4.5ns UFT++: 50ppb

Q0

Switchover

-9.80E-05

-9.79E-05

-9.79E-05

-9.78E-05

-9.78E-05

-9.77E-05

-9.77E-05

000.0E+0 10.0E-3 20.0E-3 30.0E-3 40.0E-3 50.0E-3 60.0E-3 70.0E-3 80.0E-3

Output Phase PlotSwitchover

Phase-Slope Limit

e.g. 62µs/s (62fs/ns)(9.7ppm/s at 156.25MHz)

Support for Gapped Clocks• What is a Gapped Clock?

- PHY devices recover a clock from the line and provide it as a reference clock

- OTN line may contain extra idles to prevent under-runs on Rx- OTN frame may contain extra overhead bytes that can be stripped

by framer- Many OTN framers remove unneeded bytes by suppressing clock

pulses of reference clock

PHY Rx FIFO

Dat

a

Idle

Dat

a

Dat

a

Dat

a

Dat

a

Dat

a

Dat

a

Dat

a

Dat

a

O/H

O/H

O/H

Dat

a

Dat

a

Dat

a

UFT

161.1328125MHzrecovered line clockwith2 gaps per 66 clocks

156.25MHzjitter-free clock= 64/66 * 161.1328125MHz

Operating ModesFrequency Synthesizer

Fractional-feedback PLL allows for any output frequency to be generated

Low BW Translator (Jitter Attenuator)

Selected input pre-scaledCompared to scaled PLLFractional-feedback PLL steered by

comparison- Gives jitter attenuation

Xtal+PLL similar to VCXO- Crystal is fixed freq

XTAL FracNPLL ÷ Nx 1 /

x 2

FracNPLL ÷ N

0

1÷ P

XTAL x 1 /x 2

÷ M1÷ P

• Three options for setting device power-up configuration1. Power-up with outputs disabled (-999 order code)

• Configuration always written over serial port by CPU or FPGA2. Custom configuration factory-programmed into OTP

• Custom ‘dash code’ part number assigned• Work with IDT FAEs to generate

• 1 or 2 configurations held internally3. Self-load from external serial EEPROM (UFT 3rd Gen)

• Arbitrates to be I2C bus master then reads from EEPROM

• Power-up defaults may be over-written at any time- I2C not required if power-up configuration is satisfactory

• Write-Protect pin disables I2C writes (8T49N282)- Interrupt ‘sticky’ bits are excepted from protection

Device Configuration Options

UFT 3rd Gen Device Detailed Features

3rd Gen UFT Feature Overview• Addresses several applications areas

- Universal Frequency Synthesizer- Line card frequency translation / synchronization- Radio card frequency synthesis

• 4 input references (8kHz – 875MHz)- 2 inputs only on 8T49N281 & 8T49N283

• 8 output frequencies (8kHz – 1.0GHz) :- 2 ‘clean’ outputs @ <0.3ps (12kHz – 20MHz) RMS jitter- 4 ‘flexible’ outputs @ <0.4ps (12kHz – 20MHz) RMS jitter- 2 Fractional Output Divider outputs <0.7ps (12kHz – 20MHz) RMS jitter

• Programmable loop bandwidths (0.5Hz – 512Hz)

• Outputs programmable: LVPECL, LVDS or 2xLVCMOS at 2.5V / 3.3V- LVCMOS also supports 1.8V operation

• Packaged in 56QFN (8x8mm) or 72QFN (10x10mm) packages- Power dissipation 1.0 – 1.75W (configuration-dependent)

3rd Generation Universal Frequency Translator• Input Jitter Attenuator + Frequency Translator mode

Programmable loop bandwidths (0.5Hz – 512Hz)

• Universal Frequency Synthesizer mode• Multiple input references (8kHz-875MHz)

Input quality monitoring, with auto switching, holdover support

• Outputs as many as 8 frequencies (8kHz-1.0GHz)2 ‘high performance’ outputs @ <0.3ps (12kHz – 20MHz) RMS jitter4 ‘flexible’ outputs @ <0.4ps (12kHz – 20MHz) RMS jitter2 Fractional Output Divider outputs <0.7ps (12kHz – 20MHz) RMS jitter

● Multi-channel1, 2, 3 or 4 PLLs in a single package

● Universal outputs: LVPECL, LVDS, LVCMOS – 2.5/3.3/1.8V

Any combination1.8V for LVCMOS only

● Single 3.3V power supplySimple power filteringIntegrated LDO’s

● Power savingsSimple disabling of unused blocks

● Packages:56QFN (8x8mm) or 72QFN (10x10mm)

IDT8T49N282i (72QFN) Block Diagram

IntN OutputDivider

IntN OutputDivider

FracN OutputDivider

FracN OutputDivider

FractionalFeedback

PLL 0

FractionalFeedback

PLL 1

Input ClockMonitoring,

Priority,&

Selection

Status Registers

Bypass 0Bypass 1

Control Registers

GPIOLogic

Lock 0Holdover 0

Lock 1Holdover 1

4

OSCXTAL

÷ P0Clk0

OTPI2C Master

I2C Slave

ResetLogic

SCLKSDATA

Serial EEPROM

LOS[3:0]

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

÷ P1Clk1

÷ P2Clk2

÷ P3Clk3

nINT

nRST

LOS

IntN

IntN

IntN

IntN

nWP SA0, SA1 PLL_BYPOE

82

HOLD

2

LOCK


IntN OutputDivider

IntN OutputDivider

FracN OutputDivider

FracN OutputDivider

FractionalFeedback

PLL 0

FractionalFeedback

PLL 1


Priority,&

Selection

Status Registers

Bypass 0Bypass 1

Control Registers

GPIOLogic

Lock 0Holdover 0

Lock 1Holdover 1

OSCXTAL

÷ P0Clk0

OTPI2C Master

I2C Slave

ResetLogic

SCLKSDATA

Serial EEPROM

LOS[3:0]

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

÷ P1Clk1

nINT

IntN

IntN

IntN

IntN

SA0 PLL_BYP

4

GPIO

nRST


IntN OutputDivider

IntN OutputDivider

FracN OutputDivider

FracN OutputDivider

FractionalFeedback

PLL


Priority,&

Selection

Status Registers

Bypass

Control Registers

GPIOLogic

LockHoldover

OSCXTAL

÷ P0Clk0

OTPI2C Master

I2C Slave

ResetLogic

SCLKSDATA

Serial EEPROM

LOS[3:0]

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

÷ P1Clk1

nINT

IntN

IntN

IntN

IntN

SA0 PLL_BYP

4

GPIO

nRST

Automatic Switchover Mode• UFT 3rd Gen 8T49N28x has Input Clock Monitor

- The monitor logic for each input reference will count the number of monitor clock edges indicated in the appropriate Clock Monitor register. If an edge is received on the input reference being monitored, then the count resets and begins again. If the target edge count is reached before an input reference edge is received, Input reference clock switch over to another reference clock.

- The monitor clock is fixed at the frequency of PLL0’s VCO divided by 8. With a VCO range of 3GHz - 4GHz, the monitor clock has a frequency range of 375MHz to 500MHz

CLK0

CLK1

If the target edge count is reached before an input reference edge is received, Input reference clock switch over to another reference clock.

Monitor Clock

LOS_m counter expired.A LOS_m counter value is a Reference clock period + 2~3 monitor clock.

Historical Holdover• UFT 3rd Gen supports an initial holdover frequency offset of ±50ppb in non-gapped

clock mode.• Once in holdover, there are 3 options on how it behaves:

Q0

CLK0

Monitor Clock Loss of Signal is detected.

Instantaneous ModeInstantaneously use the DPLL current frequency 100msec ago. Phase is adjusted with selected Phase-Slope Limit.

Holdover

Fast Average Mode

Return to Center of VCO Tuning Range

Transition at a rate dictated by its selected Phase-Slope Limit setting to a frequency offset setting that is based on historical settings over 10min.

Instantaneously use the Center of VCO Tuning Range. Phase is adjusted with selected Phase-Slope Limit.

Live Adjustment of Output Frequency

• May be used for frequency margining or digital frequency adjustment• Analog PLL feedback divider may be updated via serial port while running

- All relevant registers written in one burst so internal registers simultaneously updated- Analog PLL’s 200kHz loop filter will strongly attenuate effect of change on output

• The Analog PLL feedback divider has 9-bits of integer and 21-bits of fraction giving frequency adjustment resolutions as small as 1.2ppb

演示者

演示文稿备注

Resolution = lowest divide ratio of 37.5 (80MHz into 3000MHz) adjusted by one LSB (21st fraction bit) = 2^-21 / 37.5 = 12.71*10e-9 Up to highest divide ratio of 400 (10MHz into 4000MHz) = 1.19ppb

Output Type Options

• Each output may choose from one of 4 types:1. LVDS2. LVPECL3. 2 x LVCMOS – inverted phase from each other4. 2 x LVCMOS – in-phase with each other5. HCSL coming soon on 8T49N285/6/7

• Each output may independently select 2.5 or 3.3 V• Each output may have its polarity inverted• Each output may be programmed to come-up

enabled or high-impedance

Simple Power Supply Filtering

Bottom of the Evaluation Board8T49N282 (2 channels)

All power regulated with internal LDOs

Wrap-Up

Summary• IDT is the undisputed leader in timing

- Market leadership- Technology Leadership- Breadth of product- Programmability and Customization- Performance and Power- World class support

• IDT’s Universal Frequency Translator family is representative of this leadership

- Flexibility and high-performance - Optimized for communications applications- Flexible enough for multiple applications

• The newest products add even more capability to the family

- Many additional features to provide increased flexibility

- Improved jitter performance - Simple configuration with Timing Commander

Software

www.idt.com/go/uft

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