The Designer’s Guideto VHDL

Third Edition

The Morgan Kaufmann Series in Systems on SiliconSeries Editor: Wayne Wolf, Georgia Institute of Technology

The Designer’s Guide to VHDL, Second EditionPeter J. Ashenden

The System Designer’s Guide to VHDL-AMSPeter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden

Modeling Embedded Systems and SoCsAxel Jantsch

ASIC and FPGA Verification: A Guide to Component ModelingRichard Munden

Multiprocessor Systems-on-ChipsEdited by Ahmed Amine Jerraya and Wayne Wolf

Functional VerificationBruce Wile, John Goss, and Wolfgang Roesner

Customizable and Configurable Embedded ProcessorsEdited by Paolo Ienne and Rainer Leupers

Networks-on-Chips: Technology and ToolsEdited by Giovanni De Micheli and Luca Benini

VLSI Test Principles & ArchitecturesEdited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen

Designing SoCs with Configured ProcessorsSteve Leibson

ESL Design and VerificationGrant Martin, Andrew Piziali, and Brian Bailey

Aspect-Oriented Programming with eDavid Robinson

Reconfigurable Computing: The Theory and Practice of FPGA-Based ComputationEdited by Scott Hauck and André DeHon

System-on-Chip Test ArchitecturesEdited by Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba

Verification Techniques for System-Level DesignMasahiro Fujita, Indradeep Ghosh, and Mukul Prasad

VHDL-2008: Just the New StuffPeter J. Ashenden and Jim Lewis

On-Chip Communication Architectures: System on Chip InterconnectSudeep Pasricha and Nikil Dutt

Embedded DSP Processor Design: Application Specific Instruction Set ProcessorsDake Liu

Processor Description LanguagesPrabhat Mishra

The Designer’s Guideto VHDLThird Edition

Peter J. AshendenEDA CONSULTANT, ASHENDEN DESIGNS PTY. LTD.

ADJUNCT ASSOCIATE PROFESSOR, ADELAIDE UNIVERSITY

Morgan Kaufmann Publishers is an imprint of Elsevier.30 Corporate Drive, Suite 400, Burlington, MA 01803, USA

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Library of Congress Cataloging-in-Publication DataAshenden, Peter J.

The designer’s guide to VHDL / Peter J. Ashenden. -- 3rd ed.p. cm. -- (The Morgan Kaufmann series in systems on silicon)

Includes bibliographical references and index.ISBN 978-0-12-088785-9 (hardcover : alk. paper) 1. VHDL (Computer hardware description language)

2. Electronic digital computers--Computer simulation. I. Title.

TK7888.3.A863 2008621.39'2--dc22

2008011059

ISBN: 978-0-12-088785-9

For information on all Morgan Kaufmann publications,visit our Web site at www.mkp.com or www.books.elsevier.com

Printed in the United States.08 09 10 5 4 3 2 1

To my wife Katrina

vii

Contents

Preface xvii

1 Fundamental Concepts 11.1 Modeling Digital Systems 11.2 Domains and Levels of Modeling 3

1.2.1 Modeling Example 31.3 Modeling Languages 71.4 VHDL Modeling Concepts 7

1.4.1 Elements of Behavior 81.4.2 Elements of Structure 101.4.3 Mixed Structural and Behavioral Models 121.4.4 Test Benches 131.4.5 Analysis, Elaboration and Execution 14

1.5 Learning a New Language: Lexical Elements and Syntax 161.5.1 Lexical Elements 17

Comments 17Identifiers 19Reserved Words 20Special Symbols 22Numbers 22Characters 23Strings 23Bit Strings 24

1.5.2 Syntax Descriptions 26Exercises 29

2 Scalar Data Types and Operations 312.1 Constants and Variables 31

2.1.1 Constant and Variable Declarations 312.1.2 Variable Assignment 33

2.2 Scalar Types 342.2.1 Type Declarations 342.2.2 Integer Types 352.2.3 Floating-Point Types 382.2.4 Physical Types 39

Time 422.2.5 Enumeration Types 43

Characters 44Booleans 46

viii Contents

Bits 47Standard Logic 48Condition Conversion 49

2.3 Type Classification 512.3.1 Subtypes 522.3.2 Type Qualification 532.3.3 Type Conversion 54

2.4 Attributes of Scalar Types 542.5 Expressions and Predefined Operations 57Exercises 62

3 Sequential Statements 653.1 If Statements 65

3.1.1 Conditional Variable Assignments 683.2 Case Statements 69

3.2.1 Selected Variable Assignments 743.3 Null Statements 753.4 Loop Statements 76

3.4.1 Exit Statements 773.4.2 Next Statements 803.4.3 While Loops 813.4.4 For Loops 833.4.5 Summary of Loop Statements 86

3.5 Assertion and Report Statements 87Exercises 93

4 Composite Data Types and Operations 954.1 Arrays 95

4.1.1 Multidimensional Arrays 984.1.2 Array Aggregates 994.1.3 Array Attributes 103

4.2 Unconstrained Array Types 1054.2.1 Predefined Array Types 106

Strings 106Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors 106Bit Vectors 107Standard-Logic Arrays 108String and Bit-String Literals 108

4.2.2 Unconstrained Array Element Types 1094.2.3 Unconstrained Array Ports 111

4.3 Array Operations and Referencing 1144.3.1 Logical Operators 1144.3.2 Shift Operators 1164.3.3 Relational Operators 117

Maximum and Minimum Operations 1194.3.4 The Concatenation Operator 1194.3.5 To_String Operations 120

Contents ix

4.3.6 Array Slices 1204.3.7 Array Type Conversions 1224.3.8 Arrays in Case Statements 1244.3.9 Matching Case Statements 125

Matching Selected Variable Assignments 1274.4 Records 128

4.4.1 Record Aggregates 1314.4.2 Unconstrained Record Element Types 131

Exercises 134

5 Basic Modeling Constructs 1375.1 Entity Declarations and Architecture Bodies 137

5.1.1 Concurrent Statements 1415.1.2 Signal Declarations 141

5.2 Behavioral Descriptions 1435.2.1 Signal Assignment 143

Conditional Signal Assignments 146Selected Signal Assignments 147

5.2.2 Signal Attributes 1495.2.3 Wait Statements 1515.2.4 Delta Delays 1555.2.5 Transport and Inertial Delay Mechanisms 1585.2.6 Process Statements 1645.2.7 Concurrent Signal Assignment Statements 166

Concurrent Simple Signal Assignments 166Concurrent Conditional Signal Assignment 167Concurrent Selected Signal Assignments 171

5.2.8 Concurrent Assertion Statements 1735.2.9 Entities and Passive Processes 174

5.3 Structural Descriptions 1765.4 Design Processing 186

5.4.1 Analysis 1865.4.2 Design Libraries and Contexts 188

Context Declarations 1905.4.3 Elaboration 1935.4.4 Execution 195

Exercises 197

6 Subprograms 2076.1 Procedures 207

6.1.1 Return Statement in a Procedure 2126.2 Procedure Parameters 213

6.2.1 Signal Parameters 2176.2.2 Default Values 2206.2.3 Unconstrained Array Parameters 2216.2.4 Summary of Procedure Parameters 224

6.3 Concurrent Procedure Call Statements 225

x Contents

6.4 Functions 2276.4.1 Functional Modeling 2306.4.2 Pure and Impure Functions 2306.4.3 The Function now 232

6.5 Overloading 2336.5.1 Overloading Operator Symbols 234

6.6 Visibility of Declarations 236Exercises 240

7 Packages and Use Clauses 2457.1 Package Declarations 245

7.1.1 Subprograms in Package Declarations 2507.1.2 Constants in Package Declarations 250

7.2 Package Bodies 2527.2.1 Local Packages 255

7.3 Use Clauses 2577.3.1 Visibility of Used Declarations 261

Exercises 264

8 Resolved Signals 2678.1 Basic Resolved Signals 267

8.1.1 Composite Resolved Subtypes 2728.1.2 Summary of Resolved Subtypes 2788.1.3 IEEE std_logic_1164 Resolved Subtypes 278

8.2 Resolved Signals, Ports, and Parameters 2808.2.1 Resolved Ports 2828.2.2 Driving Value Attribute 2858.2.3 Resolved Signal Parameters 286

Exercises 287

9 Predefined and Standard Packages 2939.1 The Predefined Packages standard and env 2939.2 IEEE Standard Packages 296

9.2.1 Standard VHDL Mathematical Packages 296Real Number Mathematical Package 296Complex Number Mathematical Package 299

9.2.2 The std_logic_1164 Multivalue Logic System 3019.2.3 Standard Integer Numeric Packages 3049.2.4 Standard Fixed-Point Packages 3139.2.5 Standard Floating-Point Packages 3189.2.6 Package Summary 322

Operator Overloading Summary 323Conversion Function Summary 326Strength Reduction Function Summary 334

Exercises 335

Contents xi

10 Case Study: A Pipelined Multiplier Accumulator 33710.1 Algorithm Outline 33710.2 A Behavioral Model 340

10.2.1 Testing the Behavioral Model 34210.3 A Register-Transfer-Level Model 346

10.3.1 Testing the Register-Transfer-Level Model 350Exercises 353

11 Aliases 35511.1 Aliases for Data Objects 35511.2 Aliases for Non-Data Items 360Exercises 363

12 Generics 36512.1 Generic Constants 36512.2 Generic Types 37212.3 Generic Lists in Packages 376

12.3.1 Local Packages 38112.3.2 Abstract Data Types Using Packages 384

12.4 Generic Lists in Subprograms 38912.5 Generic Subprograms 39412.6 Generic Packages 407Exercises 414

13 Components and Configurations 41713.1 Components 417

13.1.1 Component Declarations 41713.1.2 Component Instantiation 41913.1.3 Packaging Components 420

13.2 Configuring Component Instances 42213.2.1 Basic Configuration Declarations 42213.2.2 Configuring Multiple Levels of Hierarchy 42513.2.3 Direct Instantiation of Configured Entities 42813.2.4 Generic and Port Maps in Configurations 42913.2.5 Deferred Component Binding 435

13.3 Configuration Specifications 43713.3.1 Incremental Binding 438

Exercises 444

14 Generate Statements 44914.1 Generating Iterative Structures 44914.2 Conditionally Generating Structures 455

14.2.1 Recursive Structures 46214.3 Configuration of Generate Statements 465Exercises 473

xii Contents

15 Access Types 47915.1 Access Types 479

15.1.1 Access Type Declarations and Allocators 47915.1.2 Assignment and Equality of Access Values 48215.1.3 Access Types for Records and Arrays 483

15.2 Linked Data Structures 48615.2.1 Deallocation and Storage Management 490

15.3 An Ordered-Dictionary ADT Using Access Types 491Exercises 495

16 Files and Input/Output 49916.1 Files 499

16.1.1 File Declarations 49916.1.2 Reading from Files 50116.1.3 Writing to Files 50416.1.4 Files Declared in Subprograms 50716.1.5 Explicit Open and Close Operations 50916.1.6 File Parameters in Subprograms 51216.1.7 Portability of Files 514

16.2 The Package Textio 51416.2.1 Textio Read Operations 51816.2.2 Textio Write Operations 52316.2.3 Reading and Writing Other Types 527

Standard Package Read and Write Operations 528Exercises 530

17 Case Study: A Package for Memories 53517.1 The Memories Package 53517.2 Using the Memories Package 546

17.2.1 Common Address and Data Conversions 551Exercises 558

18 Test Bench and Verification Features 55918.1 External Names 55918.2 Force and Release Assignments 57018.3 Embedded PSL in VHDL 575Exercises 582

19 Shared Variables and Protected Types 58519.1 Shared Variables and Mutual Exclusion 58519.2 Uninstantiated Methods in Protected Types 597Exercises 601

20 Attributes and Groups 60320.1 Predefined Attributes 603

20.1.1 Attributes of Scalar Types 603

Contents xiii

20.1.2 Attributes of Array Types and Objects 60420.1.3 Attributes Giving Types 60520.1.4 Attributes of Signals 60620.1.5 Attributes of Named Items 607

20.2 User-Defined Attributes 61620.2.1 Attribute Declarations 61620.2.2 Attribute Specifications 616

20.3 Groups 628Exercises 630

21 Design for Synthesis 63321.1 Synthesizable Subsets 63321.2 Use of Data Types 634

21.2.1 Scalar Types 63521.2.2 Composite and Other Types 636

21.3 Interpretation of Standard Logic Values 63721.4 Modeling Combinational Logic 63821.5 Modeling Sequential Logic 641

21.5.1 Modeling Edge-Triggered Logic 64221.5.2 Level-Sensitive Logic and Inferring Storage 65021.5.3 Modeling State Machines 652

21.6 Modeling Memories 65421.7 Synthesis Attributes 65821.8 Metacomments 666Exercises 667

22 Case Study: System Design Using the Gumnut Core 66922.1 Overview of the Gumnut 669

22.1.1 Instruction Set Architecture 66922.1.2 External Interface 674

The Gumnut Entity Declaration 676Instruction and Data Memories 677

22.2 A Behavioral Model 68122.2.1 The Gumnut Definitions Package 68122.2.2 The Gumnut Behavioral Architecture Body 687

Overview of the Interpreter 690Resetting the Interpreter 691Acknowledging an Interrupt 691Fetching an Instruction 692Performing an Arithmetic/Logical Operation 693Performing a Shift Operation 694Performing a Memory-I/O Instruction 695Performing a Branch Instruction 697Performing a Jump Instruction 697Performing a Miscellaneous Instruction 698

22.2.3 Verifying the Behavioral Model 69922.3 A Register-Transfer-Level Model 704

xiv Contents

22.3.1 The Architecture Body 70622.3.2 Verifying the RTL Model 720

22.4 A Digital Alarm Clock 72122.4.1 System Design 72222.4.2 Synthesizing and Implementing the Alarm Clock 729

Exercises 731

23 Miscellaneous Topics 73323.1 Guards and Blocks 733

23.1.1 Guarded Signals and Disconnection 733The Driving Attribute 737Guarded Ports 738Guarded Signal Parameters 739

23.1.2 Blocks and Guarded Signal Assignment 739Explicit Guard Signals 742Disconnection Specifications 743

23.1.3 Using Blocks for Structural Modularity 744External Names and Blocks 747Generics and Ports in Blocks 748Configuring Designs with Blocks 748

23.2 IP Encryption 75023.2.1 Key Exchange 769

23.3 VHDL Procedural Interface (VHPI) 77023.3.1 Direct Binding 77123.3.2 Tabular Registration and Indirect Binding 77323.3.3 Registration of Applications and Libraries 775

23.4 Postponed Processes 77623.5 Conversion Functions in Association Lists 77923.6 Linkage Ports 785Exercises 786

A Standard Packages 793A.1 The Predefined Package standard 793A.2 The Predefined Package env 797A.3 The Predefined Package textio 797A.4 Standard VHDL Mathematical Packages 799

A.4.1 The math_real Package 799A.4.2 The math_complex Package 801

A.5 The std_logic_1164 Multivalue Logic System Package 802A.6 Standard Integer Numeric Packages 806

A.6.1 The numeric_bit Package 806A.6.2 The numeric_std Package 812A.6.3 The numeric_bit_unsigned Package 813A.6.4 The numeric_std_unsigned Package 815

A.7 Standard Fixed-Point Packages 816A.7.1 The fixed_float_types Package 816A.7.2 The fixed_generic_pkg Package 816

Contents xv

A.7.3 The fixed_pkg Package 829A.8 Standard Floating-Point Packages 829

A.8.1 The float_generic_pkg Package 829A.8.2 The float_pkg Package 840

B VHDL Syntax 841B.1 Design File 843B.2 Library Unit Declarations 843B.3 Declarations and Specifications 845B.4 Type Definitions 848B.5 Concurrent Statements 850B.6 Sequential Statements 852B.7 Interfaces and Associations 855B.8 Expressions and Names 856

C Answers to Exercises 859

References 889

Index 891

xvii

Preface

VHDL is a language for describing digital electronic systems. It arose out of the UnitedStates government’s Very High Speed Integrated Circuits (VHSIC) program. In the courseof this program, it became clear that there was a need for a standard language for describ-ing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware De-scription Language (VHDL) was developed. It was subsequently developed further underthe auspices of the Institute of Electrical and Electronic Engineers (IEEE) and adopted inthe form of the IEEE Standard 1076, Standard VHDL Language Reference Manual, in 1987.This first standard version of the language is often referred to as VHDL-87.

Like all IEEE standards, the VHDL standard is subject to review from time to time.Comments and suggestions from users of the 1987 standard were analyzed by the IEEEworking group responsible for VHDL, and in 1992 a revised version of the standard wasproposed. This was eventually adopted in 1993, giving us VHDL-93. A second round ofrevision of the standard was started in 1998. That process was completed in 2001, givingus VHDL-2002. After that, further development took place in the IEEE working group andin a technical committee of an organization, Accellera, whose charter is to promote stan-dards for electronics design. These efforts led to the current version of the language,VHDL-2008, described in this book.

VHDL is designed to fill a number of needs in the design process. First, it allows de-scription of the structure of a system, that is, how it is decomposed into subsystems andhow those subsystems are interconnected. Second, it allows the specification of the func-tion of a system using familiar programming language forms. Third, as a result, it allowsthe design of a system to be simulated before being manufactured, so that designers canquickly compare alternatives and test for correctness without the delay and expense ofhardware prototyping. Fourth, it allows the detailed structure of a design to be synthesizedfrom a more abstract specification, allowing designers to concentrate on more strategicdesign decisions and reducing time to market.

This book presents a structured guide to the modeling facilities offered by the VHDLlanguage, showing how they can be used for the design of digital systems. The book doesnot purport to teach digital design, since that topic is large enough by itself to warrantseveral textbooks covering its various aspects. Instead, the book assumes that the readerhas at least a basic grasp of digital design concepts, such as might be gained from a firstcourse in digital design in an engineering degree program. Some exposure to computerprogramming and to concepts of computer organization will also be beneficial. This bookis suitable for use in a course in digital or computer design and will also serve practicingengineers who need to acquire VHDL fluency as part of their changing job requirements.

One pervasive theme running through the presentation in this book is that modelinga system using a hardware description language is essentially a software design exercise.This implies that good software engineering practice should be applied. Hence the treat-ment in this book draws directly from experience in software engineering. There are nu-

xviii Preface

merous hints and techniques from small-scale and large-scale software engineeringpresented throughout the book, with the sincere intention that they might be of use toreaders.

I am particularly pleased to be able to include this book in the Morgan Kaufmann Se-ries in Systems on Silicon. Modeling for simulation and synthesis is a vital part of a designmethodology for large-scale systems. VHDL allows models to be expressed at a range oflevels of abstraction, from gate-level up to algorithmic and architectural levels. It will con-tinue to play an important role in the design of silicon-based systems for some time tocome.

Structure of the Book

The Designer’s Guide to VHDL is organized so that it can be read linearly from front toback. This path offers a graduated development, with each chapter building on ideas in-troduced in the preceding chapters. Each chapter introduces a number of related conceptsor language facilities and illustrates each one with examples. Scattered throughout thebook are three case studies, which bring together preceding material in the form of ex-tended worked examples.

Chapter 1 introduces the idea of a hardware description language and outlines thereasons for its use and the benefits that ensue. It then proceeds to introduce the basic con-cepts underlying VHDL, so that they can serve as a basis for examples in subsequent chap-ters. The next three chapters cover the aspects of VHDL that are most like conventionalprogramming languages. These may be used to describe the behavior of a system in algo-rithmic terms. Chapter 2 explains the basic type system of the language and introducesthe scalar data types. Chapter 3 describes the sequential control structures, and Chapter 4covers composite data structures used to represent collections of data elements. In Chapter5, the main facilities of VHDL used for modeling hardware are covered in detail. Theseinclude facilities for modeling the basic behavioral elements in a design, the signals thatinterconnect them and the hierarchical structure of the design.

The next group of chapters extends this basic set of facilities with language featuresthat make modeling of large systems more tractable. Chapter 6 introduces procedures andfunctions, which can be used to encapsulate behavioral aspects of a design. Chapter 7 in-troduces the package as a means of collecting together related parts of a design or of cre-ating modules that can be reused in a number of designs. Chapter 8 deals with theimportant topic of resolved signals, and Chapter 9 describes a number of predefined andstandard packages for use in VHDL designs. The combination of facilities described inthese early chapters is sufficient for many modeling tasks, so Chapter 10 brings them to-gether in the first case study, in which a multiplier/accumulator circuit is designed.

The third group of chapters covers advanced modeling features in VHDL. Chapter 11covers aliases as a way of managing the large number of names that arise in a large model.Chapter 12 describes generics as a means of parameterizing the behavior and structure ofa design and enhancing the resusability of designs. This leads to a discussion of abstractdata types as a means of managing the complexity associated with large designs. Chapter13 deals with the topics of component instantiation and configuration. These features areimportant in large real-world models, but they can be difficult to understand. Hence thisbook introduces structural modeling through the mechanism of direct instantiation in ear-

Preface xix

lier chapters and leaves the more general case of component instantiation and configura-tion until this later chapter. In Chapter 14, generated regular structures are covered.

The fourth group of chapters covers language facilities generally used for system-levelmodeling. Chapter 15 introduces the notion of access types (or pointers) and uses themto develop linked data structures. The topic of abstract data types is revisited in the contextof container data types. Chapter 16 covers the language facilities for input and output us-ing files, including binary files and text files. Chapter 17 is a case study in which a packagefor designing memories is developed. The package draws upon features described in thethird and fourth groups of chapters.

In the fifth group of chapters, we introduce language features for advanced designand verification. Chapter 18 deals with features for test bench support and verification. Itdescribes how specifications written in the IEEE standard Property Specification Language(PSL) can be embedded in VHDL models. Chapter 19 covers protected types and their useas a means of concurrency control. Chapter 20 describes how we can annotate items in adesign with attributes to specify information to be used by design automation tools. Thisleads into Chapter 21, which covers guidelines for writing synthesizable models. Thisgroup of chapters is drawn together in a further case study, Chapter 22, showing devel-opment of a synthesizable processor core and its use in a small embedded system, a digitalalarm clock.

The final chapter, Chapter 23, is a miscellany of advanced topics not covered in theprevious chapters. It includes a discussion of blocks and guarded signals, which are notas widely used in modern designs as previously. Nonetheless, we describe them here forcompleteness. The chapter also covers use of features for encrypting the source text ofmodels as a means of protecting intellectual property (IP), and use of features of the VHDLProcedureall Interface (VHPI) for incorporating models and applications written in non-VHDL programming languages.

Each chapter in the book is followed by a set of exercises designed to help the readerdevelop understanding of the material. Where an exercise relates to a particular topic de-scribed in the chapter, the section number is included in square brackets. An approximate“difficulty” rating is also provided, expressed using the following symbols:

➊ quiz-style exercise, testing basic understanding

➋ basic modeling exercise—10 minutes to half an hour effort

➌ advanced modeling exercise—one half to two hours effort

➍ modeling project—half a day or more effort

Answers for the first category of exercises are provided in Appendix C. The remainingcategories involve developing VHDL models. Readers are encouraged to test correctnessof their models by running them on a VHDL simulator. This is a much more effective learn-ing exercise than comparing paper models with paper solutions.

Changes in the Second and Third Editions

The first edition of this book was published in 1995, just as VHDL-93 was gaining accep-tance. The second edition was updated to reflect the changes in VHDL-2002. Many of the

xx Preface

changes in the language standard corrected ambiguities in the previous standard thatcaused incompatibility between VHDL tools from different vendors. There were alsochanges that enhanced the usability of the language. The text and examples in the secondedition were revised where necessary to reflect the changes in the language. Furthermore,following publication of the first edition, a number of VHDL-related standards were pub-lished and gained widespread acceptance. The second edition added descriptions of theIEEE 1076.3 synthesis and IEEE 1076.2 math packages, and was revised to cover the IEEE1076.6 Synthesis Interoperability Standard.

The latest revision of the language, VHDL-2008, adds a number of significant new lan-guage features, making this edition of The Designer’s Guide to VHDL significantly biggerthan its predecessors. VHDL-2008 also specifies numerous minor new features andchanges to existing features to enhance the usability of the language. This edition inte-grates descriptions of all of the new and revised features into the text. The differencesbetween the various versions are highlighted in call-outs within the text, headed with“VHDL-2002,” “VHDL-93,” or “VHDL-87,” as appropriate. In addition, some of the materialhas been removed or rearranged. The case study on a package for arithmetic on bit-vectoroperands has been deleted because the standard numeric packages have now becomewidespread. The first case study in this book is a revised version of the MAC case studyin previous editions, and shows how the standard packages can be used. The chapter onblocks and guarded signals has been contracted and moved to a section in the last chapter,since the features are now little used in practice. There is a greater emphasis on synthesisin this edition. What was an appendix on the topic in previous editions has been substan-tially revised and promoted to full chapter status. The large case study showing develop-ment of a 32-bit processor model has been revised to show a smaller synthesizable modelof an 8-bit microcontroller core and its use in an embedded system. This is much morerelevant, both for educational purposes and professional practice. Finally, this edition in-cludes a listing of all of the VHDL standard packages as an appendix for reference.

Resources for Help and Information

Although this book attempts to be comprehensive in its coverage of VHDL, there will nodoubt be questions that it does not answer. For these, the reader will need to seek otherresources. A valuable source of experience and advice, often overlooked, is one’s col-leagues, either at the workplace or in user groups. User groups generally hold regularmeetings that either formally or informally include a time for questions and answers. Manyalso run e-mail lists and on-line discussion groups for problem solving.

Accellera is one of a number of organizations that sponsors the EDA Industry WorkingGroups Web server (www.eda.org). The server has links to Web pages and repositories ofseveral VHDL standards groups and user groups.

Readers who have access to the Usenet electronic news network will find the newsgroup comp.lang.vhdl a valuable resource. This discussion group is a source of announce-ments, sample models, questions and answers and useful software. Participants includeVHDL users and people actively involved in the language standard working group and inVHDL tool development. The “frequently asked questions” (FAQ) file for this group is amine of useful pointers to books, products and other information. It is archived atwww.eda.org.

Preface xxi

One resource that must be mentioned is IEEE Standard 1076, IEEE Standard VHDLLanguage Reference Manual, sometimes referred to as the “VHDL Bible.” It is the author-itative source of information about VHDL. However, since it is a definitional document,not a tutorial, it is written in a complex legalistic style. This makes it very difficult to useto answer the usual questions that arise when writing VHDL models. It should only beused once you are somewhat familiar with VHDL. It can be ordered from the IEEE atstandards.ieee.org.

This book contains numerous examples of VHDL models that may also serve as a re-source for resolving questions. The VHDL source code for these examples and the casestudies, as well as other related information, is available on the companion website for thebook at books.elsevier.com/companions/9780120887859.

Although I have been careful to avoid errors in the example code, there are no doubtsome that I have missed. I would be pleased to hear about them, so that I can correct themin the on-line code and in future printings of this book. Errata and general comments canbe e-mailed to me at vhdl-book@ashenden.com.au.

Acknowledgments

The seeds for this book go back to 1990 when I developed a brief set of notes, The VHDLCookbook, for my computer architecture class at the University of Adelaide. At the time,there were few books on VHDL available, so I made my booklet available for on-line ac-cess. News of its availability spread quickly around the world, and within days, my e-mailin-box was bursting. At the time of writing this, nearly 20 years later, I still regularly receivemessages about the Cookbook. Many of the respondents urged me to write a full textbookversion. With that encouragement, I embarked upon the exercise that led to the first edi-tion of The Designer’s Guide to VHDL. Two years after publication of The Designer’s Guide,the need for a book specifically for students became evident. That led to publication ofthe first edition of The Student’s Guide to VHDL. I am grateful to the many engineers, stu-dents and teachers around the world who gave me the impetus to write these books andwho made them such a success. I hope this new edition will continue to meet the needfor a comprehensive guide to VHDL.

In the previous editions of The Designer’s Guide and The Student’s Guide, I had theopportunity to extend thanks to the many people who assisted in development of thebooks. They included my colleagues at the University of Adelaide; my research collabo-rators, Phil Wilsey at the University of Cincinnati and Perry Alexander at the University ofKansas; the staff at Morgan Kaufmann Publishers, including, in particular, Denise Penrose;the reviewers of the manuscript for the first edition, namely, Poras Balsara of the Univer-sity of Texas, Paul Menchini of Menchini & Associates, David Pitts of GTE Labs and theUniversity of Lowell and Philip Wilsey of the University of Cincinnati; David Bishop forhis contribution to the material on synthesis in the first edition of The Designer’s Guide;and Mentor Graphics Corporation, for use of their ModelSim simulator to check the exam-ple models. I remain grateful to all of these people and organizations for their valuablecontributions to the earlier editions and to this edition.

For the current edition, I would also like to thank Jim Lewis, who collaborated on arecent book, VHDL-2008: Just the New Stuff. Much of the material from that book hasfound its way into this book in one form or another. Thanks also to Mentor Graphics Cor-

xxii Preface

poration for continued use of the ModelSim simulator to check the example code. I con-tinue to enjoy an excellent working relationship with the staff at Morgan KaufmannPublishers and their parent company, Elsevier. Thanks to Chuck Glaser, Senior Acquisi-tions Editor, for his support in the continued development of these VHDL books; to Dawn-marie Simpson, Senior Project Manager in the Production Department, for her meticulousattention to detail; and to Denise Penrose, Publisher, for her longstanding support of mywriting endeavors.

The previous editions of The Designer’s Guide to VHDL were dedicated to my wifeKatrina. As I said in the first edition preface, I used to think that authors dedicating theirbooks to their partners was somewhat contrived, but that Katrina’s understanding, encour-agement and support taught me otherwise. I remain deeply grateful for her continued sup-port and am honored to also dedicate this third edition to her.