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BI THO LUN S 3

THIT K S BNG NGN NG M TPHN CNG - VHDL

LP: IN T VIN THNG K2

NHM THO LUN S 5

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DANH SCH NHM :

NGUYN VN THC

NGUYN HNG LM

NGUYN VN QUYN

BI XUN ANH

BI DANH HONG PHM GIA TH

V NH VINH

O NH XUN

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MCH GII M 3-8

-- LED 7 THANH

library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_STD.all; entity led72 is Port ( I : in STD_LOGIC_VECTOR (3 downto 0);

Y : out std_logic_vector(6 downto 0)); end led72 ; architecture LOGIC of led72 is begin PROCESS (I)

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MCH GII M 3-8 BEGIN CASE I is

when "0001" => Y Y Y Y Y Y Y Y Y

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M PHNG CHNG TRNH

D:\TAI LIEU\VHDL\THUC

HANH\led72\led72.qpf D:\TAI LIEU\VHDL\THUC

HANH\led72\led72.vwf

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MCH GII M 3-8

-- MACH GIAI MA 3_8 DUNG LENH elsif"

library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; entity mahoa3_8 is port (A: in integer range 0 to 7); Y: out unsigned (7 downto 0)); end entity mahoa3_8; architecture LOGIC of mahoa3_8 is begin process (A)

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MCH GII M 3-8 begin if(A=0) then Y

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MCH GII M 3-8

-- MACH GIAI MA 3_8 DUNG LENH CASE "

library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; entity mahoa3_8 is port (A: in integer range 0 to 7); Y: out unsigned (7 downto 0)); end entity mahoa3_8; architecture LOGIC of mahoa3_8 is begin process (A)

begin

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MCH GII M 3-8 case A is

when 0 => Y Y Y Y Y Y Y Y

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MCH GII M 3-8 -- MACH GIAI MA 3_8 DUNG WITH A SELECT library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; entity mahoa3_8 is port (A: in integer range 0 to 7); Y: out unsigned (7 downto 0));

end entity mahoa3_8; architecture LOGIC of mahoa3_8 is begin process (A) begin

with A select

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MCH GII M 3-8 Y

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MCH GII M 3-8

-- MACH GIAI MA 3_8 DUNG FOR

library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; entity mahoa3_8 is port (A: in integer range 0 to 7);

Y: out unsigned (7 downto 0)); end entity mahoa3_8; architecture LOGIC of mahoa3_8 is begin

process (A)

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MCH GII M 3-8

-- MACH GIAI MA 3_8 DUNG if

library IEEE; use IEEE.STD_LOGIC_1164.all,IEEE.Numeric_std.all; entity mahoa3_8 is port (A: in integer range 0 to 7);

Y: out unsigned (7 downto 0)); end entity mahoa3_8; architecture LOGIC of mahoa3_8 is begin

process (A)

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CHNG TRNH CON

-- CAC CHUONG TRINH CON DINH NGHIA ; --TREN TAP TIN HE THONG RIENG BIET ;

Library IEEE; use Library

IEEE.STD_LOGIC_1164.all,IEEE.Numeric_STD.all; package COLOR_TYPES is type pigmentcolorprime is ( red,yellow,Blue ); type pigmentcolorsec is ( Orange, violet,green); end package COLOR_TYPES ;

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CHNG TRNH CON use work.COLOR_TYPES.all; package SUBPROGS is

procedure Mixcolor ( signal C1,C2: in pigmentcolorPrime; signal Mix : out pigmentcolorPrime); function Mixcolor (C1,C2: pigmentPrime);

return pigmentseccolor; end package SUBPROGS; package body SUBPROGS is procedure Mixcolor ( signal C1,C2: in pigmentcolorPrime;

signal Mix : out pigmentcolorsec) is

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CHNG TRNH CON begin if ( C1= red and C2= yellow ) then

Mix

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CHNG TRNH CON begin if(C1=red and C2=yellow) then Mix:=violet; else (C1= yellow and C2=Blue ) then Mix:= Green;

end if ; return Mix; end functon Mixcolor; end package body SUBPROGS;