Theses 8 : Alejandro Nieto Gutiérrez

Alejandro Nieto Gutiérrez

Hardware design of demand as frequency controlled

reserve

Master’s Thesis, January 2008

Hardware design of demand as frequency controlled r eserve

This report was drawn up by: Alejandro Nieto Gutiérrez Supervisor(s): Zhao Xu Tonny W. Rasmussen

Ørsted•DTU Centre for Electric Technology (CET) Technical University of Denmark Elektrovej Building 325 2800 Kgs. Lyngby Denmark www.oersted.dtu.dk/cet Tel: (+45) 45 25 35 00 Fax: (+45) 45 88 61 11 E-mail: [email protected]

Release date:

05-01-2008

Category:

1 (offentlig)

Edition:

1st edition

Comments:

This report is part of the requirements to achieve the Erasmus Final Thesis Project at the Technical University of Denmark. This report represents 35 ECTS points or at least 6 full-time months of dedication.

Rights:

© Alejandro Nieto Gutiérrez, 2008

i

HOME UNIVERSITY INFORMATION

Titulo: Hardware design of demand as frequency controlled reserve Prototipo de controlador de consumo de cargas según la frecuencia de la red

Autor: Alejandro Nieto Gutiérrez

Supervisores: Zhao Xu Tonny W. Rasmussen

Censor:

Nota:

Universidad: DTU, Lyngby. Departamento: Ørsted•DTU Duración, carga de trabajo: 35 ETCS. Six months full-time project Tipo: Master Thesis project, Proyecto Final de Carrera.

Fecha de inicio: 1 de Febrero de 2007

Fecha de finalizacion: 5 de Enero de 2008

Home University Information

ii

Resumen en Español: El proyecto consiste en el desarrollo de un medidor de frecuencia de la red

eléctrica desde cero. La red eléctrica ante desequilibrios de la producción y consumo de energía puede reaccionar de maneras indeseadas. El controlador desarrollado en este proyecto es capaz de medir los cambios en la frecuencia de la red eléctrica y a partir de los datos obtenidos reaccionar desconectado la carga y así disminuyendo el consumo eléctrico.

Las cargas propicias para estos propósitos son las cargas, y más específicamente, electrodomésticos, que pueden ser desconectados de la red eléctrica sin que sea apreciado por parte de los usuarios. Estos electrodomésticos pueden ser por ejemplo calentadores de agua eléctricos, frigoríficos o también bombas de calor o climatizadores. Según la carga a controlar cortes de unos segundos serán inapreciables por parte del usuario pero si por parte de la red eléctrica.

El uso generalizado de esta tecnología podrá reducir costes en el mantenimiento de centrales eléctricas de reserva, que en estos momentos, permanecen a la espera de que se produzca un exceso de consumo para así empezar su producción. El mantenimiento de estas centrales es caro y podrían ser aprovechadas para la producción regular de energía. Otra ventaja de este controlador puede ser su capacidad de reacción ante producciones de energía irregulares como pueden ser las fuentes de energía renovables. Estas fuentes de energía pueden mermar su producción sin dejar suficiente tiempo a la red para recuperarse, mediante el uso de esta tecnología, se podrá asumir gran parte de estas inestabilidades dejando un mayor margen de tiempo para la recuperación de la red.

En este documento se explica el proceso completo del desarrollo del controlador

de cargas según la frecuencia. Está contemplado desde los inicios del desarrollo, con la selección de componentes, hasta la programación del código fuente del micro controlador, pasando por el desarrollo y diseño del hardware adicional utilizado para completar los propósitos.

Palabras clave: Microcontroladores, medidor de frecuencia, programación C, DSP, DSC, Code

Composer Studio, filtro paso banda, fuente de alimentación, ADC, hardware, software, medidor de potencia RMS, Event Manager, Reserva eléctrica, equilibrio consumo-producción, Energías renovables, fuente de alimentación.

iii

ABSTRACT

This document is the final report for “Hardware design of demand as frequency controlled reserve” project, carried out by Alejandro Nieto Gutiérrez, Erasmus student from Spain.

The aim of this project is to develop a load controller, which is able to monitor the

frequency and power of the power grid, from the wall outlet, and react with frequency changes, as well as prepare for recording the acquired data for subsequent studies.

The energy Balance between consuming and producing units need to be

maintained continuously, or otherwise the system will became unstable ultimately resulting in a total system collapse. This project will react with the power grid imbalances according to the frequency measured at the wall outlet. If necessary it will disconnect the load reducing the consumption, which will help to avoid a power grid imbalance as well as recover the power grid balance within instability.

The introduction and the theoretical overview about concepts present in the

project process are included into the first chapter. The hardware part of the project, design and development is described in the

second chapter. Software development process, in instance algorithms used and programming of

the application and other related matters, is explained in the third chapter. The last chapters are the future work chapter, which describes a recommended

way to follow the development of the load controller project, the conclusions chapter, which gathers all the conclusions obtained once this load controller prototype is finish, the bibliography and finally the appendix, which contains all the additional information that is not included in neither of previous sections, like the tables of acquired data, as well as the full source code of application and the hardware schemes.

v

ACKNOWLEDGES

I specially want to acknowledge the invaluable help and understanding given by

my tutor and co-tutor, Zhao Xu and Tonny W. Rasmussen, without their help the accomplishment of this project would not be possible.

I want to thank Knud Ole Helgesen Pedersen for the help given and also for teaching me the working of microcontrollers in the January 2007 course.

I also want to thank everybody in DTU University and in Denmark in general, who made me feel like at home, in spite of being in other country.

Finally I want to thank to my family for their support and my home university for given me this opportunity.

vii

CONTENTS

1 Introduction ..................................................................................................... 1 1.1. The Power grid.......................................................................................... 1

1.2. How the power grid can be helped ........................................................... 2

1.3. The aim and objectives of the project ....................................................... 3

1.4. Block Diagram of Load Controller ........................................................... 4

1.5. Frequency measurement overview ........................................................... 5

1.6. Frequency decay measurement overview ................................................. 5

1.7. RMS Current, voltage and power measurement overview ....................... 6

2 Algorithms, procedures and results. ............................................................. 9

2.1. Frequency measurement algorithm ........................................................... 9

2.1.1. Averaging measures ........................................................................ 16

2.1.2. Maximum theoretical Accuracy ...................................................... 18

2.1.3. Soft frequency filter ........................................................................ 21

2.1.4. Frequency sensor range .................................................................. 22

2.1.5. Accuracy ......................................................................................... 23

2.2. Frequency decay measurement ............................................................... 24

2.3. Control logic Type I: Frequency Thresholds .......................................... 26

2.4. Control logic Type II: Temperature Set points change ........................... 30

2.5. Voltage, current and Power measurement .............................................. 31

2.5.1. Sample acquisition .......................................................................... 31

2.5.2. Acquired measures .......................................................................... 32

2.5.3. RMS Current, voltage and power calculation ................................. 36

2.6. Real-time stamp ...................................................................................... 42

3 Hardware ....................................................................................................... 45 3.1. DSC ......................................................................................................... 45

3.1.1. DSC prerequisites ........................................................................... 46

3.1.2. DSC Technical features .................................................................. 48

3.1.3. DSC Hardware Description ............................................................ 50

Contents

viii

3.1.3.1. C28x CPU .................................................................................. 50

3.1.3.2. Memory Bus (Harvard Bus Architecture) .................................. 50

3.1.3.3. Real-Time JTAG and Analysis .................................................. 51

3.1.3.4. SARAMs .................................................................................... 51

3.1.3.5. Flash ........................................................................................... 53

3.1.3.6. Security....................................................................................... 53

3.1.3.7. Peripheral Interrupt Expansion (PIE) Block .............................. 54

3.1.3.8. Oscillator and PLL ..................................................................... 54

3.1.4. DSC Periphery Description ............................................................. 55

3.1.4.1. Event Manager ........................................................................... 55

3.1.4.1.1. GP timers ............................................................................. 57

3.1.4.1.2. Capture unit ......................................................................... 57

3.1.4.1.3. Starting the A/D Converter with a Timer Event ................. 58

3.1.4.2. ADC ........................................................................................... 58

3.1.4.3. General purpose I/O ................................................................... 61

3.2. Board Description.................................................................................... 62

3.2.1. Signal interfacing and conditioning ................................................ 63

3.2.1.1. Measurement transformers ......................................................... 63

3.2.1.2. Analog filters .............................................................................. 64

3.2.1.3. Level shifter................................................................................ 66

3.2.2. Current and voltage values at load controller inputs ....................... 69

3.2.3. Power Supply .................................................................................. 71

3.2.4. eZDSP F2812 .................................................................................. 73

4 Software .......................................................................................................... 75 4.1. IDE .......................................................................................................... 75 4.2. User Manual ............................................................................................ 76

4.2.1. Developing board connection .......................................................... 77

4.2.2. The project ....................................................................................... 78

4.2.3. Configurations ................................................................................. 81

4.2.4. Modify, build and load a project ..................................................... 82

4.2.5. Debug project .................................................................................. 85

4.2.6. Gel File ............................................................................................ 86

Contents

ix

4.3. The load controller program ................................................................... 88

4.3.1. File structure ................................................................................... 88

4.3.2. Memory mapping ............................................................................ 89

4.3.3. Program structure ............................................................................ 92

4.3.3.1. Headers ...................................................................................... 93

4.3.3.1.1. Inclusions ............................................................................ 93

4.3.3.1.2. Constant definition and Location of attributes ................... 93

4.3.3.1.3. Functions definition ............................................................ 96

4.3.3.1.4. Variables definition ............................................................ 98

4.3.3.2. Device initialization ................................................................... 99

4.3.3.2.1. System Control Initialization ............................................ 100

4.3.3.2.2. Peripheral High speed clock configuration....................... 100

4.3.3.2.3. GPIO configuration .......................................................... 101

4.3.3.2.4. PIE initialization ............................................................... 101

4.3.3.2.5. ADC initialization ............................................................. 102

4.3.3.2.6. EV configuration, timers and capture unit ........................ 104

4.3.3.2.7. Relay initialization ............................................................ 105

4.3.3.2.8. Enable CPU interruptions ................................................. 105

4.3.3.2.9. Average frequency buffer initialization ............................ 106

4.3.4. Capture unit subroutine: Capture1_srt() ....................................... 107

4.3.5. ADC interruption subroutine: ADC_srt() ..................................... 112

4.3.6. Other subroutines .......................................................................... 114

5 functionalities and performance ................................................................ 117

6 Future work ................................................................................................. 119 6.1. Flash memory ....................................................................................... 119

6.2. Communication part ............................................................................. 119

6.3. Persistent storage .................................................................................. 120

7 Conclusions .................................................................................................. 121

8 Bibliography ................................................................................................ 123

A Source code .............................................................................................. 125 A.1 Main program source code ................................................................... 125

A.2 Memory mapping .................................................................................. 139

Contents

x

B Board Schemes ......................................................................................... 140

C Other plots................................................................................................ 143

D Tables ........................................................................................................ 145 D.1 ADC Measurements .............................................................................. 145

D.2 Frequency measures .............................................................................. 148

D.3 Frequency decay .................................................................................... 156

xi

LIST OF FIGURES

Figure 1-I – Load controller Block diagram ..................................................................... 4

Figure 2-I - period of a signal ........................................................................................... 9

Figure 2-II - Schmitt-triggered output ............................................................................ 10

Figure 2-III - Frequency measurement block diagram ................................................... 11

Figure 2-IV - Overflow in frequency counting ............................................................... 12

Figure 2-V – Capture unit measurements ...................................................................... 14

Figure 2-VI - Instant Frequency measurements ............................................................. 15

Figure 2-VII - Error spread using average ...................................................................... 16

Figure 2-VIII - Averaged frequency measurements in integer values............................ 17

Figure 2-IX - Averaged frequency measurements in Hz ................................................ 17

Figure 2-X - Instant and averaged measurements .......................................................... 18

Figure 2-XI - frequency counting error .......................................................................... 19

Figure 2-XII - Software frequency filter block diagram ................................................. 22

Figure 2-XIII - Frequency decay .................................................................................... 24

Figure 2-XIV – Frequency decay ................................................................................... 26

Figure 2-XV – Averaged frequency measurements vs frequency thresholds ................ 27

Figure 2-XVI Frequency decay Vs Frequency decay threshold ..................................... 28

Figure 2-XVII- Threshold checking flow diagram ......................................................... 29

Figure 2-XVIII - ADC curret measures .......................................................................... 32

Figure 2-XIX - ADC Voltage measures ......................................................................... 33

Figure 2-XX - Integer measures of current without offset ............................................. 33

Figure 2-XXI - Integer measures of voltage without offset ............................................ 34

Figure 2-XXII - Measured Current ................................................................................. 34

Figure 2-XXIII - Measured Voltage ............................................................................... 35

Figure 2-XXIV - Instant power in integer units ............................................................. 35

Figure 2-XXV - Calculated instant Power ...................................................................... 36

List of Figures

xii

Figure 2-XXVI - Measured RMS current (int) ............................................................... 37

Figure 2-XXVII - Measured RMS Voltage (int) ............................................................. 38

Figure 2-XXVIII - Measured RMS power (int) .............................................................. 38

Figure 2-XXIX - Measured RMS current (A) ................................................................. 40

Figure 2-XXX - Measured RMS Voltage (V) ................................................................. 41

Figure 2-XXXI - Measured RMS power (W) ................................................................ 41

Figure 3-I - Texas instruments Logo ............................................................................... 49

Figure 3-II - DSC Memory map ...................................................................................... 52

Figure 3-III - Event Manager A Functional Block Diagram ........................................... 56

Figure 3-IV - ADC block diagram .................................................................................. 59

Figure 3-V – ADC example Voltage output ................................................................... 60

Figure 3-VI - Board distribution ..................................................................................... 62

Figure 3-VII - Measuring Transformers .......................................................................... 63

Figure 3-VIII - Filter transfer function ............................................................................ 65

Figure 3-IX – Filter photo ............................................................................................... 65

Figure 3-X- Filter Scheme ............................................................................................... 66

Figure 3-XI - Voltage level Shifter Scheme .................................................................... 67

Figure 3-XII - Current Level Shifter Scheme ................................................................. 68

Figure 3-XIII - Level shifter result .................................................................................. 69

Figure 3-XIV - Single power supply scheme .................................................................. 71

Figure 3-XV - Measure at the bridge output, point C (Without capacitors) ................... 72

Figure 3-XVI – Power supply output .............................................................................. 72

Figure 3-XVII - Double Power Supply scheme .............................................................. 73

Figure 3-XVIII - eZdsp F2812 photo .............................................................................. 74

Figure 4-I - Code Composer Studio main window ......................................................... 76

Figure 4-II – Connect ...................................................................................................... 77

Figure 4-III - Board connected message ......................................................................... 77

Figure 4-IV - Open existing project ................................................................................ 78

Figure 4-V - Open Project dialog .................................................................................... 79

Figure 4-VI - Opened project .......................................................................................... 79

Figure 4-VII - Main file source Code .............................................................................. 80

Figure 4-VIII - Linker configuration ............................................................................... 81

Figure 4-IX – Select Configurationt ................................................................................ 81

Contents

xiii

Figure 4-X - Build a project ............................................................................................ 82

Figure 4-XI - Build report ............................................................................................... 82

Figure 4-XII - Load Program .......................................................................................... 83

Figure 4-XIII - Load project output ................................................................................ 83

Figure 4-XIV - Reload Project........................................................................................ 84

Figure 4-XVRun a program ............................................................................................ 84

Figure 4-XVI - watch window ........................................................................................ 85

Figure 4-XVII - Break point ........................................................................................... 86

Figure 4-XVIII - GEL file .............................................................................................. 86

Figure 4-XIX - GEL Menu ............................................................................................. 87

Figure 4-XX - Example code of GEL language ............................................................. 87

Figure 4-XXI - Simplified program flow ....................................................................... 92

Figure 8-I - Board Scheme............................................................................................ 141

Figure 8-II - DSC connectors Detail ............................................................................. 142

Figure 8-III – Averaged frequency measurements (Integer units) ............................... 143

Figure 8-IV – Averaged frequency measurements (Hz) ............................................... 144

xv

LIST OF TABLES

Table 7-I – ADC samples table..................................................................................... 145

Table 7-II - Instant frequency measurements ............................................................... 148

Table 7-III - Averaged frequency measurements ......................................................... 149

Table 7-IV - RMS measurements ................................................................................. 154

Table 7-V - Frequency decay........................................................................................ 156

xvii

LIST OF SYMBOLS

Symbol Unit Definition

Integer Output integer value of ADC

Integer First averaged measure in a pair of period measurements

Integer Second averaged measure in a pair of period measurements

Hz Frequency of capture unit counter

Hz/s Frequency decay

N/A Factor that converts integer current measurements in S.I units

N/A Factor that converts integer power measurements in S.I units

Hz Frequency at power grid

N/A Factor that converts integer measurements in S.I units

V/V Total current gain in current channel

V/V Current gain in current level shifter

V/V Current gain in current transformer

V/V Total voltage gain in voltage channel

V/V Voltage gain in voltage level shifter

V/V Voltage gain in voltage transformer

A Current consumed by the load

A Current present at ADC input

_ ! Integer RMS Current in integer units at ADC

N N/A Number of event manager cycles within a power grid cycle or number of ADC measures used in RMS calculations

"#$% Integer Integer value of offset sensed by ADC

& ! W Power grid power in RMS

&_ ! Integer RMS power in integer units at ADC

' Ω Resistance of ADC current resistor

List of Symbols

xviii

Symbol Unit Definition

% S First period value in a pair of period measurements

% S Second period value in a pair of period measurements

% Integer Period measured by capture unit

( S Time of a time base count unit

% S Period at power grid

) V Voltage at load controller input

) V Voltage value sensed by ADC in Volts

) ! V Power grid Voltage in RMS

)_ ! Integer RMS voltage in integer units at ADC

∆ Hz Increment of frequency in two following frequency measures

∆( S Increment of time in two following frequency measures

∆% S Relative period error in frequency measurements

xix

ACRONYMS

#

µC Microcontroller

A

ADC Analog to Digital Converter

C

CPU Central Processing Unit

CSM Code Security Module

CUPS Capture Unit input clock PreScaler

D

dB Decibel

DC Direct Current

DSC Digital Signal Controller

DSP Digital Signal Processor

E

EV EVent manager

EVA EVent manager A

EVB EVent manager B

F

FCF Frequency Conversion Factor

G

GP General Purpose

GPIO General Purpose Input/Output

Acronyms

xx

I

IDE Integrated Development Environment

J

JTAG Joint Test Action Group

M

MAC Multiplication And aCcumulation

P

PC Personal Computer

PIE Peripheral Interrupt Expansion

PLL Phase Locked Loop

R

RAM Random Access Memory

RMS Root Mean Square

ROM Read Only Memory

S

SI Le Système International d'unités (International System of units)

SRAM Single-access Random Access Memory

U

UART Universal Asynchronous Receiver-Transmitter

1

1 INTRODUCTION

1.1. The Power grid Electrical systems in the form of power grids are one of the most efficient ways of

transferring energy over large distances directly to the consumers, hereby limiting the need for production of energy in the closeness of consumers.

Electrical power in the quantities that modern countries consume cannot be stored

in any currently available storage solution, and can therefore not be used as a solution to preserve the power grid.

The energy Balance between consuming and producing units need to be

maintained continuously, or otherwise the system will became unstable ultimately resulting in a total system collapse.

The responsibility of maintaining the system balance is placed with the system

operators. These operators have to monitor the power system continuously and the most effective way of doing so, is to measure the frequency.

When the production and consumption of active electrical power is in balance the

frequency will be 50Hz. The reason being, that electrical energy taken out of the system matches the mechanical power grid into the system, in fact in this state the rotational speed of generators will remain fixed.

As the system starts to lose synchronization, the rotations speed of the

synchronous generators will begin to change, which make us know that the balance is beginning to degrade by changing the frequency of the grid.

In instance of frequency rise, it indicates that the production starts to exceed the

consumption. The generators will begin to rotate faster because of the excess energy delivered from the mechanical side of the generation unit. If the frequency drops below 50Hz then the consumption exceeds the production.

Introduction

2

The electrical systems are thought up to solve this last problem by activating the reserve systems that will inject or consume energy until the consumption-generation balance is recover.

1.2. How the power grid can be helped As explained in previous section when the consumption exceeds the production

the frequency starts to drop. Although the electrical system is able to solve this problem it is possible to help to solve it from the consumer side, reducing the need of reserve systems. By doing so, many benefits can be achieved, low costs, the possibility to use the reserve system as primary production and also energy savings while de loads are disconnected.

Most importantly, it is to facilitate increased integration of fluctuating renewable

energy, in example wind generators, into the power system in the future. The renewable energy sources have an unstable production. Therefore an unexpected drop of power production in this kind of sources can also cause the excess of consumption. The easier possibility to introduce renewable energy sources can reduce the contaminant emissions can be reduced.

The consumers have at home several loads that can be switched on and off

without noticing it, these loads are named FCLs. A control device that can be able to sense the power grid status and under

frequency changes could react will help to preserve the power grid integrity, for example by switching off this FCLs in an excess of consumption, or increasing the thermostat temperature in the particular cases of a fridge or decreasing it in a water heater.

Introduction

3

1.3. The aim and objectives of the project The objective of this project is to provide a fast-responding control device that

reacts in response to frequency events. It also has to be able to measure the Root Mean Square (RMS) power, voltage and current.

The controller must sense the local grid frequency at the wall outlet and de-energize the load, based in two control logics.

The load will be tripped if the frequency goes below a specified threshold, or if

the rate of frequency decay is lower than a user specified threshold for the logic Type I.

Tripping criteria: Maximum delay 0,5s (in can be reduced by compromising the frequency accuracy) C1: Low frequency criteria: <49.90 Hz and C2: Fast frequency decay criteria <-0.13 Hz/sec Reconnection criteria: R1: Tripped by C1, frequency recovers to a margin above tripping set point (49.98 Hz) and C2 not met R2: Tripped by C2, C2 not met and after a time delay R3: Both subject to a random time lag 0~30 Secs It is possible to change the values of C1, C2, R1, and R3

The control logic type II is specially designed for those thermostically controlled

loads with cyclic on/off durations. In this type, instead of tripping the loads according to the frequency directly, their temperature set points are dynamically controlled according to the frequency

For type II, the set points of the appliance (fridge or air-con) can be

)(*

)(*

0

0

ffkfTT

ffkfTTnormal

lowlow

normalhighhigh

−−=

−−=

(1.1)

This control logic is not completely development in this load controller prototype

due to the miss of the interface that can change the thermostat temperature of a FLC of this type.

From this point a frequency event is understood as the frequency change that

fulfills any of the control logics described above.

Introduction

4

The load is re-energized after the recovery criteria fulfill, utilizing a random

waiting period between a selectable amount of time (30 seconds as default) providing a smooth transition for the grid. The random time lag prevents all loads from turning back on all at the very same time after a frequency event, which could cause a rebound effect, potentially tripping other overload relays on transmission or generation equipment

1.4. Block Diagram of Load Controller

Figure 1-I – Load controller Block diagram

The block diagram above, (Figure 1-I – Load controller Block diagram), describes the basic operation of the control device. The load represents the controlled device such as a fridge, a water heater or any other FCL appliance.

The relay represents can energize or de-energize the device according to control

logics, in the case that the power grid is under a frequency event. It can also be a control module able to change the thermostat temperature or any other action that can reduce the consumption of the controlled load.

The voltage divider or voltage transformer reduces the voltage of the power grid

to a range that can be sensed by the Analog to Digital Converter (ADC) integrated on the Digital Signal Controller (DSC) chip.

Power

Outlet

Voltage

Divider

Transimpedance

amplifier

LOAD Relay

Voltage

channel

Current

channel

DSCAD

C&

EM

I/O

Introduction

5

The transimpedance transformer outputs a voltage proportional to the input current. It is also connected with the ADC input which allows measuring the current and consequently the power of consumed by the controller device. The transimpedance transformer is compound by a current transformer and a know resistor that drops a know amount of voltage according to the input current.

The output signal of both transformers is conditioned before being connected with

the ADC inputs; the conditioning hardware is included in the transformers blocks in order to simplify the diagram.

1.5. Frequency measurement overview The frequency measurement method used is the zero-crossing detection. This

method measures the time between zero-crossings, which is the period of the power grid signal. The frequency can be directly obtained madding use of the period, This algorithm is explained in section 0

This chapter describes the algorithms and methods used to develop the load controller. In this chapter it is also show the results obtained by the

Frequency measurement. The frequency measurement is used to implement the control logic Type I, which

is based on the frequency changes.

1.6. Frequency decay measurement overview The frequency decay measurement is realized using the frequency measurements

of consecutive cycles. It is calculated the decay between selectable amounts of pairs of measures in a row. Immediately after it, is calculated the average of these frequency decays and finally it is compared with the frequency decay threshold.

In the case that the threshold is surpassed, the control device proceeds to start the frequency event response.

More details about the algorithm used are covered in section 2.2 Frequency decay

measurement. This type of measurement is used to implements the control logic Type II, which is based on the frequency decay changes.

Introduction

6

1.7. RMS Current, voltage and power measurement overview

The instant voltage, current and power varies in the time from negative to positive

values. Current, voltage and power should be expressed in Root Mean Square (RMS) values. The RMS measurements can contribute in the subsequent studies more than instant values.

A microcontroller will acquire only discrete values, therefore in the RMS

calculations it is used a discrete method. RMS measurements can be calculated for a series of discrete values varying

function. The name, RMS, comes from the fact that it is the square root of the mean of the squares of the values. It is a power mean with the power p = 2.

The RMS for a collection of n values is:

(1.2)

In the project, it is important to monitor all the time the power consumption of the

FCL appliances, in order to know exactly the state of the load when a frequency event happens

. In addition, the accuracy of the power measures is not as important as the time

they are made. For example it is more important to have a power measure with accurate time stamp than the accurate power measurement itself.

The RMS values are obtained from the ADC samples. The ADC has to sample the

channels at a fast speed to have sufficient accuracy in measurements. Experimentally a sample rate of every 1ms is found enough for our purposes. This

sample rate allows us to calculate the RMS values from 20 measures within a cycle. It is also possible to select the number of cycles used in the calculation of RMS values, by default are used two cycles so 40 measures are involved in the RMS calculation process. The more cycles used in RMS values the more accurate is the result.

Introduction

7

In the worst case the power measure is displaced 1ms from the frequency

measurement which is affordable according to the project specifications. The maximum displacement is produced when the frequency measurement is made just before a new sample acquisition. As it is explained in following sections, frequency measurements are obtained every zero-crossing and RMS measurements every one millisecond.

9

2 ALGORITHMS, PROCEDURES AND RESULTS

This chapter describes the algorithms and methods used to develop the load

controller. In this chapter it is also show the results obtained by the

2.1. Frequency measurement algorithm This section describes the frequency measurement algorithm. It is based in

measuring the time between two consecutive rising zero-crossings.

t

Rising zero-crossing

Rising zero-crossing

T

Figure 2-I - period of a signal

The frequency measurement algorithm is part of the Control logic Type I and

Control logic Type II. In control logic Type I the frequency is used as a tripping criteria if it goes below

the frequency event threshold. In control logic Type II it is used to regulate the temperature set points according

to the control logic Type II equations, equation (1.1).

Algorithms, procedures and results

10

First of all is needed to detect when the power grid signal crosses by zero, then it is needed to measure the time between two consecutive crossings.

The DSC has a specific module that can carry out these actions, the capture unit (3.1.4.1.2 Capture unit), the capture unit is part of the periphery Event Manager (3.1.4.1

Event Manager). The capture unit is able to detect level changes at the signal connected with its

inputs. It can detect four different events, rising or falling edges and constant positive or negative level. The capture unit can be configured to detect any of them.

In order to simplify the level changing detection the capture unit has and Schmitt-

triggered gate at the input, this gate converts the power grid sinusoidal signal in a square signal with the same frequency. The square signal makes easy to detect the level changes in the input signal.

Figure 2-II - Schmitt-triggered output

The red plot in the figure above represents the output of the Schmitt triggered gate. The square signal period Tsq is the same as the sinusoidal one Tsin.

The capture unit has a timer associated, it is used as time base, when the capture

unit is enabled the timer stats to count. A signal event is detected when the level is maintained at least for two time base units.

Every time it is detected any of the selected signal events the capture unit carries

out the following actions. It stores the current count value of the timer in the specific two-level FIFO stack. It is also called the interruption subroutine configured in the capture unit

interruption vector (4.3.3.2.4 PIE initialization).


11

The FIFO stack, which contains two consecutive signal events, can be read from

the interruption subroutine. In the case of the load controller the capture unit is configured to detect the rising edges, which coincide with the beginning and end of a single cycle.

The power grid period is calculated in the interruption subroutine madding use of

capture time stored in the FIFO stack. The first capture time is subtracted to the second one, this subtraction results on the number of time base count units between the two rising edges. Knowing the time that corresponds to a count unit is easy to get the period of the power grid signal in seconds, whose inverse is the frequency.

Figure 2-III - Frequency measurement block diagram

This algorithm fails only when the counter is overflowed, in other words, when

the counter reach its maximum count value and starts again from zero. In this case, the second capture has a lower value because the counter has reach

the overflow value between the two captures. This is solved checking if the value of last capture is lower than the previous. If it is lower, a counter overflow is considered. In this case the period is obtained by adding the time from the first capture to the overflow

Level-Shifter

output Schmitt-trigger

CAP1FIFO.1 CAP1FIFO.1

CAP1FIFO.2

Stores the

Counter value

Shifts previous

value

-

Cycle period

CAP1FIFO.2

CAP1FIFO - CAP2FIFO

Time base clock


12

and the time between the overflow and the second. The Figure 2-IV - Overflow in

frequency counting illustrates the cases of a measurement with and without an overflow.

Figure 2-IV - Overflow in frequency counting

The timer base clock frequency cannot be selected arbitrarily. As is going to be

explained in a following section, the higher is the frequency the better is the accuracy, which is because the count unit is smaller and the quantification error is smaller too. However if the time base frequency is too much high it can be possible that more than one overflow happens between two consecutive zero crossings, which is impossible to detected it and in consequence the obtained measurement results wrong.

The interruption subroutine configured as the capture unit interruption subroutine

is capture1_srt().The code analysis of this subroutine is done in section 4.3.4

Capture unit subroutine: Capture1_srt().

As explained above the number of time base count units is proportional to the

period in seconds, it is only needed to know the time that corresponds to a single time base count unit and multiply it by the total number of time base count units.

The time base timer is fed by the High Speed Periphery Clock (HSCLK)

Without overflow

temp1_1

temp1_2

Temp1_2>temp1_1

p+n p+n+1 p+n+2 p+n+3 …

n

p-2 p-1 p p+1 p+2 p+3 …

Period = (n+p)-p=

= temp1_2 – temp1_1 =n

With overflow

temp1_1

temp1_2

Temp1_2<temp1_1

n

Period = p + (OF – k)=

= temp1_2 + (OF-temp1_1)=n

0 1 2 …. p p+1 p+2 p+3k k+1 … OF

Assuming OF as maximun

value of counter


13

+,-./ 0 12345

(2.1)

The time base timer has a count register of 16 bits. Therefore the maximum count value is 65535. In order to avoid more than one overflow within a power grid cycle the clock speed has to be reduced.

A regular power grid cycle has a period of 0,02 seconds, so that the clock speed has to be reduced to the speed that no more than 65535 count units can fit in 0,02

seconds. The way of reducing the input clock is using the prescaler included in the capture

unit. The prescaler divides the speed by a fixed value. The capture unit prescaler (CUPS) can take the values of the powers of two from 1 to 256. Some easy calculations conclude that the optimal prescaler is 8.

6-7 0 +,-./-78, 0 123459 0 :. <12345

(2.2)

Finally this clock speed is used to know the time in seconds that corresponds to a single count unit.

=-7 0 <:. <12345 0 >. :1?@ (2.3)

For example, if the Counter of the Capture unit gives the period value of 62500

count units, the calculations are the following: A8B 0 C12>> D >. :1?@ 0 >. >1@

(2.4)

68B 0 <>. >1@ 0 2>+5 (2.5)

Where TPG is the period and fPG is the frequency at power grid. It can be referred to a period expressed in the number as being in integer units.

Since the number of count units is always an integer number. The DSC works internally with the integer values. It will store and compare only

the integer values. It is attempted to use the integer values as much as possible, since the DSC do not have a float coprocessor. It only uses the values in Hz, which are expressed with float numbers, in the frequency decay measurement whose algorithm do not allows to do it with integer values due to an excessive lost of precision.


14

In order to make easy the conversion from the integer measures to the Herzl or Seconds measures it is defined a conversion factor FCF. This factor is not more than the frequency of the time base clock. E-E 0 :<12>>> F</HI

(2.6)

68B 0 E-EA-7 F+5I

(2.7)

A8B 0 A-7E-E F@I (2.8)

Where TCU is the period measured by the capture unit in integer units and fPG is the frequency at power grid in Hz as well as TPG is its period in seconds.

The following plot shows the measures of period directly returned by the Capture

unit interruption subroutine without averaging. The period is represented in integer units.

Figure 2-V – Capture unit measurements

62420

62440

62460

62480

62500

62520

62540

1 6 11 16 21 26

Instant Measures

Instant Measures


15

The next figure shows the instant frequency measurements again, but It is divided into the FCF. Therefore the frequency is represented in Hz.

Figure 2-VI - Instant Frequency measurements

As seen in the plots, the frequency has some fluctuations. These fluctuations are

reduced by averaging the output frequency measurements in order to improve the accuracy.

The instant frequency measurements are not stored after being used in the averaging calculations; that is because the plots within this section shows only 30 measurements in a row, in following sections and in the appendix can be found other plots with more consecutive measurements.

49,950

49,960

49,970

49,980

49,990

50,000

50,010

50,020

50,030

50,040

1 6 11 16 21 26

Instant Measures

Series1


16

2.1.1. Averaging measures As seen in the previous section, the instant frequency measurements presents

some fluctuations, in order to improve the accuracy and stabilize the measurements it is use the average of a selectable amount of instant measurements. These averaged measurements are the ones used in the threshold checking.

The more instant measures used in the average the more accurate is the measure,

but the more measurements are used the more increases the delay of a measure. A frequency change will be assuredly detected after the number of cycles used in

the average. This is because the frequency event measures are spread within the cycles in the average and is not assured that the measures within a frequency event will change the average enough to fulfill the threshold, at least with the early measures.

The error is cancelled in the inner averaged measurements and the error in the first

and the last cycle is spread in all the cycles.

Figure 2-VII - Error spread using average

The positive error in one cycle is the opposite in the adjacent cycles. The only

error that is not cancelled is the error produced by the first and the last measure. This error is divided according with the cycles used in the average.

In instance of using the average of 25, the default in the project, the measurement

delay is 0.5 Seconds. A the detection of a frequency event is not assured until 0.5 seconds.

Real zero-crossings

Sensed zero-crossings

time

Individual error


17

The instant measurements averaged can be observed in the following plot.

Figure 2-VIII - Averaged frequency measurements in integer values

The next plot shows the same values as the previous one but in Hz units.

Figure 2-IX - Averaged frequency measurements in Hz

The figure above shows the averaged frequency measurements in Hz, comparing

these plots with the previous instant measurements in section 0


62498

62499

62500

62501

62502

62503

62504

62505

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

Average of 25 values

Average of 25 values

49,995

49,996

49,997

49,998

49,999

50,000

50,001

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

Average of 25 values (Hz)

Average of 25 values (Hz)


18

Frequency measurement the measures are smother. In the following figure is possible to compare in the same plot the instant

measures with the averaged measurements.

Figure 2-X - Instant and averaged measurements

It can be found more plots of frequency measurements in appendix C Other plots.

2.1.2. Maximum theoretical Accuracy This section explains the maximum theoretical accuracy that could be reached

using the frequency algorithm explained in the previous sections. In this section is considered that the input power grid signal is clean of noise and

the only source of error is the quantification error of the capture unit. As obvious, the accuracy calculated in this section is not the accuracy of the load

controller but it is the maximum reachable accuracy. The frequency measurement depends on the frequency of Capture unit clock. It has an error of ±1 count units every measure. But as explained in section 0


Frequency measurement algorithm the capture unit clock frequency cannot be increased more than a limit.

49,950

49,960

49,970

49,980

49,990

50,000

50,010

50,020

50,030

50,040

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

instant Vs average measures

Instant values (Hz) Average, 25 values (Hz)


19

Figure 2-XI - frequency counting error

The figure above explains the error of measurements. It shows how are measured

cycles whose edges are just in the limits of the Capture unit cycles. These case produces the measurements with the error of +1 or -1 count units.

In other cases the excess time compensates the lost time, always withing the range

of the absolute error is ±1 time base count units. The absolute in error in period can be expressed with the following equation. ∆AJKL 0 M< (2.9)

N represents the number of time base count unit, therefore the error does not depend on the frequency measured.

The accuracy or relative error depends on the frequency measured. In lower frequencies, the number of time base count units is higher, for that reason

the absolute error is proportional smaller than the measure itself. In higher frequencies the number of time base count units is smaller and the absolute error is proportional higher.

Case of counting one unit less

EV clock:

Real length of period signal

The period

have not

started yet

Here starts

The counting

Here ends

The counting

Lost time

Ends just before

checkingStarts just

after

checking

Case of counting one unit more

EV clock:

Real length of period signal

Here starts

The counting

Signal period

have not

finished yet

Excess time Ends just after checkingStarts just

before

checkingExcess time

Here ends

The counting


20

As explained in section 0


Frequency measurement algorithm. The capture unit uses a GP timer to count the Capture Unit Cycles between rising edges. The timer is a 16-bit-timer so the maximum count is from 0 to 216-1 or from 0 to 65535 in decimal.

The Capture unit is fed by the high speed periphery clock that runs at 25Mhz.

Using directly this clock in a regular power grid cycle (1/50Hz=20ms) the counter should count 500000 that is higher that the overflow limit of the counter. A prescaler is used to reduce the clock speed.

Using all the data above is possible to calculate the theoretic accuracy at 50Hz, the

calculations are the following:

∆A 0 JK M <L N K6OP 0 M<6OP 0 M>, :1μ@ (2.10)

So that the period of a signal at 50Hz will have values between

TPG(50Hz)=0.02s+∆Ts=0.02±32µ

(2.11)

These periods corresponds to these frequencies:

6STU 0 <ASVW 0 <1>. >>>:1S@ 0 XY, YYY1+5 (2.12)

That is a relative error of: fmin-50=-0.8Hz And finally:

6SVW 0 <ASTU 0 <<Y. YYYC9S@ 0 2>, >>>9+5 (2.13)

That is a relative error of:


21

fmax-50=0.8Hz In summary, at 50Hz we have an accuracy of ∆f(50Hz)=±0.8Hz, or a relative

error of 1,6%, The relative accuracy depends on the frequency measurement, at higher speeds the absolute error can be proportional higher and the accuracy is worse.

The use of accuracy improves the accuracy. The error is divided into the number

of instant frequency measurements.

2.1.3. Soft frequency filter Experimentally it is observed that some measures differ too much from expected

measures. These measures are produced by external interferences such as the interferences produced by the physical movement of the extension cord.

In order to avoid these fake measures it is implemented a frequency filter by software.

This filter checks every measure if the frequency decay is higher than a limit. In the case the measure exceeds the threshold the measurement takes the value of the previous one. The frequency threshold in this filter is too much higher than the frequency decay in the power grid in normal state and within a frequency event.


22

Figure 2-XII - Software frequency filter block diagram

The filter basically compares the last measure with the previous one, if the

different between them is higher than the limit stored in the attribute MAXIMUN_FREQUENCY_CHANGE the output frequency is the last measure, otherwise it is used the unmodified frequency measure.

By default it is used the value of 150 time base count units between two

consecutive frequency measurements, it corresponds at 50Hz to a decay of ±6Hz/s, the control logic type II uses a decay of -0,16Hz/s

2.1.4. Frequency sensor range The speed of the clock that feeds the capture unit sets the frequency range The lower limit is when the period is enough long to have more than one overflow

inside. The limit is equal to the overflow limit of the counter, 65535 EV-cycles →65535/3.125 MHz ≈ 0,021ms = 47,7Hz

Attribute:

MAXIMUN_FREQUENCY_CHANGE

Last frequency measure

Prev. Frequency measure

Frequency out

-

Outs

the

higher

+

Outs

the

lower


23

, that is much lower than the limit in the specifications. If the period is longer is not possible to be sure that more than one overflow happens within a cycle.

The higher frequency hypothetically has the limit when the frequency is so fast to

at least count one unit in but is not useful because the relative error is ±100%. Therefore the higher frequency limit is at the point where the accuracy drops below a desider limit.

2.1.5. Accuracy In the accuracy study it was not possible to obtain the signal to noise ratio of

power grid line, and also it was not possible to obtain the Spectral Frequency Noise density present in the working frequency band, moreover the manufacturer of DSC don’t provide the hysteresis windows width and finally it was not available a frequency counter with enough accuracy to compare the measurements made by the load controller. Therefore it is not possible to do a theoretical study of accuracy.

The study of section 2.1.2 Maximum theoretical Accuracy gives the maximum

theoretical accuracy, but not the accuracy of the Load Controller. Assuming the frequency measurements were not taken within a frequency event.

The measurements showed in this project are randomly chosen from several similar measurements in different times, therefore it not probable that the frequency measurements where done within a frequency event.

The frequency measurements vary in the experimental measurements not more

than 15 mHZ within a measurement session, that means that this fluctuations can be due to regular power grid fluctuations but it cannot be possible to ensure it.

Therefore the accuracy of this load Controller is within the range of ±0.8mHz and

±7,5mHz. The minimum accuracy grated by the load controller is enough for its purposes.

Minimum grated accuracy ±7,5mHz. @50Hz Maximum delay: 0,5seconds.


24

2.2. Frequency decay measurement The frequency decay is measured by the average of the frequency changes within

a selectable number of consecutive power grid cycles. The frequency decay measurement is part of the control logic Type I.

In the control device as explained in section 0


Frequency measurement what is really measured is the period in number of cycles of EV clock, otherwise, the time between zero-crossings.

The frequency of the sample is the inverse of the period and the time between

frequency measures is the period itself.

Figure 2-XIII - Frequency decay

As seen in the figure above, the time between two correlative measures is the

period of the second one and the frequency change is the subtraction of the inverses of correlative period measures.

The frequency decay is defined as the difference of frequency in any amount of

time. It is obtained from the period measures with the following equation:

time

Frequency

1/T0

1/T1

Δt=T1

Δf=1/T1-1/T0


25

EZ 0 ∆6∆= 0<A< N <A>A< 0 A> N A<A> D A<1

(2.14)

In section 0


Frequency measurement it was described that the measure of the periods is measured in number of EV cycles.

The frequency decay measurement algorithm uses lots of resources. The

calculations made in this algorithm needs more calculation power than others algorithms. The frequency and RMS calculations are made with the integer values from the ADC and the EV but this algorithm cannot be made using the integer values due to the rounding. The operations must to be float operations, not integer operations.

The internal operations made by the CPU are specially selected to avoid as much

as possible the float operations and use the integer and long operations.

E[\][U^_ Z[^V_ `+5@ a 0 ∆6∆= 0 E-E D b <c3< N <c3>dc3<E-E 0

0 E-E1 D c3> N c3<c3<1 D c3> 0 E-E1c3<1 D c3> N c3<c3> 0 E-E1

c3<1 D ec3>c3< N <f

(2.15)

Where FCF is the Frequency conversion factor that relates the integer values with

the frequency values in Hz. See 0


Frequency measurement. And AM1 represents the last frequency measurement value and AMs0 represents

the previous one. Note that AM are the integer values given by the Capture unit and they are period measurements.


26

g is a long multiplication, the rest of operations are float operations, one division, one subtraction and one multiplication.

The frequency decay measurements are averaged in order to have more accurate

results. The average can be done with a selectable number of frequency decay results. By default it is done the average of last 5 values.

Figure 2-XIV – Frequency decay

2.3. Control logic Type I: Frequency Thresholds The load tripping according to the frequency and frequency decay measured

implement the control logic Type I. The load controller can be in three different states depending on the frequency

sensed. The default sate is the CLOSE state. In this state the frequency is higher than the

lower frequency threshold. Therefore the power grid is not within a frequency event. The load is connected with the power grid.

If a frequency event is detected, when the frequency goes below the frequency

threshold, the state is changed to OPEN state. In this state the load is disconnected. The load will remain always disconnected while the frequency is below the recover frequency event, which is higher than the frequency threshold.

-0,1

-0,05

0

0,05

0,1

1 29 57 85 113 141 169 197

Frequency decay (Hz/s)

frequency decay


27

Once the frequency is recovered, so the recover threshold is fulfilled, the state is changed to WAIT state. When the load controller enters in this state, it is set a random time to attachment. The load controller remain in this state while the delay time is over, when the delay time is up the load controller changes to CLOSE state, being the load reconnected. In this state it is also checked if the frequency returns below the frequency threshold cancelling the reconnection and changing the state to OPEN again.

The default thresholds used are the following. The frequency values in integer

units is obtained by using the conversion equation (2.7): DEFAULT_HIGHER_LIMIT = 62525 = 49,98Hz DEFAULT_LOWER_LIMIT = 62626 = 49,89Hz The default lower threshold can be also called default frequency event threshold.

In the case of the frequency below this threshold it is considered the power grid under a frequency event.

The default higher threshold it can be called also the recover threshold, this threshold defines the frequency threshold which in the case of being surpassed within a frequency event the frequency event is considered to be recovered.

Figure 2-XV – Averaged frequency measurements vs frequency thresholds

The frequency decay threshold works in a similar way as frequency threshold in

exception that the frequency decay event has a single threshold, it is used the same

49,8

49,85

49,9

49,95

50

50,05

50,1

1 29 57 85 113 141 169 197

Averaged Vs Thresholds

Average measurements recover threshold frequency event threshold


28

threshold for detecting a frequency decay event and checking the frequency decay event recover.

Figure 2-XVI Frequency decay Vs Frequency decay threshold

The next figure shows the state flow diagram, the load controller starts by default

in the state CLOSE. The circles represent the states. The “f” inside the decision blocks

is the last frequency measure acquired. Lower_limit is the frequency threshold and

higher_limit is the recover threshold. Decay represents the last frequency decay measurement and limit represents the frequency decay threshold.

-0,2

-0,15

-0,1

-0,05

0

0,05

0,1

1 29 57 85 113 141 169 197

Frequency decay Vs Threshold

frequency decay decay threshold


29

Figure 2-XVII- Threshold checking flow diagram


30

2.4. Control logic Type II: Temperature Set points change

The dynamic temperature set points regulation implements the control Logic Type

II. As explained in the introduction, this control logic is not completely implemented.

This control logic is based on regulate the load temperature set points dynamically, according to the frequency measured in the power grid.

This control logic is applicable only to the loads that has a thermostat with two set

points, and the load is only started when it reach one of the set points and it is stopped when the temperature reach the other set point.

In this loads, a fridge or an electric heater can change the normal set points by the

user. The load controller should modify this normal set points according to the frequency measured.

The load controller assumes that the input normal temperature set points are

introduced in the load controller thought the ADC. The thermostat should have two analog outputs which vary from 0 to 3 Volts depending on the temperature set point.

This normal temperature set point reading method is only a proposal that could be changed depending on the load.

The load controller has to calculate a new high and low set points depending on

the power grid frequency. The output Temperature set points are calculated with the following equation:

)(*

)(*

0

0

ffkfTT

ffkfTTnormal

lowlow

normalhighhigh

−−=

−−=

(2.16)

The input set points are assumed to be an integer number, the output temperature

is an integer too, the Kf factor has to be regulated to use the Temperature in integer units, as well as use the frequency measurements in integer units too.

The load controller stores the new temperature set points in a variable, the

variable should be used to change the temperature set points according to the interface used to set the temperatures in the load thermostat.


31

The normal temperature set points that should be read by the ADC are read in the ADC interruption subroutine (4.3.5 ADC interruption subroutine: ADC_srt()) the output temperature set points are calculated in the capture unit interruption subroutine (4.3.4

Capture unit subroutine: Capture1_srt()), the set points are calculated every frequency measurement, every 0,02 seconds

2.5. Voltage, current and Power measurement This section describes the process of RMS voltage, current and power

measurement. First of all it is described the sampling method, and finally the process of obtaining the RMS values from the instant measurements, it is also show some sample plots of the measurements made by the ADC.

2.5.1. Sample acquisition The sample acquisition is made by the ADC. As explained in section 3.1.4.2 ADC

the ADC is configured to sample the voltage and current channel every one millisecond

The sample acquisition is made by the subroutine adc_isr(void). The EV is configured to start the ADC conversion every one millisecond, once the

ADC has the sampling results available the interruption subroutine is called. Every time this subroutine is executed it is ensured that the ADC registers has

ready to use the last measures stored inside. At this point the offset of each channel is subtracted to the measure of the input

signals. The measures of voltage and current, with the offset already subtracted, are stored

in an array, one array for each channel. These arrays contain by default the last 40 measures of voltage and current those

are used to calculate the power and RMS values. Note that this subroutine stores the integer values of these measures and not the

floating point values corresponding for the equivalent in Volts or Amperes. The DSC works every time with these integer values simplifying the calculations.

As seen in section 3.1.4.2 ADC the values in volts or in amperes are obtained directly with fixed operations that can be made in the analysis time, that mean, when the measurements are retrieved into the server.


32

This subroutine doesn’t calculate the RMS power, voltage and current but it calculates the square of the measures. The capture unit interruption subroutine is the responsible of the RMS calculations and it uses the last 40 measures from the ADC. In the RMS calculations is needed the square of these measures and doing it in the ADC subroutine it is only needed to do it once every new measure, otherwise the capture unit subroutine should do the square of last 40 ADC measures, which would result in not efficient DSC calculation power usage.

2.5.2. Acquired measures This section shows the plots of the measures made by the ADC. The first two plots shows the integer measures given by the ADC. These measures

are within the range of the ADC, between 0 and 4096. Next two figures show the integer values given by the ADC channels of current

and voltage.

Figure 2-XVIII - ADC curret measures

0

500

1000

1500

2000

2500

3000

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Cu

rre

nt

Va

lue

s

samples

Input Current


33

Figure 2-XIX - ADC Voltage measures

The offset has been measured without connecting any signal to the ADC input.

The offset is so stable that it can be considered as a constant value. The offset in current and voltage is estimated in 1904 and 1921 ADC integer

units. The signals used in all the load controller internal calculations are integer values

given by the ADC subtracted with the corresponding offset. These measurements can be observed in the two following figures.

Figure 2-XX - Integer measures of current without offset

0

500

1000

1500

2000

2500

3000

3500

4000

4500

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Vo

lta

ge

va

lue

s

samples

Input Voltage

-3000

-2000

-1000

0

1000

2000

3000

1 11 21 31 41 51 61 71 81

Cu

rre

nt

Va

lue

s

samples

ADC Current integer measures

(without offset)


34

Figure 2-XXI - Integer measures of voltage without offset

The measures above can be also observed in I.S. units of measure in the next two

figures. These values are obtained using the method described in section 3.2.2 Current

and voltage values at load controller inputs.

Figure 2-XXII - Measured Current

-3000

-2000

-1000

0

1000

2000

3000

1 11 21 31 41 51 61 71 81 91

Vo

lta

ge

(in

t)

samples

ADC Voltage integer measures

(without offset)

-2

-1,5

-1

-0,5

0

0,5

1

1,5

2

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Cu

rre

nt

(In

t)

samples

Input Current


35

Figure 2-XXIII - Measured Voltage

With the measurements of voltage and current it is possible to calculate the RMS

power. The RMS power is calculated using the individual values of current and voltage. Therefore it is first calculated the instant power and then is calculated the RMS power using the same method used in voltage and current.

The next figure shows the instant power values in integer units.

Figure 2-XXIV - Instant power in integer units

The figure below shows the instant power in S.I units.

-400

-300

-200

-100

0

100

200

300

400

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Vo

lta

ge

(V

)

samples

Input Voltage

0

200000

400000

600000

800000

1000000

1200000

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Po

we

r (W

)

samples

Instant power (integer untis)


36

Figure 2-XXV - Calculated instant Power

In order to improve the accuracy the channels are oversampled, therefore the

channels are sampled many times in a row and it is use as final measurement the average of all of them.

In this prototype it is use the oversampling of two values, the load controller

hardware allows up to oversample the channel eight times. The time between consecutives samples is 250ns which is enough small compared with the signal period to permit the oversampling.

2.5.3. RMS Current, voltage and power calculation

The Current, voltage and power in RMS values are calculated in the same

subroutine where the frequency is measured (Capture1_isr). RMS Voltage, current and power is calculated using this equation:

h3, 0 i∑ cZ-S[V@]k[T1KTl> K (2.17)

0

100

200

300

400

500

600

700

800

900

1000

1 6

11

16

21

26

31

36

41

46

51

56

61

66

71

76

81

86

91

96

Po

we

r (W

)

samples

Input power


37

Where ADC_MEASUREi represents the integer sample made by the ADC or the multiplication of the voltage and current samples in the case of the power RMS measurement.

N represents the number of measures used in the calculation, by default this value

is 40, therefore, the RMS value is calculated according to the last two cycles. In order to simplify the RMS calculations, the square of the instant samples are

stored in specific arrays, this avoids recalculating the instant sample squares every time a RMS calculation is done. It is only calculated the square of the new samples.

In summary the load controller does the following calculations in order to calculate the RMS values:

h3, 0 i ∑ adc_square_sampleTKTl> K (2.18)

Where adc_square_sample represents the respective squared samples array

(voltage, current or power) The square samples are calculated in the ADC sampling subroutine (4.3.5 ADC

interruption subroutine: ADC_srt()) in the array adc_square_voltage[] for voltage,

adc_squeare_current[] for current and adc_squeare_power[] for power. The following plots show the measurements made by the load controller in integer

units. RMS current measurement:

Figure 2-XXVI - Measured RMS current (int)

360

360,5

361

361,5

362

362,5

363

363,5

1 11 21 31 41 51 61 71 81

Cu

rre

nt

RM

S (

Int)

RMS Current (Int)


38

RMS voltage measurements:

Figure 2-XXVII - Measured RMS Voltage (int)

And finally the RMS power measurements:

Figure 2-XXVIII - Measured RMS power (int)

It is used all the time Integer values that simplify the calculations and the

subroutine can be executed faster. The integer values have a direct relation with the values in Volts, Amperes or Watts.

1407

1407,5

1408

1408,5

1409

1409,5

1410

1410,5

1 11 21 31 41 51 61 71 81

Vo

lta

ge

(IN

T)

RMS Voltage (Int)

0

100

200

300

400

500

600

700

800

900

1000

1 11 21 31 41 51 61 71 81

Po

we

r R

MS

(In

t)

RMS power (int)


39

In the case of the Voltage this relation is:

Ph3, 0 P_cZ- h3,Ex (2.19)

Where Fv is the conversion factor from ADC values to Real values and it can be

calculated by the following way:

Ex 0 X>YC: D yx (2.20)

Where gv is the total gain of the Voltage channel. In the case of the Current this relation is:

zh3, 0 z_cZ- h3,ET (2.21)

Where Fi is the conversion factor from ADC values to Real values and it can be

calculated by the following way:

ET 0 X>YC: D yT D <> (2.22)

Where gi is the total gain of the current channel. And 10 is the resitance of the

resistor connected at the ADC input The power RMS is also calculated using the integer values given by the ADC.

The RMS power can be obtained from the RMS power calculated with the integer values using the following equation:

8h3, 0 8_cZ- h3,E (2.23)

Where P_ADCRMS is the power calculated from the integer ADC measures and Fp

is the power conversion factor that is defined in the following equation:


40

ET 0 ET D Ex 0 X>YC D h D yT: D X>YC D yx: 0 X>YC1:1 D yT D yx (2.24)

Where R is the resistor connected to the ADC current channel (see 3.1.4.2 ADC) They are some reasons because the calculation is made this routine instead of be

done in the ADC subroutine, the sampling routine. ADC subroutine is executed every 1ms, 20 times every power grid cycle, but the

RMS values are only needed one time every power grid cycle, which is the measurements rate specified in the specifications.

By doing it in the ADC subroutine results in 20 measurements of RMS values per cycle, which means calculating it 20 times per cycle. That requires more performance that the DSC can deliver.

The other reason is that the RMS values have to be of the same cycle of the frequency measure. By doing the RMS calculations in the same subroutine as the frequency measurement it is ensured that the RMS results correspond to the same cycle as the frequency value.

Figure 2-XXIX - Measured RMS current (A)

RMS voltage measurements:

2,196

2,198

2,2

2,202

2,204

2,206

2,208

2,21

2,212

2,214

2,216

2,218

1 11 21 31 41 51 61 71 81

Cu

rre

nt

RM

S (

A)

RMS Current (A)


41

Figure 2-XXX - Measured RMS Voltage (V)

And finaly the RMS power measurements:

Figure 2-XXXI - Measured RMS power (W)

The three figure above shows the RMS values of current, voltage and power in the

international system of units but the DSC works internally with the integer values, the plots of the RMS results in integer values are omitted in this section and it can be found in the appendix C Other plots. In the appendix it can also be found the tables of values of these plots.

224

224,1

224,2

224,3

224,4

224,5

224,6

1 11 21 31 41 51 61 71 81

Vo

lta

ge

(V

)

RMS Voltage (V)

616000

617000

618000

619000

620000

621000

622000

623000

1 11 21 31 41 51 61 71 81

Po

we

r R

MS

(W

)

RMS power (W)


42

As well as explained in the frequency accuracy it is not enough available data to calculate and exact voltage, current or power accuracy.

The maximum variation in RMS voltage measurements is 0,6 V in all the voltage

measurement sessions, therefore the voltage accuracy should be better than ±0,3V. This corresponds to an accuracy of ±0,13%

Using the same reasoning as before the maximum variation in Current

measurement is 0,03A, therefore the current accuracy should be better than ±0,015A. This corresponds to an accuracy of ±0,05%.

Finally referring to the power measurements the maximum variation observed is

10W in the test load. Therefore the power accuracy should be better than ±5W. This corresponds to an accuracy of ±0,8%.

All the results described above are only estimated results that could change

depending on the test load stability. It should be considered a detailed accuracy study.

Accuracy

Voltage ±0,3V

Current ±0,015A

Power ±5W

Note that this result are done using the test load of nominal 600W. The current

accuracy could be improved by expanding the current signal in the ADC conversion range, it can be done by changing the number of loops in the current transformer.

The maximum RMS measurement delay is 1ms.

2.6. Real-time stamp The real time stamp is used in order to locate the measurements in time. The time stamp is a long integer value that is incremented every one millisecond.

The Real-time system also offers the possibility to get the current time and also to synchronize the time stamp with a external time source.


43

The time stamp register is incremented in the ADC interruption subroutine that is

periodically executed exactly every one millisecond. The time stamp uses an arbitrary date as origin. For example choosing January 1st

of 2008, the register will contain the millisecond elapsed from that date. The time stamp is valid until the register doesn’t overflow. Long integer variables

stores 64 bits so that the total time while this load controller can work is: |~ 0 2 0 18446 D 10 Therefore the time stamp will remain valid until around 584942417 years. What is

more than enough.

The function time_synchronization(long time) sets the current time to the time passed in the argument.

The current time is obtained by reading the current_time variable.

45

3 HARDWARE

This chapter explains everything related with the hardware, the selection of DSC,

design of the board and description of the developing board.

3.1. DSC The DSC (Digital signal controller) is one of the most important parts of the

hardware. It is the core of the control device. It manages the hardware and made the calculations.

As a key part of the project, a deep research had been made. The conclusion of

the research is show within this section. The function of the DSC can be made also by microcontrollers (µC) and Digital

Signal Controllers (DSC), they are some differences between then. In the following paragraphs the different proposals are compared.

The microcontroller is designed for a wide field of uses but not for any specific

function. Therefore, they are capable of virtually carry out any application, it is designed as a generic device. Microcontrollers are also easy to use and cheap.

Referring to this project, microcontrollers in budget do not have enough signal processing features. A more specific solution is needed. Regular microcontrollers are not able to carry out all the requirements of the control device. In instance they are used to be lack of ADC inputs and other signal processing specific hardware, such as a 32 bit MAC (Multiplication And aCcumulation) module needed to carry out the numerous multiplications needed in the RMS calculations.

The DSPs solves the typical microcontroller problems described above. They

have specific instructions for signal processing, the used to have enough ADCs and they

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46

are quite powerful. But like the microcontrollers, DSPs have some problems, they are more expensive and difficult to program and they use lack on general purpose peripheries like Universal Asynchronous Receiver-Transmitters (UART) or Serial Periphery Interfaces (SPI), being needed to use a microcontroller as co-processor.

Therefore it will be very effective in Signal processing but not so good in other stuff.

The solution is a DSC. The DSC is basically a Microcontroller with DSP

capabilities. They have a microcontroller as core with the common peripheries in microcontrollers (UART, SPI, Timers, GPIO and so on) and they have also peripheries common in DSPs (ADCs, MAC, EV).

It is as simple to program as a microcontroller, even having some signal specific instructions.

For that reason is decided to use a DSC that is more flexible than a DSP and has more Signal processing capabilities than a microcontroller.

3.1.1. DSC prerequisites The project specifications determine some features that the DSC must have in

order to fulfill all the specifications The aim of the project is measure the frequency of the power grid as well as the

power consumption of the controlled appliances. It should be able to measure in the future tri-phased signals if the project is continued by that way.

Power measurement specification requires that the microcontroller must have an

ADC with multiple input channels. It must have at least two channels for a mono-phase power grid source, one for voltage and other for current. These two channels must also be sampled at simultaneous time, in other words, it must have at least one dual channel able to sample both of the inputs at the same time.

Looking for the lower complexity the best option is to choose a DSC that has the

ADC on-chip with at least one dual channel, for a single phase of Current and Voltage. The DSC is hast to do some complex calculations periodically, so it is required

that it is able perform all the calculations within the period of available time. It has to calculate the average of last frequency measures, frequency decay and also voltage, current and power in RMS values, all of them every power grid cycle.

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The DSC must have a MAC module able to calculate 16x16 (used in RMS voltage

and current calculations) and 32x32 (used in RMS power Calculation) integer multiplications. The RMS calculations made an intensive use of multiplications every a short amount of time (1ms), these MAC unit is essential to ensure that all of the calculations are made before the next RMS calculation.

The DSC has to support the connection of external memory. All the previous

measurements before a frequency event should be stored in order to send them to the server. The external memory connection can be done using the on-chip external memory interface (cable select outputs and memory address outputs) or using a seral flash memory (using the SPI periphery).

Finally according the DSC should have a UART port in order to connect the

GPRS module for data communications between device and a Server. Other matters not related with the technical features had been considered in order

to take the best decision. It has been considered the availability of a developing board, a board with the

DSC integrated and with the PC connection ports, in order to start quickly the developing of the hardware.

The availability of a good Integrated Development Environment (IDE),

more details in section 4.1 IDE, had also been considered, as well as the support and documentation of the manufacturer and obviously, the final price.

A detailed research drops as result that the best option is the TSM320F2812

manufactured by Texas instruments. Its technical features are showed in the next section.

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3.1.2. DSC Technical features The features of the selected DSC are the following.

High-Performance Static CMOS Technology

150 MHz (6.67-ns Cycle Time)

Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design

3.3-V Flash Programming Voltage

JTAG Boundary Scan Support

High-Performance 32-Bit CPU (TMS320C28x)

16 x 16 and 32 x 32 MAC Operations

16 x 16 Dual MAC

Harvard Bus Architecture

Atomic Operations

Fast Interrupt Response and Processing

Unified Memory Programming Model

4M Linear Program Address Reach

4M Linear Data Address Reach

Code-Efficient (in C/C++ and Assembly)

TMS320F24x/LF240x Processor Source Code Compatible

On-Chip Memory

Flash Devices: Up to 128K x 16 Flash

(Four 8K x 16 and Six 16K x 16 Sectors)

ROM Devices: Up to 128K x 16 ROM

1K x 16 OTP ROM

L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM)

H0: 1 Block of 8K x 16 SARAM

M0 and M1: 2 Blocks of 1K x 16 Each SARAM

Boot ROM (4K x 16)

With Software Boot Modes

Standard Math Tables

External Interface (F2812)

Up to 1M Total Memory

Programmable Wait States

Programmable Read/Write Strobe Timing

Three Individual Chip Selects

Clock and System Control

Dynamic PLL Ratio Changes Supported

On-Chip Oscillator

Watchdog Timer Module

Three External Interrupts

Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts

128-Bit Security Key/Lock

Protects Flash/ROM/OTP and L0/L1 SARAM

Prevents Firmware Reverse Engineering

Three 32-Bit CPU-Timers

Motor Control Peripherals

Two Event Managers (EVA, EVB)

Compatible to 240x Devices

Serial Port Peripherals

Serial Peripheral Interface (SPI)

Two Serial Communications Interfaces (SCIs), Standard UART

Enhanced Controller Area Network (eCAN)

Multichannel Buffered Serial Port (McBSP) With SPI Mode

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49

12-Bit ADC, 16 Channels

2 x 8 Channel Input Multiplexer

Two Sample-and-Hold

Single/Simultaneous Conversions

Fast Conversion Rate: 80 ns/12.5 MSPS

Up to 56 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins

Advanced Emulation Features

Analysis and Breakpoint Functions

Real-Time Debug via Hardware

Development Tools Include

ANSI C/C++ Compiler/Assembler/Linker

Supports TMS320C24x™/240x Instructions

Code Composer Studio™ IDE

DSP/BIOS™

JTAG Scan Controllers [Texas Instruments (TI) or Third-Party]

Evaluation Modules

Broad Third-Party Digital Motor Control Support

Low-Power Modes and Power Savings

IDLE, STANDBY, HALT Modes Supported

Disable Individual Peripheral Clocks

Package Options

179-Ball MicroStar BGA™ With External Memory Interface (GHH), (ZHH) (2812)

176-Pin Low-Profile Quad Flatpack (LQFP) With External Memory Interface (PGF) (2812)

128-Pin LQFP Without External Memory Interface (PBK) (2810, 2811)

Temperature Options:

A: -40°C to 85°C (GHH, ZHH, PGF, PBK)

S: -40°C to 125°C (GHH, ZHH, PGF, PBK)

Q: -40°C to 125°C (PGF, PBK)

This DSC fulfills all the prerequisites. It has enough ADC inputs, it has all the

external interfaces required, it is not expensive and it has enough calculation power. It also has a specific periphery that carries out the frequency measurement, the Event Manager (EV).

Figure 3-I - Texas instruments Logo

The final price of a single DSC unit is about 75DKK, depending on the amount purchased the price can be lower.

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3.1.3. DSC Hardware Description This section describes the DSC hardware and the peripheries on-chip.

3.1.3.1. C28x CPU

The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is an efficient C/C++ engine, enabling users to develop their system control software in a high-level language using C/C++.

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing

capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. This is perfect for the calculation of power from voltage and current in real time which requires lots of long multiplications.

The C28x has an 8-level-deep protected pipeline with pipelined memory accesses.

This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Therefore this CPU is able to execute up to 8 instructions at the same time.

Special branch-look-ahead hardware minimizes the latency for conditional discontinuities, so in branches the execution taken up again more efficiently. This feature is very useful in the project that is based in asynchronous and synchronous interruptions, shouted by the power grid cycles and ADC every sample. That ensures a good performance on the interruption execution against the continuous changes of context. Every time that an interruption is called, the microcontroller must save the context of execution, load the specific context of the interruption and when it ends the interruption execution it must restore the previous context.

This change of context happens around 20ms in asynchronous interruption (every power grid zero-crossing) and every 1ms in periodical interruption (sample rate of ADC).

3.1.3.2. Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between

the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of

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51

22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. This feature increases the execution speed being able to retrieve the results of the peripheries at the same time that the next instruction is read.

3.1.3.3. Real-Time JTAG and Analysis

The F281x implement the standard IEEE 1149.1 JTAG interface. Additionally,

the F281x support real-time mode of operation whereby the contents of memory, peripheral, and register locations can be modified while the processor is running and executing code and servicing interrupts. This is very useful in the debug stage where it is necessary to trace the running of the program and in also useful to modify the register to emulate external events.

The F281x implement the real-time mode in hardware within the CPU. This is a unique feature to the F281x, no software monitor is required. Additionally, special analysis hardware is provided that allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs. The features above can be done using the parallel connection with the Personal computer (PC)

A specific JTAG emulator hardware also allows the user to write inside the on-chip flash memory unfortunately it cost about 1300$ (6 857DKK), but in this prototype there is enough memory with only the on-chip and external RAM memory. So that it is not used in this project stage.

3.1.3.4. SARAMs

The DSC contains two blocks of single access memory, each 1K x 16 in size. The

stack pointer points to the beginning of one of this block on reset. The F281x also contains an additional 16K x 16 of single-access RAM, divided

into 3 blocks (4K + 4K + 8K). Each block can be independently accessed hence minimizing

pipeline stalls.

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Figure 3-II - DSC Memory map

The RAM memory described in this section is not all the memory available in the

load controller; it is only the on-chip RAM. External RAM from the Developing Boar is also available.

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3.1.3.5. Flash

The F2812 contain 128K x 16 of embedded flash memory, segregated into four

8K X 16 sectors, and six 16K X 16 sectors The user can individually erase, program, and validate a flash sector while

leaving other sectors untouched. However, it is not possible to use one sector of the flash to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash is mapped to both program and data space; therefore, it can be used to execute code or store data information.

The use of flash is slower in program execution speed than the internal RAM. In order to use the flash memory is mandatory to use the JTAG emulator. The JTAG was not purchased and the final program is inserted it in RAM memory. Anyway, the interruption functions developed in this prototype are time critical function and they must be on the RAM memory.

3.1.3.6. Security

The F281x and C281x support high levels of security to protect the user firmware

from being reverse-engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/ROM and the SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which matches the value stored in the password locations within the Flash/ROM.

In this project I will not use this feature that will be only useful in a final product in order to avoid the copy of the source.

If using this feature it is possible under some circumstances to leave the microcontroller locked, so that the memory is unprotected all the prototyping time.

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3.1.3.7. Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of

interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the DSC, 45 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

In this project the interruptions are essential. The ADC interruption has higher priority because it is executed every 1ms versus the frequency measurement interruption that is executed every 20ms. The remaining time for the frequency interruption (time where the ADC interruption is not executing) is more than enough to complete the desired calculations.

3.1.3.8. Oscillator and PLL

The DSC can be clocked by an external oscillator or by a crystal attached to the

on-chip oscillator circuit. A Phase Locked Loop (PLL) is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. The PLL block can be set in bypass mode in order to use the external source. This PLL feeds the main clock of the DSC, in this project it is set up to work at maximum speed, 150MHz.

Using a lower speed results in a lower consume of energy but the time critical and calculation power exigencies of this project should not allow using a lower clock frequency.

The calculation in the frequency decay algorithm uses lots of available calculation power in the CPU as well as RMS calculations. Using a lower speed could result in inaccurate frequency measurements in the case that the next frequency interruption is called before the previous one finish its execution.

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3.1.4. DSC Periphery Description This DSC has several peripheries but not all of them are used. In the following

sections, the peripheries used in this project are described.

3.1.4.1. Event Manager

The event manager will be the periphery entrusted with the frequency

measurement. The DSC counts with two Event Manager Modules. The event-manager (EV) modules include general-purpose (GP) timers, full-

compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. Every EV module count with two GP timers and three capture units.

The two EV modules are similar, EVA and EVB. EVA and EVB functions, timers, compare units, capture units and so on are

identical. Event managers A and B have similar peripheral register sets except for different

addressing. The capture unit need to be associated with a GP timer within the same module,

the associated timer is used as time base of the capture unit. The capture units can use any of the EV timers with the only restriction that the capture units 2 and 3 must use the same timer as time base.

The load controller uses two timers, one of each EV module and the capture unit 1

of the EV module A (EVA). One GP timer is used to control the ADC sample rate, this timer is also used to

increase the real-time stamp. The capture unit also uses another timer in the measurement of the power grid

signal period. More information about the timers usage can be found in following sections.

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Figure 3-III - Event Manager A Functional Block Diagram

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57

3.1.4.1.1. GP timers Each Event Manager (EV) has two General Purpose timers. These timers can be

used for any purpose. They are not reserved for DSC internal functions. Every timer has individual configurations registers, so that it can be used for

different purposes at the same time. In this project, it is used one timer in frequency measurement. It is used as time

base of the capture unit. It will be explained in the section 3.1.4.1.2 Capture unit. Another timer is in charge of the ADC sample. It will be explained in section

3.1.4.1.3 Starting the A/D Converter with a Timer Event, this last timer is also used in the real-time stamp, explained in section 2.6 Real-time stamp.

3.1.4.1.2. Capture unit This is a module of the event manager that reacts with external events. It is configurable to detect any change in its inputs. The capture module is configured to detect rising edges in its inputs. It has

Schmitt-triggered inputs, so that, when connecting the voltage signal with the input, the corresponding interruption subroutine is called every power grid cycle.

This module basically starts the associated general purpose counter used as time

base and in every rising-edge, it stores the value of the timer in a register and throws an interruption. When the timer overflows the count starts at zero again.

In the interruption subroutine (capture1_srt()) the program reads the registers where the last two measures are stored, by subtracting them the period of the input signal is obtained.

The Timer speed is directly related with frequency accuracy. The faster runs the

timer the better accuracy is obtained. If the timer counter is increase at too much speed, the counter that measures the frequency can be overflowed within two zero-crossings and the measurements would be wrong. The frequency measurement process deeply explained in section 0


Frequency measurement.

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3.1.4.1.3. Starting the A/D Converter with a Timer Event The event manager can be used to control the sample rate of the ADC. It is possible to configure a Timer to define the period of sampling. The ADC has four special registers called sequence registers, in this registers is

stored the sequence of inputs measured. In this project EV is configured to react with timer 1 period interruption. This

interruption is generated every 1 millisecond, when the timer count is equal to its compare register. This results in a sample rate of 1kHz, therefore, it samples the input twenty times per cycle.

3.1.4.2. ADC

The ADC module has 16 channels, configurable as two independent 8-channel

modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure

3-IV - ADC block diagram shows the block diagram of the F2812 ADC module. The two 8-channel modules have the capability to auto sequence a series of

conversions; each module has the choice of selecting any one of the respective eight channels available through an analog MUX. The two 8-channel modules can be configured in a simultaneous sample mode, where the pairs of inputs (one of each 8-channel module) can be sampled at the same time.

On each sequencer, once the conversion is complete, the selected channel value is

stored in its respective ADCRESULT register (ADCRESULT1, ADCRESULT2…). In the project the sequencers are set to measure the instant current and voltage simultaneously two times. The result used is the average of the two measurements, this over sampling will increase the SNR of the meassurments.

Although the ADC only has one ADC converter it is possible to sample dual

channels using the sample and hold circuit. This circuit samples the channels at exactly the same time and keeps the value until the single ADC converter converts both of the channels. This circuit is necessary in order to have instantaneous measures of current and voltage.

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Figure 3-IV - ADC block diagram

Below is a detailed list of the ADC module features:

12-bit ADC core with built-in dual sample-and-hold (S/H)

Simultaneous sampling or sequential sampling modes

Analog input: 0 V to 3 V

Fast conversion time runs at 25 MHz, ADC clock, or 12.5 MSPS

16-channel, multiplexed inputs

Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion

can be programmed to select any 1 of 16 input channels

Sequencer can be operated as two independent 8-state sequencers or as one large 16-state

sequencer (i.e., two cascaded 8-state sequencers)

Sixteen result registers (individually addressable) to store conversion values

Multiple triggers as sources for the start-of-conversion (SOC) sequence

S/W − software immediate start

EVA − Event manager A (multiple event sources within EVA)

EVB − Event manager B (multiple event sources within EVB)

External pin

Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other

EOS

Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to

Synchronize conversions

EVA and EVB triggers can operate independently in dual-sequencer mode

Sample-and-hold (S/H) acquisition time window has separate prescale control

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Figure 3-V – ADC example Voltage output

The figure above shows the output of the ADC in the voltage channel and the

respective offset. The offset is fixed to the value measured in absence of other input signal. The ADC output is a series of integer values between 0 and 4096. The integer value corresponds with the range from 0 to 3 volts. The integer results are convertible to voltages present at ADC input with the following equation.

PcZ- 0 JcZ-S[V@]k[ N EE,OAL D :X>YC FPI (3.1)

ADCmeasure represents the value returned by the ADC, in instance of the voltage

channel, the OFFSET has the value of 1921. A similar equation can be used to obtain the current at the input of the current

ADC channel.

zcZ- 0 JcZ-S[V@]k[ N EE,OAL D :X>YC D h FPI (3.2)

0

500

1000

1500

2000

2500

3000

3500

4000

1 8

15

22

29

36

43

50

57

64

71

78

85

92

99

AD

C o

utp

ut

(in

teg

er

Un

its)

Number of sample

Input Voltage

Input Voltage

Offset

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As well as in the previous equation, ADCmeasure represents the value returned by the ADC, in the case of current, the OFFSET has the value of 1904. The R in the denominator represents the resistance of the resistor connected to the current transformer. The ADC is only be able to measure the voltage, so that, the ADC measures the voltage dropped in a know resistor, being direct to obtain the current thought it. It is used a 10Ω resistor.

The OFFSET is the integer value corresponding to the level shifter input. This

offset is added in order to sample the input signal that varies from negative to positive values. The ADC is only able to work with positive signals.

The offset cannot be measured every signal measurement, that is because the level

shifter inverts the input signals, so that, the offset is regulated to the invert value. In order to improve the accuracy of the measurements, the offset could be

measured every time the signal is sampled. The offset should be obtained from the level-shifter reference input but it has to be inverted, due to the stability of the offset reference value and the fact that the offset has to be inverted, it is used a fixed offset value. There are more details about the level shifter in section 3.2.1.3 Level shifter.

3.1.4.3. General purpose I/O

Most of the periphery pins are configurable to be used as a General purpose

input/output (GPIO). In this project, one pin is used as I/O. This pin controls the relay that will disconnect or reconnect the load. It could be possible to use more than one pin in the case that more reactions were needed against a frequency event. There is more details about the General purpose Inputs/outputs in section 4.3.3.2.3 GPIO

configuration.

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3.2. Board Description The load controller needs some special hardware specially designed to achieve its

purposes. The included hardware in the DSC developing board (more details in 3.2.4

eZDSP F2812) is not enough. It only has RAM memory connected to the on-chip external memory interface, direct connections with the chip pins, the PC connection (thought JTAG port) and the usual ADC external reference hardware (two capacitors).

The load controller has to measure the frequency and the power of the power grid.

The wall outlet output has to be transformed in order to be measured. First of all the AC power grid at 230V cannot be connected to the 3V inputs of the

microcontroller’s ADC. It is needed to reduce the voltage to the allowed range. The DSC has only ADCs that convert voltage to digital values but in order to

calculate the power we also need to know the Current. Therefore, a current to voltage converter is required. It has as well to be reduced to a compatible range.

The power grid is affected by noise, external interferences, and also by harmonics.

In order to obtain the cleanest possible measurements the input signal must be filtered. Once the input signal is reduced and filtered, It has to be adapted to the DSC

voltage input range. The input signal varies between positive and negative values. The DSC, and in consequence the ADC, only works with voltages between 0 and 3 Volts, so it is also needed to shift the signal to only positive values. It is done by adding to the input signal and offset that centers it in the middle of the ADC range.

Regarding to the power supply, all parts of this hardware need to be powered so

that, a single positive power supply for the DSC and a double power supply for the filters are included in this board.

Figure 3-VI - Board distribution

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3.2.1. Signal interfacing and conditioning This section it is describes how the signal coming from the power grid is

conditioned in order to obtain a proper signal for the DSC hardware.

3.2.1.1. Measurement transformers

These transformers are in charge of reducing the power grid signal at 230V to a

range that can be used by the microcontroller. These transformers have lots of repercussion in the final measures. Therefore,

high-precision transformers are used at this point.

Figure 3-VII - Measuring Transformers

The voltage Transformer is a high-precision toroidal transformer. It has a

conversion ratio of 325:1.65, its gain is fixed and cannot be changed. It gain is calculated in the following equation (3.3):

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64

yx= 0 :12<, C2 0 >, >>2 FP/PI (3.3)

The current transformer ratio is variable, the installed transformer has 50 loops in

the primary coil and the ratio can be change according to the number of loops thought the transformer.

The gain of the current transformer is the following (3.4) :

y^= 0 K2> Fc/cI (3.4)

Where N represents the number of loops thought the primary coil.

The number of loops cannot be set arbitrary. The current at the ADC input cannot have amplitude higher than 150mA. Higher amplitude causes voltages with amplitude higher than 1.5V which saturates the range of the ADC.

In order to measure the test load (A heater) it is used two loops. Therefore the

current transformer ratio is 50:2 which results in this special case in a current gain of: .

y^= 0 K2>Kl1 0 12> 0 >, >X Fc/cI (3.5)

The gain of the transformers is calibrated in the last stage of the signal

conditioning hardware, the level shifters, it is explained in section 3.2.1.3 Level shifter.

3.2.1.2. Analog filters

The power grid signal is affected by noise and harmonics. In order to obtain

accurate measurements active analog filters are used. In both of the channels, voltage and current, it is used butterworth second order

filters. The signals outside the working band will be reduced 40dB per decade, the signal inside the band is not affected, it has a gain of 0dB.

The measurement band is centered in 50Hz and has a band-width of 1Hz. This

band is too small to be implemented with real components without compromise other

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filter characteristic like the phase spread. Therefore, it is used a real pass-band filter with a band-width of 20 Hz. It fulfills the purposes of the project because it sufficiently reduces the noise outside the working band and the first harmonic at 100Hz.

Figure 3-VIII - Filter transfer function

In the figure above it is show the transfer function of the filters, it is a second

order filter so it has a gain of -40dB/decade outside the pass band. The band-width is exactly 20.96 Hz at -3dB. The label at 100Hz corresponds to the first harmonic, that it is reduced in -22.46dB.

Figure 3-IX – Filter photo

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The scheme of the filters is the following:

Figure 3-X- Filter Scheme

3.2.1.3. Level shifter

The level shifter is the last stage of the signal conditioning hardware. The ADC of the DSC works with voltages between 0 and 3 Volts but the signals

at the output of filters is in the range of ±1.5 Volts. The level shifter consists on one Operational Amplifier (OA) in the configuration

of an inverter mixer, whose inputs are connected with the voltage or current signal and with the offset reference.

The level shifter has to add an offset of 1.5 Volts. This offset centers the signal in

1,5Volts and removes the negative voltages. Due to the inverter configuration, the offset reference has a value of -1,5V which is converted to 1,5V at the level shifter output.

The level shifters is as well used as gain stage (The filter stage has no gain in the

working band). The gain of the level shifters is calibrated to expand as much as possible the input

signals into the ADC input range. Therefore, in the voltage channel the level shifter is calibrated to output the power

grid signal with 3 Volts in peak-to-peak and with a DC offset of 1.5 Volts.

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The current channel calibration cannot be done without knowing the controlled load, depending on the load the current amplitude can change. As seen in section 3.2.1.1

Measurement transformers the current signal range can be calibrated in the current transformer.

Figure 3-XI - Voltage level Shifter Scheme

The gain of the voltage level shifter is calculated with the followings equations:

yx@ 0 N h1h< 0 N <>> D <>:<<> D <>: 0 N>, Y `PPa (3.6)

It is also added an offset of -1,5V Offset, with a gain of -1. Finally the transfer

function of this level shifter is the following: 0 N>, Y D <, 2 FI

(3.7)

The current channel is similar in exception of the resistor R1. It can be observed

in the following scheme.

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Figure 3-XII - Current Level Shifter Scheme

The gain of the current level shifter is calculated using the following equation:

y^@ 0 N h1h< 0 N <>> D <>::<< D <>: 0 N>, :1 `PPa (3.8)

Note that the units of this gain are [V/V] because at this point the current is yet

converted to voltage.

As well as in the voltage channel it is added an offset of -1,5V Offset, with a gain of -1. Finally the transfer function of this level shifter is the following:

P 0 N>, : D PT <, 2 FPI

(3.9)

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Figure 3-XIII - Level shifter result

The input signal inversion do not affect in the final calculations, the RMS

calculations uses the square of the ADC samples, therefore, a change of sign is not representative.

3.2.2. Current and voltage values at load controller inputs

Section 3.1.4.2 ADC described how to obtain the values of current and voltage in

the ADC inputs but these values are not the same as the values present in the power grid.

This section describes how to obtain the values at the wall outlet the values

acquired by the ADC. In order to know the real values is needed to consider the voltage and current

transformers, as well as the gain of the level shifter. Considering them, the current and voltage in the load controller inputs can be obtained with theses equations:

P 0 PcZ- D <yx 0 PcZ- D C2>: (3.10)

Where gv is the total gain of the voltage channel:

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yx 0 yx= D yx@ 0 >. >>2 D >. Y< 0 >, >>XC `PPa 0 :C2> (3.11)

Where gvt is the total gain of the voltage transformer (3.2.1.1 Measurement

transformers), and gvls (equation (3.3)) is the total gain of the voltage level shifter. The instant peak-to-peak power grid amplitude is 650 V and the 3V is the peak-to-

peak amplitude in the ADC input. The level shifter gain is calibrated to obtain a 3V peak-to-peak signal from the

transformer output that has a fixed transfer ratio. The voltage don’t depend on the load, therefore the equation above is suitable

with any load. The current calculations are similar to the voltage calculations. The equation for

obtaining the current at the load controller inputs is the following:

z 0 zcZ- D <y^ (3.12)

Where gc is the total gain of the current channel, the current measured depends on

the load connected with the load controller inputs. The current transformer gain can be configured according to the load connected.

y^ 0 y^= D y^@ `PPa (3.13)

Where gct is the total gain of the current transformer, and gcls the total gain of the

current level shifter.. The total gain in the current channel in the particular case of the test load, two

loops through the primary coil, is the following:

y^ 0 y^= D y^@ 0 >. >X D >. : 0 >, ><1 PP (3.14)

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3.2.3. Power Supply The board has two different powers supplies. A 5 Volts power supply to power

the DSC and a double ±5Volts power supply to power the filters and the signal drivers. It is used two power supplies because the power supply used in the filters introduces interferences in the DSC which needs s supply as stable as possible.

The energy is obtained from the power grid but the output of this power supplies will not be used to measure the frequency or the power of the line. These supplies are used only to power the system.

It is used a simple power supply based on a bridge rectifier and on a voltage regulator.

In the Figure 3-XIV - Single power supply scheme it is show the scheme of a single power supply. The double power supply will be exactly the same with exception on the voltage regulator that will be a negative voltage regulator (LM7905). A detailed scheme of both of the power supplies can be found in annex B Board Schemes.

In the rest of this section it is explained the function of the power supply. In the Figure 3-XIV, which is below this paragraph, the letters from A to D

represents voltage measurers or oscilloscopes and in following figures the measurements at these points is showed.

Figure 3-XIV - Single power supply scheme

At point A its present a typical sinusoidal signal at 230 Volts (RMS) from the

power grid. In point B it is found the signal with the voltage reduced, its amplitude is around

10Volts. The output of the transformer is connected with a bridge rectifier (DB101G). This

component is composed of 4 diodes that invert the negative part of the signal. The output result, at point C, without connecting anything more is the following.

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Figure 3-XV - Measure at the bridge output, point C (Without capacitors)

At this point the power supply offers only positive voltages, but it is not the

constant value in a DC power supply. In order to “fill up” the valleys it is used two capacitors in parallel, they works as a very low low-pass filter. The results of at this point, point C with the capacitors installed ,can be watch at next figure, in the magenta plot.

Figure 3-XVI – Power supply output

As observed in the graphic above the output starts to be similar to a DC power supply but the curl is too much big to be useable (magenta plot).

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In order to reduce this curl we used a voltage regulator. This component “cuts” the input signal to a fixed value, the regulator used regulates to the voltage to 5V (cyan plot). It consumes the excess voltage, so it gets warm and sometimes is needed a heat sink.

Finally it is used a capacitor in order to stabilize the DC level with the ground. The double power supply is similar to the single one, in exception that it uses each

transformer output for each voltage level. It also uses other voltage regulator (LM7905C) for the negative output that regulates the voltage to -5 Volts.

Figure 3-XVII - Double Power Supply scheme

3.2.4. eZDSP F2812 In order to start the prototyping of any hardware based on the DSC F2812 it is

used the developing board eZdsp manufactured by Spectrum digital. The developing board is a board with the DSC integrated and the minimum

additional hardware needed to develop any project. Te hardware included in eZdsp is the following:

• One tms32F2812 DSC

• PC parallel communications port, This port is used to connect the device to the PC, thought this port the programs are loaded into the DSC memory. It is also possible to control the execution and watch the contents of the memory in real time in order to debug the developed software

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• 64Kx16 of extra external RAM. The board has this memory attached to the external memory interface, it is used to extend the code and data memory.

• ADC analog interface, This port is used to connect the external reference of ADC and the inputs to sample, the board also includes the extra hardware needed in the case of using the internal reference.

• I/O interface, This port are the friendly pins connected with the on-chip DSC peripheries, these pins are multiplexed with the GPIO pins.

eZdsp is fully supported by the IDE developed by Texas instruments, which is included in the developing board kit, as a reduced version only functional with this DSC.

Figure 3-XVIII - eZdsp F2812 photo

More details can be found in the technical reference provided by Spectrum digital.

The reference can be found in the Bibliography section

75

4 SOFTWARE

This section describes all the software process. Once the hardware is designed this

is next step in the load controller development, where the processor is programmed to carry out its duty.

This section uses two different types of font styles. The regular type, Times new

Roman, used in regular text, and console type used in source code Example source code text

4.1. IDE The Integrated Development Environment (IDE) is the software installed in the

PC that allows the user to develop, debug and load a program into the DSC. The quality of the IDE is decisive in order to obtain a good quality program. The IDE used in this project is Code Composer Studio (CCS) which is included in

the developing board. This IDE is one of the best IDEs in the market. The provided CCS has the only

limitation that it can only be used with the included DSC. It cannot be used with other DSC, DSP or microcontroller.

The IDE has all the featured usually present in a microcontroller environment. It has a text editor with a syntax coloring engine. It manages all the source code

and header files. The IDE is able to compile and link the code and obtain output binary program

that is loaded into the DSC.

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The IDE also provides the user debug functions like the possibility of adding software beaks and follow the execution step by step, as well as watch the values stored in any memory location at any time.

4.2. User Manual This section contains the basics to use the CCS IDE, for more details it should be

referred to the CCS included tutorial. The first step is opening the application. The main window looks like this:

Figure 4-I - Code Composer Studio main window

It has the look-and-feel as most of the applications available under Windows

operative system. In this brief tutorial it is supposed that the user is familiarized with the Windows operative system.

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4.2.1. Developing board connection It is not needed to change any configuration in Windows neither in CCS. It has to be connected the parallel port wire from the ezDSP board to the PC

parallel input and finally it is needed to connect the power socket to the power grid. Once all the connections are done it hast to connect the CCS with the board. It is

done by clicking the option Debug->Connect in the main window.

Figure 4-II – Connect

If the connection succeeds The picture of a socket in the bottom left corner goes from red to green, it appears a balloon message advising that the connection is done and it appears a new window that shows the current contents of the DSC memory.

Figure 4-III - Board connected message

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4.2.2. The project All the CCS developments are formed by a CCS project. The CCS project is folder that contains a file with the extension .pjt, this file

contains all the IDE configurations made for the development, as well as the location of all the other files included in the project.

These files should be located in the same folder where the pjt file is located.

Otherwise it should be possible to miss files if the application is ported to other computer.

In the menu Project->Open… is possible to open a existing project, it can be

selected new… to create a new one.

Figure 4-IV - Open existing project

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When the open option is selected it appears a regular opening windows dialog.

Figure 4-V - Open Project dialog

It has to be selected the .pjt file, after clicking the Open button (Abrir) the project

is open and the main window changes.

Figure 4-VI - Opened project

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The File view tab shows all the files involved in the load controller development. By double clicking any file it is opened to be modified.

For example if it is double-clicked the main source code file proyectoMain.c it is

showed on the right part of main window.

Figure 4-VII - Main file source Code

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4.2.3. Configurations The general, compiler and linker configurations can be changed in the build menu.

For example the following figure shows the linker configuration window.

Figure 4-VIII - Linker configuration

It is possible to have simultaneous profiles with different configurations.

Figure 4-IX – Select Configurationt

It is possible to create a new profile in the project menu option configurations…. More details about the configuration can be found in the CCS included tutorial.

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4.2.4. Modify, build and load a project If it is desired to modify the source code of any file it has to be opened as

explained in the previous version. Once the changes are made the files have to be build in order to be loaded into the DSC memory.

Figure 4-X - Build a project

This option compiles all the files modified, if wanted it is possible to rebuild all

the files modified or not by clicking on rebuild all. After clicking the build option it is showed a report of the building on the botton

part of the main window.

Figure 4-XI - Build report

If the compilation ends without any problem the report should look like the figure above. Once the project is correctly compiled the next step is to load it into the DSC memory in order be executed.

The program is loaded by clicking on the menu option Load Program inside the

menu File.

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Figure 4-XII - Load Program

It appears a dialog similar to the open project one. In this dialog it has to be selected the file .out contained in the folder debug that is inside the main folder, where the pjt file is contained.

The debug folder corresponds to the output generated by the configuration named

debug, it is possible to create various configurations and use any of them at any time. In this project it is only used one configuration.

Figure 4-XIII - Load project output

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Once the building output is loaded one time, it is possible to reload it bypassing the open dialog, the project could be modified and rebuilding and the reload option will reload the last built project.

Figure 4-XIV - Reload Project

The loading process is the last step to run a program, if the loading process finish successfully the program can be run.

A loaded program is run by pressing the option run in the menu debug.

The execution of a program is stopped by clicking on the option halt, also in the

menu debug. It is not possible to reload a program while a program is running.

Figure 4-XVRun a program

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4.2.5. Debug project The IDE CCS offers lots of debug tools. One of the tools is the watch window, by right-clicking on any variable in the

source code and selecting the option add to watch window… it is possible to watch the contents of the variables in real time.

Figure 4-XVI - watch window

Other typical debug tool is the control of execution, CCS offers the possibility to

set software and hardware break points, the execution stops in these points and can be controlled.

For example it is possible to run to the next break point, execute just one

assembler instruction or one c instruction.

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A software break point can be easily set by double-clicking on the left of any line of code. It can be watch in the next figure, where the red circle is the break point and the yellow arrow is the point of execution.

Figure 4-XVII - Break point

4.2.6. Gel File The CCS has the possibility to be programmed and personalized madding use of

the programming language GEL. It is possible to load a GEL file in CCS, only one for all the projects opened, but

in can be changed at any time.

Figure 4-XVIII - GEL file

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A possible personalization is the possibility to add a options menu with personalized actions.

Figure 4-XIX - GEL Menu

In this project the GEL file has been modified to add in the watch window the

relevant variables and arrays every time the program is loaded.

Figure 4-XX - Example code of GEL language

It is encouraged do the getting started tutorial included in the CCS help center.

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4.3. The load controller program This section describes the structure of the files that compound the project and the

relevant source code.

4.3.1. File structure A project developed with CCS is form by many files all of them grouped in a CCS

(Code Composer Studio) project. The project root folder contains six files and four folders, not all of them are

relevant in the project, some of them are automatically generated in the compilation process and they are logging files or temporal files. his section only describes the relevant files used in the project.

The project root folder contains the following files:

alex_project.pjt

This is the CCS main project file. It stores the configuration of the compiler and linker, as well as the list of the files that compound the project. This file is essential in order to work with the IDE.

proyectoMain.c

This file contains the most of the source code of the project. It is deeply described in following sections.

The other files in the root folder are automatically generated by the IDE. One of

them contents information about the CPU (alex_project.sbl). The IDE uses it to generate the specific assembler code for the CPU.

Other file contains temporal information about the project loaded

(alex_project.paf2), It allows the IDE not to phrase the project file every time a change is made, only when opening an saving the project.

The other files with the extension “log” are loggings about the internal process of the compiler. The root folder contains the following three folders:

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Debug This folder contains the output files of the compiler, binary code generated from

the source code. The content of this file is the program that is loaded into the DSC memory.

DSP281x_common and DSP281x_headers These folders contain the files provided by Texas instruments needed to develop a

program for the DSC. They contain the CPU initialization subroutines and the registers structures. The register structures relates the register memory address with user-friendly names which allows the user not to use the memory address when writing of reading a register, only the mnemonic assigned names.

alex_project.CS_ This folder is a temporal automatically generated folder. It is used by the IDE in

internal process, for example, to store the CPU variables that are wanted to be showed in the screen.

4.3.2. Memory mapping The memory available is scarce. Although this DSC has the possibility of use

flash memory it is only used the RAM memory. In order to use the flash memory a JTAG emulator is needed. However, in the

developing of this prototype the RAM memory is enough.to archive the prototype purposes.

There are two different types of RAM, the integrated in the DSC core and the

external RAM included in the eZDSP board (developing board). The RAM has to be shared between data and code, due to the DSC Harvard

structure. The memory mapping has to be made before the compilation and it is not possible

to change it after compilation. Memory mapping is defined in the command file

“F2812_EzDSP_RAM_Link.cmd”. It is stored inside the DSP281x_common folder, it has to be modified specifically for the project.

The main difference between the internal and external RAM is the speed. The

internal RAM is a single access RAM (SRAM), very fast, and the external RAM is slower, it uses several CPU cycles for a single access.

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The faster RAM is used to store time critical subroutines code, the other

subroutines and in the initialization process uses the external RAM. The appendix Memory mapping shows the code to distribute the memory. The memory mapping file is divided into two sections, MEMORY and

SECTIONS. The memory section defines the addresses and lengths of memories; it divides

physical memory into zones. The memory is divided in two pages; each page has different functions.

PAGE 0 is used to store the code of the program and de PAGE 1 to store the data.

The DSC has Harvard architecture and it has CODE and DATA moved a part. The second part of the memory mapping file is the SECTIONS part. In this part the sections of the program are defined and it is assigned a memory

zone to them. Any program has different memory sections, like the initialization code, the stack,

the user code and so on. It is possible to assign several sections to a single memory zone; the memory is

shared between all sections assigned to it. In the case that a memory zone has not enough memory for all sections designed

the program cannot be compiled. By default the initialization sections are assigned to external ram, they are

executed once and they are not time critical. The stack and other internal sections are allocated to internal RAM. These

sections will access to the memory very frequently and the location of these sections affects too much to the global speed.

The user code is assigned to external ram and user data to internal ram. There are some exceptions, user code has to be executed as fast as possible, in

instance of frequency measurement subroutine, is stored into the internal SRAM. In order to select where data of functions code are stored there are two special

compiler directives. Used to choose the memory section where a variable or a function is allocated. They are only used when it is needed to change the location of the function from the original section defined in the memory mapping file.

The directive to allocate the date in a desired section is:.

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#pragma DATA_SECTION(variable, ".section");

To allocate a specific function in a desired section it is used the directive:

#pragma CODE_SECTION(function, ".section");

The data directive can only allocate data within the data page sections and code

directive within code page sections. By default the user code is allocated in external ram which is slow. But there are

two time critical subroutines in the project, the one that measures the frequency and the one that samples de input signals. These subroutines are periodically executed in a short period of time, they have to be executed as fast as possible in order to avoid that the next execution of that subroutine were before the previous execution has finished. They

are allocated in the code section “ramfuncs” which is defined into the internal RAM memory zone.

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4.3.3. Program structure This section describes the structure of the program. The figure below shows the

program flow.

.

Figure 4-XXI - Simplified program flow

The start point is the red circle on the top of the figure, the programs stars its

execution at that point. The initialization of the load controller is done in the first lines of the main

function. The initialization process consists on configuring the peripheries implied in the functions of the load controller. It is done the initialization of the internal peripheries such as the PLL, the watchdog and ADC. Then they are filled up the ADC and EV configuration registers. The initialization process ends by setting up the interruption vectors of the ADC and EV interruption subroutines and enabling all the interruptions.

MAIN FUNCTION

Initialization process

Main loop

idle

If

Zero-

Crossi

ng

Capture1_isr

Frequency

measurement

Average calculation

RMS calculation

Create record

Threshold checking

If

ADC

ReadyADC_isr

Get ADC results

Store ADC results

Program start

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Once the initialization is finished the main function enters into an infinite loop without any function. At this point the program waits for the interruption events and calls the interruption subroutines. The most of the work it is done in the interruptions. Other functions are used in the program but they are not relevant in the program flow.

4.3.3.1. Headers

This section describes the header of the program. The headers define the library

inclusion, the special directives to map functions or variables to a specific part of memory, the definition of the function prototypes and the definition of constants and variables.

4.3.3.1.1. Inclusions The load control program includes three files.

#include "DSP281x_Device.h" // DSP281x Headerfile Include File

#include "DSP281x_Examples.h" // DSP281x Examples Include File

#include <math.h> //mathematical functions and constants

The first and the second file included are the libraries provided with the

microcontroller, these libraries contain the CPU initialization subroutines and the user-friendly names of registers as well as the interruption vector.

The last file is the mathematics library that is provided by the compiler. This librarie contains the mathematical function such as sin, cos, sqrt or constants as π or e.

4.3.3.1.2. Constant definition and Location of attributes As explained in section 4.3.2 Memory mapping, it is possible to map any data

structure or variable to the internal or external RAM depending on its time requirements. The mapping directives take place in this part of the header section. They are also defined in this part of the header the constant used in the rest of the program.

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According to the memory mapping, explained by the section 4.3.2 Memory

mapping, by default, the variables are allocated in the on-chip RAM. The directive

#pragma DATA_SECTION(variable_name,“memory_zone”)

allocates a variable or data structure to the specified zone of memory (in instance of memory zone “.extRAM” that is allocated in the external RAM memory).

The constants are defined with the directive

#define name value. In the compilation process the compiler replaces the constants names with its

value. frequency measurements constants : number of frequency measurements used in average #define AVERAGE_FREQUENCY_VALUES 25

Recover frequency threshold in integer units (Running at 25MHz) define DEFAULT_HIGHER_LIMIT 62525

Frequency event threshold in integer units (Running at 25MHz) #define DEFAULT_LOWER_LIMIT 62626

length of averaged frequency measurements array #define AVERAGE_MEASURES 5

Frequency decay filter constants:

Maximum allowable frequency change between frequency measurements.,150 integer units/cycle= 6Hz/s

#define MAXIMUN_FREQUENCY_CHANGE 150

frequency decay measurement constants: //square of FCF, It is needed in frequency decay calculations; it is defined with

one decimal value to specify that the number is a float number. #define FCF2 976562500000.0

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frequency decay event threshold #define DECAY_THRESHOLD -0.16

number of decay measurements used in the average #define AVERAGE_MEASURES 5

RMS constants: Number of samples used in RMS calculations

#define ADC_MEASURES_PER_CYCLE 40

Offset present in current and voltage channels.

#define VOLTAGE_OFFSET 1904

#define CURRENT_OFFSET 1904

Realy constants:

The different load controller states are the following: 0=OPEN CIRCUIT 1=CLOSED CIRCUIT 2=WAITING FOR

RECONNECTION

Define the initial state #define DEFAULT_RELAY_STATUS 0x1

Define the states.

#define OPEN 0x0 //relay status

#define CLOSE 0x1 //relay status

#define WAIT 0x2 //relay status

Define the maximum time to re-attachment power line cycles.

1500*0.02s=30s

#define MAXIMUN_WAIT_TO_ATTACHMENT 1500

Control logic type II Constants

Kf value in Control logic type II equation #define KF 1

Nominal frequency in Nordic systme, integer units, 50Hz #define FO 62500

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Data recording constants: This constant defines the number of records stored in external memory simulating

the external memory #define STUB_EXT_MEMORY_LEGTH 50 The value of these constants cannot be changed once the program is compiled.

The constants are named by collective agreement in uppercase letters, it makes easy to distinguish them from variables. Some of the values that could be changed in running time are stored in the initialization process in a variable, from that point it can be modified while the program is running. These constants define the initial configuration of the load controller. As it is explained in the chapter future work, it should be better to define these values in the external flash memory that it is not erased if the hardware is powered down, and if they are modified the modifications remains after a reboot.

4.3.3.1.3. Functions definition This part of the header defines the prototypes of the functions. It also allocates

some functions to and specified part of memory. As default the functions are allocated in the external RAM memory, which is slower than the internal memory.

Using the directive:

#pragma CODE_SECTION(name_of_function, memory_zone);

it is possible to allocate the time critical into the faster internal RAM, in instace of code section “ramfuncs” that is allocated in the internal ram.

As in the data allocation directive, the memory zone must be defined in the memory mapping file and it must to be in the code page.

/*** frequency measurement functions ***/

//definition of the interruption subroutine of capture unit 1

//and allocation in internal RAM

interrupt void Capture1_isr(void);

#pragma CODE_SECTION(Capture1_isr, "ramfuncs");

/*** data acquisition functions ***/

//definition of the interruption subroutine of ADC


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interrupt void adc_isr(void);

#pragma CODE_SECTION(adc_isr, "ramfuncs");

/*** relay control functions ***/

void close_relay(void);

//opens the load relay

void open_relay(void);

//closes the load relay

//sets the frequency recover threshold

void set_higher_limit(unsigned int);

//sets the frequency event threshold

void set_lower_limit(unsigned int);

/*** time stamp ***/

//synchronizes the real time counter

void time_synchronization(long);

/*** decay functions ***/

//sets the frequency decay threshold

void set_decay_limit(float);

Control logic type II function. This function changes the temperature set points. void set_points_update(unsigned int,unsigned int);

/*** storing stub ***/

//Function that should store the recors in external memory

void recod(long time,unsigned int period,unsigned int voltage,unsigned

int current,unsigned long power, float decay,short relay);

The functions are defined in the same way as is done in ANSI C. First of all it is

defined the type of value that the function returns (void means nothing), next it is defined the name of the function, and finally, in brackets, the parameters and its types. All the functions are explained in following sections.

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4.3.3.1.4. Variables definition This part of the header defines the variables of the project. All the variables and

arrays in C have to be defined before being used. In this part of the header it is assigned the type (short, integer, unsigned integer…) to the attributes and if necessary, some of them are initialized to a specified value.

//generic variables

short i; //generic index

short j; //generic index

/*** frequency measurement ***/

// Temp integers variables in capture unit subroutine

unsigned int temp1_1;


[…]

//table of average frequency measurements

unsigned int average_measures[AVERAGE_MEASURES];

//index used in frequency measurement array

unsigned int measure_index=0;

unsigned int average_measure; //average period measure

/*** Frequency decay measurement ***/

//table of frequency decay measurements

float decay[AVERAGE_MEASURES];

//last frequency decay measurement

float average_decay=0;

//frequency decay threshold definition and initialization

float decay_limit= DECAY_THRESHOLD;

/*** relay control ***/

//frequency recover threshold initialization

unsigned int higher_limit=DEFAULT_HIGHER_LIMIT;

[…]

/*** data adquisition ***/

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//ADC current measures without offset

unsigned int adc_samples_current[ADC_MEASURES_PER_CYCLE];

[…]

/*** RMS calculations ***/

//square of ADC measures in RMS calculations

unsigned long adc_square_current[ADC_MEASURES_PER_CYCLE];

unsigned long adc_square_voltage[ADC_MEASURES_PER_CYCLE];

[…]

unsigned int voltage_RMS; //voltage RMS calculation result

[…]

//temporal variables in RMS calculations

long temp_results;

long temp2_1;

[…]

/*** Time stamp ***/

//time variable definition and initialization

long current_time=0;

/*** external memory stub ***/

unsigned int ext_index=0;

[…]

short ext_relay[STUB_EXT_MEMORY_LEGTH];

//relay s.

Not all the variables and arrays used are showed in the piece of code above, the whole variable definition section can be found in the appendix A.1 Main program

source code.

4.3.3.2. Device initialization

The main function is the first function executed by the DSC. This function does

the initialization task. Once time the control device is initialized the main function ends and all the actions are done by the interruption subroutines.

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This section describes the functions and the registers that are involved in the initialization process.

Some of the registers used in the initialization are ELLAOW protected registers. The directives ELLAOW and EDIS are used to write in protected registers. The EALLOW protected registers are protected against spurious writes after configuration. It can only be modified between these two directives.

These directives are ignored in the description of the code in the following sections.

4.3.3.2.1. System Control Initialization

InitSysCtrl(); // Init the system control

This function initializes the system control. This function is provided by Texas Instruments. This function initializes the internal peripheries, the PLL, peripheral clocks and so on.

The PLL sets the speed of the CPU . It is initialized with the default speed of 150Mhz.

4.3.3.2.2. Peripheral High speed clock configuration

This code configures the speed of the High Speed Clock (HSCLK). The peripheries are clocks are fed by this global clock, subsequently the peripheries uses a prescaler to adapt the speed to its requirements.

//set HSPCLK to SYSCLKOUT / 6 (25Mhz assuming 150Mhz SYSCLKOUT)

EALLOW;

SysCtrlRegs.HISPCP.all = 0x3; // HSPCLK = SYSCLKOUT/6

EDIS;

The configuration of the HSCLK is done by setting up the prescaler applied to the

main clock , SYSCKOUT, that runs at 150Hz. It is set to obtain the clock frequency of 25MHz that is the maximum that the peripheries support.

The register of the High speed peripheries prescaler (HISPCP) is EALLOW

protected.

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4.3.3.2.3. GPIO configuration The next code sets up the DSC pins that are used as General purpose Input/Output

(GPIO). The GPIO multiplexer registers are EALLOW protected.

EALLOW; // Enable write protected registers

GpioMuxRegs.GPAMUX.bit.CAP1Q1_GPIOA8 = 1; // Sets pin as Caputure unit

GpioMuxRegs.GPFMUX.bit.MCLKXA_GPIOF8=0x0; //sets as I/O

GpioMuxRegs.GPFDIR.bit.GPIOF8 = 0x1; //sets as output

EDIS; // Disables write protected registers modification

Most of the DSC GPIO pins are multiplexed with peripheries. By default the pins are used by the peripheries. The pins of a periphery which is not used can be used as GPIO. Each periphery has a register associated where is possible to set the pins are GPIOs or as periphery pin, it is also possible to chose the direction of the GPIO pins.

The first line, ignoring the directives, sets the first pin of the capture unit to work

as the capture input. It is configured in the capture unit GPIO register number 8. The second line sets the pin, which is going to be used to control the load relay, as

a general purpose IO. It is set in the register of the McBSP, this periphery is not used in the project, that is because their pins are used as GPIO.

The last line specifies the direction of the GPIO. It sets the pin as an output.

4.3.3.2.4. PIE initialization The next directive disables all interruptions. The initialization process is not

desired to be interrupted, particularly in the initialization of the PIE vectors.

// Disable CPU interrupts

DINT;

This function starts the interruption system.

// Initialize the PIE control registers to their default state.

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// The default state is all PIE interrupts disabled and flags

// are cleared.

InitPieCtrl();

The next step is clear all the interruption flags, it sets all the interruptions as

attended and cleared. They are also disabled all the interruptions individually.

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000; // Disables al interrputions

IFR = 0x0000; // Clear al interruption flags

Then it is initialized the vector table. It uses the default interruption subroutines even if they are not used.

// Initialize the PIE vector table with pointers to the shell

Interrupt

// Service Routines (ISR).

// This will populate the entire table, even if the interrupt

// is not used.

InitPieVectTable();

Finally they are set up the interruption vectors used in the load controller

program. The ADC vector is used for the sampling subroutine and the Capture

unit vector is used for the frequency measurement subroutine.

EALLOW; // This is needed to write to EALLOW protected register

PieVectTable.CAPINT1 = &Capture1_isr;// sets capture 1 unit interruption

routine as Capture1_isr

PieVectTable.ADCINT = &adc_isr; //sets adc_isr as interruption routine of ADC

EDIS; // This is needed to disable write to EALLOW protected registers

This piece of code stores the address of the interruption function in the interruption vector. Every time that the interruptions requirements are fulfill, it is called the function stored in its interruption vector.

4.3.3.2.5. ADC initialization The next initializes the ADC internals hardware, it is provided by Texas

Instruments

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InitAdc(); //init ADC.

The ADC measures buffer index is initialized to 0. ConversionCount = 0;

The next lines of code configure the ADC sequencer to sample only the desired channels.

Setup 3 conversions on SEQ1

AdcRegs.ADCMAXCONV.all = 0x0002;

Setup ADCINA0 & ADCINB0 as 1st SEQ1 conv. Current and voltage channels

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;

Setup ADCINA1 & ADCINB1 as 2n SEQ1 conv. Current and voltage, second sample


Setup ADCINA2 & ADCINB2 as 2n SEQ1 conv. Read User normal high and low.temperature


The next lines of code enables the event manager to start the ADC’s sequencer

one it is also enabled the interruption of the sequencer one. The end of sequence interruption calls the ADC interruption subroutine, the sampling subroutine, once al the conversions configured in the sequencer are done.

AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1 = 1; // Enable EVASOC to start SEQ1

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS)

The next line activates the simultaneous mode. Therefore the sample and hold circuits are activated and the pair of channels are sampled at the same time and held until both of the conversions are done.

AdcRegs.ADCTRL3.bit.SMODE_SEL = 1; //active the simultaneous mode in order

to measure current and voltage at the same time

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4.3.3.2.6. EV configuration, timers and capture unit First of all the general purpose timers configuration registers are cleared.

/* EVA GP timers configuration */

EvaRegs.GPTCONA.all = 0; // Clears configuration

The next lines configure the timer 1 that controls the ADC sample rate and real time stamp. /* Configures GP timer 1 with ADC sample rate */

EvaRegs.T1PR = 0x61A8; // Setup period register

The value of this register is 25000 in decimal base, the prescaler is disabled, so that, the timer runs at the High Speed periphery clock, at 25Mhz. The timer required to reach the count of 25000 takes 1 millisecond, which is the desired sample rate.

Enable timer to start ADC

EvaRegs.GPTCONA.bit.T1TOADC = 0x2; // Enable EVASOC in EVA

Finally the timer is configured in up-count mode and in compare mode. The compare mode allows the timer to generate an interruption when the count goes up to one millisecond. It is also disabled the prescaler.

EvaRegs.T1CON.all = 0x1040; // Enable timer 1 compare (upcount mode)

The next lines configure the timer 2. This timer is used as time base by the capture unit, this counter counts the time between zero-crossings. The frequency of the timer is set in order to not to be overflowed within two zero-crossing, as explained in previous sections.

Configures GP timer 2 with capture unit

EvaRegs.T2PR = 0xffff; // Sets timer periode

EvaRegs.T2CNT = 0x0000; // Conpare value,not needed

The next line sets the prescaler to 1/8, reducing the High speed periphery

clock to 3.125Mhz.

EvaRegs.T2CON.all = 0x1340; // Configures timer 2

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All the timers belonging to an EV module have some common configuration registers. The Global configuration of timers 1 and 2 is show in the next lines.

EvaRegs.CAPCONA.all = 0x0000; // Clears configuration

EvaRegs.CAPCONA.bit.CAP12EN = 1; // Enables capture 1 and 2 interruption

EvaRegs.CAPCONA.bit.CAP12TSEL = 0; // Chooses timer 2 as timer for capture

unit 1

EvaRegs.CAPCONA.bit.CAP1EDGE = 1; // Configures capture unit to detect rising

edges

EvaRegs.CAPFIFOA.all = 0x0000; // clears FIFO A

EvaRegs.CAP1FBOT = 0x0000; // clears capture 1 FIFO top

EvaRegs.CAP1FIFO = 0x0000; // clears capture 1 FIFO bottom

Configures interrptions of EVA

EvaRegs.EVAIFRC.all = 0xFFFF; // Sets capture unit 1 flags

EvaRegs.EVAIMRC.bit.CAP1INT = 1; // Enables captured unit 1 interruption

4.3.3.2.7. Relay initialization This piece of code sets the relay to the default status defined in the constant

section of source code.

//initialize Relay

if(relay_status==CLOSE)

close_relay();

else

open_relay();

4.3.3.2.8. Enable CPU interruptions The PIE block can support up to 96 peripheral interrupts. The 96 interrupts are

grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Therefore it is needed to enable the whole interruption line where the single interruption belongs.

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// Enable CAP1 in PIE

PieCtrlRegs.PIEIER3.bit.INTx5 = 1;

IER |= M_INT3; // Enable CPU Interrupt 3

The code above enables the individual interruption of the capture unit in the interruption group number 3 and activates the whole group in the CPU interruption register (IER).

// Enable ADCINT in PIE



The code above enables the individual interruption of the ADC in the group number 1 and activates the whole group in the CPU interruption register (IER).

EINT; // Enable Global interrupt INTM

ERTM; // Enable Global realtime interrupt DBGM

The groups where an interruption belongs cannot be changed. By default the lower number of group the higher priority has the interruption. Therefore, the ADC has more priority than the other subroutine as desired.

4.3.3.2.9. Average frequency buffer initialization This code initializes the frequency buffers to the initial values.

for(i=0;i<AVERAGE_FREQUENCY_VALUES;i++)

measures[i]=62500;

for(i=AVERAGE_MEASURES-1;i>0;i--)

average_measures[i]=62500;

average_decay = 0;

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4.3.4. Capture unit subroutine: Capture1_srt() This function is the interruption subroutine configured in the interruption vector

of the capture unit, therefore, it is going to be called when the capture unit requires it, every time it detects a rising edge.

This function does more task than frequency measurements, such as threshold checking and RMS calculation. Most of the code is already explained in previous sections.

The next lines of code reads the values stored in the capture unit FIFO, These

reads returns the time of the last and the previous zero-crossings.

temp1_1 = EvaRegs.CAP1FIFO; // Reads value in fifo stack


Once the values of last frequency measured are retrieved the frequency averaging is started.

Resets the measurement accumulator used in the average.

measures_addition=0;

Measurements are shifted to leave space for the new measurements, the and average calculation, the for loop is also used to add the previous measurements, the new one is added later.

for(i=AVERAGE_FREQUENCY_VALUES-1;i>0;i--)

measures[i]=measures[i-1];

//adds last instant measures except the last one.

measures_addition=measures_addition+measures[i];

Calculate the new measure checking if the capture unit had been overflowed.

//gets the last measure

if(temp1_2>temp1_1)

//No overflow

measures[0] = temp1_2 - temp1_1;

else

//overflow

measures[0] = temp1_2 +(0xffff- temp1_1);

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The next lines describe the frequency soft filter. It is described in section 2.1.3

Soft frequency filter.

if(measures[0]>average_measures[0] + MAXIMUN_FREQUENCY_CHANGE

|| measures[0]<average_measures[0] - MAXIMUN_FREQUENCY_CHANGE)

measures[0]=measures[1]; //duplicate previous measurement

The averaging calculation is continued after the frequency decay soft filter. The

adding of instant frequency measurements started some lines before in order to improve the efficiency of the code, avoiding two loops that use the same variables.

//adds the last measure

measures_addition=measures_addition+measures[0];

//calculates the average

average_measure= measures_addition/AVERAGE_FREQUENCY_VALUES;

Finally the table of average measures is shifted and the new value is inserted.

//Shift the average values array and insert the new one.


average_measures[i]=average_measures[i-1];

average_measures[0]=average_measure;

The next lines implements the decay measurement algorithm described in section

2.2 Frequency decay measurement.

The process of averaging is the same as the used in frequency measurement. First of all it is clear the average decay accumulator. Then the previous decays are shifted, the loop is also used for adding the decay measurements.

average_decay=0; //clear average decay addition


//freency decay shift

average_decay=average_decay+decay[i-1];

decay[i]= decay[i-1];

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It is calculated the frequency decay using the described equation in the frequency decay section. The only different is that the next line uses the square of FCF divided into one million and next multiplied by the same amount; it is done in order to avoid the integer rounding.

//frequency decay calculation

decay[0]= (FCF2/(float)((long)average_measures[0]*(long)average_measures[0]))

*(((float)average_measures[1]/(float)average_measures[0])-1);

Finally it is calculated the decay average adding the new decay measurement and

the decay accumulator.

//average_decay Calculation

average_decay=(average_decay+decay[0])/AVERAGE_DECAY_MEASURES;

//

The next lines calculates the RMS values, it is showed only the algorithm used to

calculate the voltage RMS, the code is exactly the same for current and power in exception of the input data tables used. The RMS algorithm uses the square measures calculated in the sampling subroutine. It is explained in the next section.

//RMS power voltage and current

//voltage

The accumulator is cleared temp_results=0;

Main loop, it adds all the square measures.

for(i=0;i<ADC_MEASURES_PER_CYCLE-1;i++)

temp_results=temp_results+adc_square_voltage[i];

The total adding is divided into the number of measurements used in RMS calculation. temp_results=temp_results/ADC_MEASURES_PER_CYCLE;

Finally it is stored in the respective result variable, this variable is passed to the record function, that simulates the external memory data recording.. voltage_RMS=sqrt( temp_results);

The result of this calculations gives RMS values in integer units used internally by the microcontroller, in section 2.5.3 RMS Current, voltage and power calculation it is described the process to convert this results into the international system of units (Volts,

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Amps or Watts). The other RMS calculations are done in a similar way in exception that is used the respective squared samples array.

The Control logic Type II Source code is very simple. Measures[0]

contains the last frequency measurement and T_high and T_low should contain the Normal temperature set points measurements. It is used the algorithm explained in section 2.4 Control logic Type II: Temperature Set points change.

T_high_out=T_high*KF*(measures[0] - FO);

T_low_out=T_low*KF*(measures[0] - FO);

Finally this interruption subroutine checks the frequency thresholds that implements the tripping criteria of control logic Type I..

If frequency is lower than the frequency threshold or the frequency decay is lower than the frequency decay threshold is considered that a frequency event has happened.

It has to be considered that the frequency checking are made comparing the period of the signal, therefore the frequency event happens when the measure is higher than the lower frequency limit.

if(average_measure > lower_limit || average_decay < decay_limit)

//there is a frequency event.

The relay is opened open_relay();

If the frequency and the decay is recover

else if(average_measure < higher_limit && average_decay > decay_limit)

//frequency event is recovered

It is set an initial random waiting time and the state is changed to waiting for attachment. In this state the relay remains opened, it is used to distinguish the open state when the frequency event is recovered or not.

if(relay_status == OPEN) //only The first time

It is set the new state and it is get the random waiting time measured in power grid cycles.

relay_status=WAIT;

waiting_cycles= temp1_2 % MAXIMUN_WAIT_TO_ATTACHMENT;

else

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If the load controller is in the waiting state it is subtracted one unit to the waiting counter.

//from the second time

waiting_cycles--;

If the waiting time ends it is closed the relay.

if(waiting_cycles <= 0)

//the waiting time is up.

close_relay();

else if(relay_status == WAIT)

If the frequency goes below the recover threshold and it is in the waiting state it is get a new waiting time.

// if frequency and frequency decay do not fulfill the event thresholds but

they don’t fulfils the recover criteria thresholds.


It is called the stub function that should store the record into the external memory

for subsequent sending.

recod(current_time,average_measure, voltage_RMS,current_RMS, power_RMS,

decay[0],relay_status);

The next line calls the function that should change the temperature set points, it is

passed the calculated high and low set points. set_points_update(T_high_out,T_low_out); Finally it is cleared the interruption in the capture unit and in the respective

acknowledge group. This prepares the interruption for the next executions.

EvaRegs.EVAIFRC.bit.CAP1INT = 1; // Clears capture unit 1 interruption flag

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; // PIE 3 ack

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4.3.5. ADC interruption subroutine: ADC_srt() This function gets the current and voltage measurements and calculates its squares

that are used in the RMS calculations. It also increases the real time stamp counter. First of all the function increments the real time counter

current_time++;

The next action retrieves the samples gotten by the ADC. If this function

is called, the ADC guaranties that the samples are ready in the results register. The

results are allocated in the set of registers AdcRegs.ADCRESULTn where n is the number of sample. The results are allocated according to the acquisition order. In this prototype are used the dual simultaneous sampling, in this case it is firstly stored the channel A which corresponds to the Current channel, and next the channel B which corresponds to the voltage. Once the signal channels are sampled they are sampled the offset channels, which are allocated in the next two result registers in the same way as the signal channels.

In the following lines it is used ConversionCount as index of arrays, this index in an integer variable that is incremented every execution of this function.

//Current measurements

adc_samples_current[ConversionCount] = ((AdcRegs.ADCRESULT0

>>4)+(AdcRegs.ADCRESULT2 >>4))/2-CURRENT_OFFSET;

////Voltage measurements

adc_samples_voltage[ConversionCount] = ((AdcRegs.ADCRESULT1

>>4)+(AdcRegs.ADCRESULT3 >>4))/2-VOLTAGE_OFFSET;

The pair of samples of each channel are added and divided into two, finally it is

subtracted the offset. The result of these subtractions is stored in the samples array, type integer, it is

not used an unsigned integer because the values varies from negative to positive values. The normal temperature set points are read from the ADC inputs, The load

controller assumes that the normal temperature set points are introduced thought the ADC but it could be done though any other way as the GP inputs.

T_high = AdcRegs.ADCRESULT4 >>4;

T_low = AdcRegs.ADCRESULT5 >>4;

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Now it is calculated the square values for the RMS calculations, it use long type

variables because the square of the maximum sample is higher than the maximum number represented by the integer type. It uses the measurements made in the previous lines of code.

adc_square_current[ConversionCount]=(long)adc_samples_current[ConversionCount

]*(long)adc_samples_current[ConversionCount];

adc_square_voltage[ConversionCount]=(long)adc_samples_voltage[ConversionCount

]*(long)adc_samples_voltage[ConversionCount];

adc_square_power[ConversionCount]=adc_square_current[ConversionCount]*adc_squ

are_voltage[ConversionCount];

If ADC_MEASURES_PER_CYCLE conversions have been logged, start over, where

ADC_MEASURES_PER_CYCLE is the selected amount of measures used for the RMS calculations in the constants definition.

if(ConversionCount == ADC_MEASURES_PER_CYCLE-1)

ConversionCount = 0;

else ConversionCount++;

Reinitialize interruption for next ADC sequence Reset SEQ1, so the ADC sequence interruption is marked as attended.

AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;

Clear INT SEQ1 bit, so the interruption is activated to be called the next time. AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;

Acknowledge interrupt to PIE. So the whole interruption vector is marked as attended, it is possible to acknowledge the whole group because this interruption is the only one of this group which can be called in this project.

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

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4.3.6. Other subroutines This sections describe the others function present in the load controller source

code which do not fit in the previous categories. This function sets the time stamp to a desired value. It should be called by an

external source of synchronization, for example the time given by the GPRS network.

void time_synchronization(long time)

current_time = time;

The next functions controls the relay. They change the state flag and open or close the relay according to the function. In this prototype the relay is simulated by a LED diode which is turned on when the load should be connected and is turned off in the opposite case. The way of activating the LED is the same to activate an external relay.

Inside this fuctions can be added any other instructions required in the final design

in order to do any other task like changing the thermostat themperature of a heat pump or a fridge.

Sets the state of load controller to close and activates the LED.

void close_relay()

relay_status=CLOSE;

GpioDataRegs.GPFSET.bit.GPIOF8 =0x1;

Sets the state of load controller to open an disconnects the LED. void open_relay()

relay_status=OPEN;

GpioDataRegs.GPFCLEAR.bit.GPIOF8 =0x1;

//IT SHOULD BE STARTED HERE THE DATA SUBMISION

This function changes the frequency and decay thresholds. They should be used in order to change them once the program is compiled and running by future extensions. For example for change them remotely though the GPRS network.

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void set_higher_limit(unsigned int new_limit)

higher_limit=new_limit;

void set_lower_limit(unsigned int new_limit)

lower_limit=new_limit;

void set_decay_threshold(float new_limit)

decay_limit=new_limit; //set new frequency decay threshold

Finally, the last functions are stubs, which are not implemented function. The first stub corresponds to the frequency that should change the temperature set

points; it should be modified depending on the selected interface.

void set_points_update(unsigned int T_high,unsigned int T_low)

//this function should change the temperature set points if applicable

The second stub should be implemented to store the data in the external memory.

In the case of using a serial flash memory, as recommended, is should store all the acquired data in the last free memory address. Another function would be needed to read the acquired data when it is needed to delivery it. In order to simulate the data storage it is used the external RAM, it obviously cannot fulfill the memory capacity required.

//this stub should store last measurements in external flash memory

//store measurements in internal RAM

ext_time[ext_index]=time;

ext_period[ext_index]=period;

ext_voltage[ext_index]=voltage;

ext_current[ext_index]=current;

ext_power[ext_index]=power;

ext_decay[ext_index]=decay;

ext_relay[ext_index]=relay;

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//increment the index and reset to zero if out of bounds

ext_index++;

ext_index=ext_index%STUB_EXT_MEMORY_LEGTH;

117

5 FUNCTIONALITIES AND PERFORMANCE

The load controller is able to carry out the two control logics, Type I and Type II. It can reconnect the load within a random selectable amount of time, 30 seconds

by default. The load controller is prepared to be extended in the future. It supports the time

synchronization and changing the configuration values in running time, in the case of adding an external synchronization source and a communication module.

It is also prepared to store the acquired data in a external memory in the case of

adding an external data storage module.

Accuracy

Frequency ±7,5mHz. @50Hz

Voltage ±0,3V

Current ±0,015A

Power ±5W

Maximum measurement delay: 0,5s (Average of 25 values) Maximum power measurement delay: 1ms Note that this result corresponds to a load of nominal 600W. The current accuracy

could be improved by expanding the current signal in the ADC conversion range; it can be done by changing the number of loops in the current transformer. In consequence the power accuracy could be improved to.

119

6 FUTURE WORK

This section describes the next logic steps in following stages of this project, if it

is continued in the future.

6.1. Flash memory This program is programmed using only RAM memory. Using this memory

entails three problems. The first problem is the Memory limitation, the RAM memory is not enough to

expand too much the program, in order to follow the development of this project is recommendable to use the extra memory space given by Flash Memory.

The second problem is about the persistence of the program. The RAM memory does not allow maintaining the stored data when it is powered off, therefore, in a power cut, the internal data could be erased.

The last problem is the remote software update, it is not possible to update the program stored in RAM memory from a external source in exception of the PC, the on-chip flash memory is possible to be updated from other sources, like a GPRS module that sends the new program by the internet.

6.2. Communication part In order to make the load controller fully useful, is needed the communication

with remote locations. It has no sense to store the measurements if it is not possible to retrieve it in order to be studied.

A solution can be to use a GPRS module. This module through the RS-232 port

can get the acquired data and send it to a desired location. This module can be the GM862 QUAD manufactured by the corporation Round Solutions. This module

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120

supports the TCP/IP stack as well as for example the FTP protocol. TCP/IP allows sending though the GPRS network the data directly to a computer that could record the data from every load controller.

This module also has the possibility of being programmed, with the high level

language Python and it also has two RS-232 ports, one can be used for receiving the measurements and the other to update the internal software. The capability of being programmed is essential because during the update the DSC cannot execute any code, therefore the GSPS module can take the control.

6.3. Persistent storage The load controller measurement has a pretty high throughput of data. It has to

store some measures in short periods of time. It has to store and send the measures ten minutes before a frequency event. The measures have to be stored somewhere, this place can be and external persistent storage based on Serial Flash memory. This serial flash has enough capacity to store the measurements, their capacities goes from 1Mb to 128Mb. They are connected with the SPI interface of the DSC. The serial nature of the measurements made by the load controller is suitable for this kind of memory.

This memory can be used also to preserve configuration changes made remotely.

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7 CONCLUSIONS

In this section I going to explain all the objectives achieved in the developing of

this project, as well as all the problems solved. The development of a real project evolves lots of mishaps and problems which

before the begging of this project I was not able to imaging. I thought that these problems are common and the experience acquired in this project allows me to surpass them easier than before.

The first point solved is to search the hardware needed to achieve the

specifications. The market is full of manufacturers which has lots of processors. The research process is a critical point, choosing a wrong processor could result in a complete fail. Changing the processor, which is the main part of these kind of project, in an advance stage could imply in starting the development again. Now I know how to carry out these researches and how to make them.

The next point is the design of the additional hardware that completes the

capabilities of the microcontroller. The microcontroller is the core of the hardware but it cannot fulfill all the hardware requirements, it is needed other essential hardware, such as the power supplies, or other needed hardware like the filters or the signal conditioning hardware, whose functions cannot be made by any microcontroller. I designed a simple board with making use of my knowledge about electronics but it could not completely fulfill all the requirements, but fortunately my co-tutor Tonny improved the board until the point to be suitable for my purposes.

Once the hardware part is completed the next logical step is the software

development which is the “mind” of the any electronically device based on a microcontroller. The software is also a key part of any electrical development. I have learned to use the Code Composer IDE, which is one of the best IDEs in the market. I think that know I am able to develop any other microcontroller software based on any other platform and also using any other advanced IDE.

Conclusions

122

Referring to the product obtained. I have developed a prototype of a load

controller based on the specifications given by my Tutor Zhao Xu. The prototype developed is a frequency meter. The load controller is also able to measure voltage, current and power. It is also capable of react to frequency events, frequency drops and excess of frequency decay. The project has being developed with the expandability in mind, because this prototype has to be continued in order to be fully working product.

In resume, I have developed a prototype able to help the power grid integrity

against changes of power consumption which can involve in the imbalance of the consumption-production power grid equilibrium. The continuity of this project is leaved open to be followed by any other student in order to complete a fully working load controller as described in the future work section.

With these words I consider this Master thesis ended. Thank you for reading, Alejandro Nieto.

123

8 BIBLIOGRAPHY

1. Grastrup, Martin Skov Johansen & Lars Henrik. Consumer Based Freqeuncy Controlled Reserve in the Danish Power Grid. Lyngby : s.n., 2006. 2. Agilent Technologies. Understanding Frequency. agilent.com. [Online] http://cp.literature.agilent.com/litweb/pdf/5965-7664E.pdf. 3. Texas Instruments. TMS320x281x Event Manager (EV) Reference Guide (Rev. E). Texas instruments official web site. [Online] June 27, 2007. [Cited: September 1, 2007.] http://www.ti.com/litv/pdf/spru065e. 4. —. TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (Rev. D). [Online] July 2005, 14. [Cited: October 2007, 2.] http://focus.ti.com/lit/ug/spru060d/spru060d.pdf. 5. —. TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811,TMS320C2812 DSPs (Rev. O). Texas Instruments official web site. [Online] July 17, 2007. [Cited: September 1, 2007.] http://www.ti.com/lit/gpn/tms320f2812. 6. wikipedia. Root mean square. Wikipedia. [Online] wikipedia. http://en.wikipedia.org/wiki/Root_mean_square. 7. Spectrum digital. eZdspTM F2812 Technical reference. 2003. 8. California Energy Comission. Smart Load Control and Grid-Friendly Appliances. October 2003. P-500-03-096-A10. 9. Z. Xu, Member, IEEE, J. Østergaard, Member IEEE, M. Togeby, C. Marcus-Møller. Design and Modelling of Thermostatically Controlled Loads as Frequency Controlled Reserve. 10. Ning Lu, Member, IEEE and Donald J. Hammerstrom, Member, IEEE. Design Considerations for Frequency Responsive Grid Friendly Appliances. 11. Rasmussen, Tonny W. Additional hardware design and layout. Lyngby : oersted DTU, 2007.

125

A SOURCE CODE

A.1 Main program source code

/*****************************************************************

*

* File inclusion

*

*****************************************************************/

#include "DSP281x_Device.h" // DSP281x Headerfile Include File

#include "DSP281x_Examples.h" // DSP281x Examples Include File

/*****************************************************************

*

* constants definition

*

*****************************************************************/

/*** frequency measurements constants ***/

//number of frequency measurements used in average

#define AVERAGE_FREQUENCY_VALUES 25

//Recover frequency threshold in integer units (Running at 25MHz)

#define DEFAULT_HIGHER_LIMIT 62525

//Frequency event threshold in integer units (Running at 25MHz)

#define DEFAULT_LOWER_LIMIT 62626

/*** frequency decay filter constants ***/

//maximun allowable frequency change between frequencies

//measurements. 150 integer units/cycle= 6Hz/s

#define MAXIMUN_FREQUENCY_CHANGE 150

/*** frequency decay measurement constants ***/

//square of FCF, It is nedeed in frequency decay calculations,

//see thesis for more details.

#define FCF2 976562500000.0

//frequency decay event threshold

#define DECAY_THRESHOLD -0.16

//length of averaged frequency measurements, used in frequency

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//decay calculations

#define AVERAGE_MEASURES 5

//Measures used in RMS calculations

#define ADC_MEASURES_PER_CYCLE 40

/*** relay constants ***/

//0=OPEN CIRCUIT 1=CLOSED CIRCUIT 2=WAITING FOR RECONNECTION

#define DEFAULT_RELAY_STATUS 0x1

#define OPEN 0x0 //relay status

#define CLOSE 0x1 //relay status

#define WAIT 0x2 //relay status

//in number of powerline cycles. 1500*0.02s=30s

#define MAXIMUN_WAIT_TO_ATTACHMENT 1500

/*** control logic type II ***/

#define KF 1 //KF value in Control logic type II

#define FO 62500 //Nominal frequency in Nordic systme, integer units.

/*** data recording constants ***/

//This constan defines the number of records stored in

//external memory simulating the external memory

#define STUB_EXT_MEMORY_LEGTH 5

/*****************************************************************

*

* Special memory allocations

*

*****************************************************************/

#pragma DATA_SECTION(measures, ".extRAM"); //stores this array in external RAM

#pragma DATA_SECTION(average_measures, ".extRAM"); //stores this array in external RAM

/*****************************************************************

*

* Function prototype definition

*

*****************************************************************/

/*** frequency measurement functions ***/

//definition of the interruption subroutine of capture unit 1


interrupt void Capture1_isr(void);

#pragma CODE_SECTION(Capture1_isr, "ramfuncs");

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/*** data adquisition functions ***/

//definition of the interruption subroutine of ADC


interrupt void adc_isr(void);

#pragma CODE_SECTION(adc_isr, "ramfuncs");

/*** relay control functions ***/

void close_relay(void); //opens the load relay

void open_relay(void); //closes the load relay

//sets the frequency recover threshold

void set_higher_limit(unsigned int);

//sets the frequency event threshold

void set_lower_limit(unsigned int);

/*** time stamp ***/

//synchronices the real time counter

void time_synchronization(long);

/*** decay functions ***/

//sets the frequency decay threshold

void set_decay_limit(float);

/*** Control logic type II ***/

void set_points_update(unsigned int,unsigned int);

/*** storing stub ***/

//Function that should store the recors in external memory

void recod(long time,unsigned int period,unsigned int voltage,unsigned int current,unsigned long

power, float decay,short relay);

/*****************************************************************

*

* variables and array definition and initialization

*

*****************************************************************/

//generic variables

short i; //generic index

short j; //generic index

/*** frequency measurement ***/

// Temp integers variables in capture unit subroutine



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//addition of al the last AVERAGE_FREQUENCY_VALUES periods.

unsigned long measures_addition;

//table of instant frequency measurements

unsigned int measures[AVERAGE_FREQUENCY_VALUES];

//table of average frequency measurements

unsigned int average_measures[AVERAGE_MEASURES];

//index used in frequency measurement array

unsigned int measure_index=0;

unsigned int average_measure; //average period measure

/*** Frequency decay measurement ***/

//table of frequency decay measurements

float decay[AVERAGE_MEASURES];

//last frequency decay measurement

float average_decay=0;

//frequency decay threshold definition and initialization

float decay_limit= DECAY_THRESHOLD;

/*** relay control ***/

//frequency recover threshold initialization

unsigned int higher_limit=DEFAULT_HIGHER_LIMIT;

//frequency event threshold initialization

unsigned int lower_limit=DEFAULT_LOWER_LIMIT;

//defalut relay state initialization

short relay_status=DEFAULT_RELAY_STATUS;

//count of waited cycles on reconection

int waiting_cycles;

/*** data adquisition ***/

//ADC current measures without offset

unsigned int adc_samples_current[ADC_MEASURES_PER_CYCLE];

//ADC voltage measures without offset

unsigned int adc_samples_voltage[ADC_MEASURES_PER_CYCLE];

//Index of ADC samples table

Uint16 ConversionCount=0;

/*** Control logic II ***/

//variables to store the user high and low temperature.

unsigned int T_high=0;

undigned int T_low=0;

//output control logic II temperature

unsigned int T_high_out=0;

unsigned int T_low_out=0;

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/*** RMS calculations ***/

//square of ADC measures in RMS calculations

unsigned long adc_square_current[ADC_MEASURES_PER_CYCLE];

unsigned long adc_square_voltage[ADC_MEASURES_PER_CYCLE];

unsigned long adc_square_power[ADC_MEASURES_PER_CYCLE];

unsigned int voltage_RMS; //voltage RMS calculation result

unsigned int current_RMS; //current RMS calculation result

unsigned int power_RMS; //power RMS calculation result

//temporal variables in RMS calculations

long temp_results;

long temp2_1;

long temp2_2;

long temp2_3;

/*** Time stamp ***/

//time variable definition and initialization

long current_time=0;

/*** external memory stub ***/

unsigned int ext_index=0; //index

long ext_time[STUB_EXT_MEMORY_LEGTH]; //time

unsigned int ext_period[STUB_EXT_MEMORY_LEGTH]; //period

unsigned int ext_voltage[STUB_EXT_MEMORY_LEGTH]; //voltage

unsigned int ext_current[STUB_EXT_MEMORY_LEGTH]; //current

unsigned long ext_power[STUB_EXT_MEMORY_LEGTH]; //power

float ext_decay[STUB_EXT_MEMORY_LEGTH]; //f. decay

short ext_relay[STUB_EXT_MEMORY_LEGTH]; //relay s.

/*****************************************************************

*

* Main function, hardware initialization

*

*****************************************************************/

main()

//

// Step 1. Initialize System Control:

// PLL, WatchDog, enable Peripheral Clocks

//

InitSysCtrl(); // Init the system control

//set HSPCLK to SYSCLKOUT / 6

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//(25Mhz assuming 150Mhz SYSCLKOUT)

EALLOW;

SysCtrlRegs.HISPCP.all = 0x3; // HSPCLK = SYSCLKOUT/6

EDIS;

// Step 2. Initialize GPIO:

EALLOW; // Enable writing on write protected registers

// Sets pin as Caputure unit

GpioMuxRegs.GPAMUX.bit.CAP1Q1_GPIOA8 = 1;

//Sets relay pin as GPIO

GpioMuxRegs.GPFMUX.bit.MCLKXA_GPIOF8=0x0; //sets as I/O

GpioMuxRegs.GPFDIR.bit.GPIOF8 = 0x1; //sets as output

EDIS; // Disables writing on write protected registers

//

// Step 3. Clear all interrupts and initialize PIE vector

// table:

//

// Disable CPU interrupts

DINT;

// Initialize the PIE control registers to their default state.

// The default state is all PIE interrupts disabled and flags

// are cleared.

InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000; // Disables al interrputions

IFR = 0x0000; // Clear al interruption flags

// Initialize the PIE vector table with pointers to the shell

// Interrupt Service Routines (ISR).

// This will populate the entire table, even if the interrupt

// is not used.

InitPieVectTable();

// Interrupts that are used in this example are re-mapped to

// ISR functions found within this file.

EALLOW; // enable write in EALLOW protected registerd

// sets capture 1 unit interruption routine as Capture1_isr

PieVectTable.CAPINT1 = &Capture1_isr;

//sets adc_isr as interruption routine of ADC

PieVectTable.ADCINT = &adc_isr;

EDIS; // disable write in EALLOW protected registers

//

//

//

// Step 4. Initialize all the Device Peripherals:

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//

//

InitAdc(); //init ADC.

// Step 5. User specific code, enable interrupts:

// Configure ADC

AdcRegs.ADCTRL1.bit.RESET = 1;

//resets ADC

asm(" RPT #10 || NOP");

// Setup 2 conv's on SEQ1

AdcRegs.ADCMAXCONV.all = 0x0002;

// Setup ADCINA0 & ADCINB0 as 1st SEQ1 conv.

// Current and voltage channels


// Setup ADCINA1 & ADCINB1 as 2n SEQ1 conv.

//Current and voltage, second sample


// Setup ADCINA2 & ADCINB2 as 2n SEQ1 conv.

//Read User normal temperature high and low.


// Enable EVASOC to start SEQ1

AdcRegs.ADCTRL2.bit.EVA_SOC_SEQ1 = 1;

// Enable SEQ1 interrupt (every EOS)

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;

//set simultaneous mode to measure current and voltage

//at the same time

AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;

AdcRegs.ADCTRL3.bit.ADCEXTREF=0x0; //use internal reference

/*** EVA GP timers configuration ***/

EvaRegs.GPTCONA.all = 0; // Clears configuration

/*** Configures GP timer 1 with ADC sample rate ***/

EvaRegs.T1PR = 0x61A8; // Setup period register

EvaRegs.GPTCONA.bit.T1TOADC = 0x2; // Enable EVASOC in EVA

EvaRegs.T1CON.all = 0x1040; // Enable timer (upcount mode)

/* Configures GP timer 2 with capture unit */

EvaRegs.T2PR = 0xffff; // Sets timer periode

EvaRegs.T2CNT = 0x0000; // Initial counter value

EvaRegs.T2CON.all = 0x1340; // Configures timer 2

/* Global configuration of timers 1 and 2 */

EvaRegs.CAPCONA.all = 0x0000; // Clears configuration

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// Enables capture 1 and 2 interruption

EvaRegs.CAPCONA.bit.CAP12EN = 1;

// Chooses timer 2 as timer for capture unit 1

EvaRegs.CAPCONA.bit.CAP12TSEL = 0;

// Configures caputure unit to ditect rising edges

EvaRegs.CAPCONA.bit.CAP1EDGE = 1;

EvaRegs.CAPFIFOA.all = 0x0000; // clears FIFO A

EvaRegs.CAP1FBOT = 0x0000; // clears capture 1 FIFO top

EvaRegs.CAP1FIFO = 0x0000; // clears capture 1 FIFO bottom

/*** Configures interrptions of EVA ***/

EvaRegs.EVAIFRC.all = 0xFFFF; // Sets caputre unit 1 flags

// Enables caputure unit 1 interruption

EvaRegs.EVAIMRC.bit.CAP1INT = 1;

//initialize Relay

if(relay_status==1)

close_relay();

else

open_relay();

//initialization of instant frequency table

for(i=0;i<AVERAGE_FREQUENCY_VALUES;i++)

measures[i]=62500;

//initialization of average frequency table


average_measures[i]=62500;

//enable CPU interruptions

// Enable CAP1 in PIE, frequency measurement subroutine



// Enable ADCINT in PIE, ADC sampling subroutine



EINT; // Enable Global interrupt INTM

ERTM; // Enable Global realtime interrupt DBGM

return 0;

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/*****************************************/

/*****************************************

FREQUENCY MEASUREMENT FUNCTIONS

*****************************************/

interrupt void Capture1_isr(void)



//resets the measures accumulator

measures_addition=0;

//Measures shift and average calculation

for(i=AVERAGE_FREQUENCY_VALUES-1;i>0;i--)

measures[i]=measures[i-1];

// adds last instant measures except the last one.

measures_addition=measures_addition+measures[i];

//gets the last measure

if(temp1_2>temp1_1)

//No overflow

measures[0] = temp1_2 - temp1_1;

else

//overflow

measures[0] = temp1_2 +(0xffff- temp1_1);

//Software frequency filter

if(measures[0]>average_measures[0] + MAXIMUN_FREQUENCY_CHANGE

|| measures[0]<average_measures[0] - MAXIMUN_FREQUENCY_CHANGE)

measures[0]=measures[1]; //duplicate previous measurement

//average calculation

//adds the last measure

measures_addition=measures_addition+measures[0];

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//calculates the average

average_measure= measures_addition/AVERAGE_FREQUENCY_VALUES;

//Shift the averege values array and insert the new one.


average_measures[i]=average_measures[i-1];

average_measures[0]=average_measure;

/*** frequency decay measurement ***/

average_decay=0; //clear average decay addition


//freency decay shift

average_decay=average_decay+decay[i-1];

decay[i]= decay[i-1];

//frequency decay calculation

decay[0]=(FCF2/(float)((long)average_measures[0]*(long)average_measures[0]))

*(((float)average_measures[1]/(float)average_measures[0])-1);

//average_decay Calculation

average_decay=(average_decay+decay[0])/AVERAGE_MEASURES;

//

//RMS power voltage and current

//voltage

temp_results=0; //clear temp variable


//add square voltage measurements

temp_results=temp_results+adc_square_voltage[i];

//divide between number of elements in RMS calculation

temp_results=temp_results/ADC_MEASURES_PER_CYCLE;

voltage_RMS=temp_results; //Store result

//Current

temp_results=0;


temp_results=temp_results+adc_square_current[i];


current_RMS=temp_results;

//Power

temp_results=0;


temp_results=temp_results+adc_square_power[i];

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power_RMS=temp_results;

//Control logic Type II, Temperature Control

T_high_out=T_high*KF*(measures[0] - FO);

T_low_out=T_low*KF*(measures[0] - FO);

//Control logic Type I, relay control

if(average_measure > lower_limit || average_decay < decay_limit)

//there is a frequency event.

open_relay();

else if(average_measure < higher_limit && average_decay > decay_limit

&& relay_status!=CLOSE)

//frequency event is recovered

//the relay status in changed to "wating for attachment"

if(relay_status == OPEN) //only once

relay_status=WAIT;

waiting_cycles= temp1_2 %

MAXIMUN_WAIT_TO_ATTACHMENT;

else

//from the second time

waiting_cycles--;

if(waiting_cycles <= 0)

//the waiting time is up.

close_relay();

else if(relay_status == WAIT)

// if frequency and frequency decay do not fullfit the event

// thresholds but they dont fullfits the recover

// criteria thresholds.


//it is call the stub function that should store the data adquired in the

external memory.

recod(current_time,average_measure, voltage_RMS,current_RMS, power_RMS,

decay[0],relay_status);

//Temperature Set points change

set_points_update(T_high_out,T_low_out);

// Clears capture unit 1 interruption flag

EvaRegs.EVAIFRC.bit.CAP1INT = 1;

// PIE 3 ack

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

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/*****************************************/

/*****************************************

DATA ADQUISITION FUNCTIONS

*****************************************/

interrupt void adc_isr(void)

//current time stamp increment

current_time++;

//Current measurements

adc_samples_current[ConversionCount] = ((AdcRegs.ADCRESULT0 >>4) +

(AdcRegs.ADCRESULT2 >>4))/2;

////Voltage measurements

adc_samples_voltage[ConversionCount] = ((AdcRegs.ADCRESULT1 >>4) +

(AdcRegs.ADCRESULT3 >>4))/2;

T_high = AdcRegs.ADCRESULT4 >>4;

T_low = AdcRegs.ADCRESULT5 >>4;

//Calculates the square values for the RMS calculations

adc_square_current[ConversionCount]=(long)adc_samples_current[ConversionCount]*(l

ong)adc_samples_current[ConversionCount];

adc_square_voltage[ConversionCount]=(long)adc_samples_voltage[ConversionCount]*(l

ong)adc_samples_voltage[ConversionCount];

adc_square_power[ConversionCount]=adc_square_current[ConversionCount]*adc_square_

voltage[ConversionCount];

// If ADC_MEASURES_PER_CYCLE conversions have been logged, start over

if(ConversionCount == ADC_MEASURES_PER_CYCLE-1)

ConversionCount = 0;

else ConversionCount++;

// Reinitialize for next ADC sequence

AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1

AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE

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return;

/*****************************************/

/*****************************************

RELAY CONTROL FUNCTIONS

*****************************************/

void time_synchronization(long time)

current_time = time;

/*****************************************/

/*****************************************

RELAY CONTROL FUNCTIONS

*****************************************/

void close_relay()

relay_status=CLOSE; //sets status close

GpioDataRegs.GPFSET.bit.GPIOF8 =0x1; //close relay

void open_relay()

relay_status=OPEN; //sets status open

GpioDataRegs.GPFCLEAR.bit.GPIOF8=0x1; //open relay

void set_higher_limit(unsigned int new_limit)

higher_limit=new_limit; //set new recover threshold

void set_lower_limit(unsigned int new_limit)

lower_limit=new_limit; //Set new frequency event threshold

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void set_decay_threshold(float new_limit)

decay_limit=new_limit; //set new frequency decay threshold

/*****************************************/

void set_points_update(unsigned int T_high,unsigned int T_low)

//this function should change the temperature set points if applicable

void recod(long time,unsigned int period,unsigned int voltage,unsigned int current,unsigned long

power, float decay,short relay)

//this stub should store last measurements in external flash memory

//store measurements in internal RAM

ext_time[ext_index]=time;

ext_period[ext_index]=period;

ext_voltage[ext_index]=voltage;

ext_current[ext_index]=current;

ext_power[ext_index]=power;

ext_decay[ext_index]=decay;

ext_relay[ext_index]=relay;

//increment the index and reset to zero if out of bounds

ext_index++;

ext_index=ext_index%STUB_EXT_MEMORY_LEGTH;

Board Schemes

139

A.2 Memory mapping MEMORY PAGE 0 : /* For this example, H0 is split between PAGE 0 and PAGE 1 */ /* BEGIN is used for the "boot to HO" bootloader mode */ /* RESET is loaded with the reset vector only if */ /* the boot is from XINTF Zone 7. Otherwise reset vector */ /* is fetched from boot ROM. See .reset section below */ RAMM0 : origin = 0x000000, length = 0x000400 BEGIN : origin = 0x3F8000, length = 0x000002 PRAMH0 : origin = 0x3F8002, length = 0x000FFE RESET : origin = 0x3FFFC0, length = 0x000002 XINTF60 : origin = 0x100000, length = 0x008000 PAGE 1 : /* For this example, H0 is split between PAGE 0 and PAGE 1 */ RAMM1 : origin = 0x000400, length = 0x000400 DRAMH0 : origin = 0x3f9000, length = 0x001000 XINTF61 : origin = 0x108000, length = 0x008000 SECTIONS /* Setup for "boot to H0" mode: The codestart section (found in DSP28_CodeStartBranch.asm) re-directs execution to the start of user code. Place this section at the start of H0 */ codestart : > BEGIN, PAGE = 0 ramfuncs : > PRAMH0 PAGE = 0 .text : > XINTF60, PAGE = 0 .cinit : > XINTF60, PAGE = 0 .cio : > XINTF60, PAGE = 0 .pinit : > XINTF60, PAGE = 0 .switch : > RAMM0, PAGE = 0 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .stack : > RAMM1, PAGE = 1 .ebss : > DRAMH0, PAGE = 1 .econst : > DRAMH0, PAGE = 1 .esysmem : > DRAMH0, PAGE = 1 .sysmem : > DRAMH0, PAGE = 1 .extRAM : > XINTF61, PAGE = 1

Board Schemes

140

B BOARD SCHEMES

This appendix contains the full schemes of the load controller.

The symbol is understanded as an input, as well as the symbol as an output. This symbols are used to connect the intputs and outputs of the main scheme with the detail of the DSC connectors. They are also used to represent the power outlet connection.

Board S

chemes

141

Power On LEDStub Relay

Current Measuring

Transformer

Voltage Measuring

Transformer

Processor Single Power Supply

Double Power Supply

Voltage Level Shifter

110kΩ-

+

100kΩ

Voltage Output

OPA277

100nF

-5V

5V

100nF

10kΩ

23,3kΩ

100nF

5V

100kΩ

Filter

69,8kΩ

100nF

4,02kΩ

-

+

196kΩ100nF

100nF91Ω

100nF

5,49kΩ

-

+

261kΩ100nF

100nFOPA277 OPA277

100nF

-5V

5V

100nF

100nF

-5V

5V

100nF

5V 5V

Current Level Shifter

311kΩ-

+

100kΩ

Current

OPA277

100nF

-5V

5V

100nF

10kΩ

23,3kΩ

100nF

5V

100kΩ

Filter

69,8kΩ

100nF

4,02kΩ

-

+

196kΩ100nF

100nF91Ω

100nF

5,49kΩ

-

+

261kΩ100nF

100nFOPA277 OPA277

100nF

-5V

5V

100nF

100nF

-5V

5V

100nF

5V 5V

10Ω

230:6

100nF 470µF

BridgeLM7805

INPUT OUTPUT

1N4001

100nF

Wall-Outlet

5V100nF 470µF

BridgeLM7905

INPUT OUTPUT

1N4001

100nF

-5V

230:6

100nF 470µF

BridgeLM7805

INPUT OUTPUT

1N4001

100nF

Wall-Outlet

+5V

Wall-Outlet

Current

Offset

Voltage

Offset

5V

100kΩ

Relay

5V

50:1

220:1.1

Figure 8-I - B

oard Schem

e

Board Schemes

142

Figure 8-II - DSC connectors Detail

ADC Connection Socket 10x3Port 5 and 9

Connection Socket 20x3Ports 4 and 8

1 4 7 10 13

16 19 28 31 34 37 40 43 46

49 52 55 58

Relay Control

2 5 8 11 14

17 20 29 32 35 38 41 44 47

50 53 56 59

Voltage

Capture Unit

3 6 9 12 15

18 21 30 33 36 39 42 45 48

51 54 57 60

2223

24

2526

27

GP I/O

1 4 7 10 13

16 19 28

2 5 8 11 14

17 20 29

Voltage

Capture Unit

3 6 9 12 15

18 21 30

2223

24

2526

27

Voltage Offset

Current Current Offset

AD

CIN

B0

AD

CIN

B1

AD

CIN

A0

AD

CIN

A1

143

C OTHER PLOTS

The next plots show other averaged measurement plots, it shows 200 values instead of 30 as the one in the frequency measurement section. The data of these tables can be found in Table 8-III - Averaged frequency measurements.

Figure 8-III – Averaged frequency measurements (Integer units)

62350

62400

62450

62500

62550

62600

62650

1 30 59 88 117 146 175

Averaged Vs Thresholds

Average measurements recover threshold Frequency event threshold

Board Schemes

144

Figure 8-IV – Averaged frequency measurements (Hz)

50,025

50,03

50,035

50,04

50,045

1 21 41 61 81 101 121 141 161 181

Average measurements

Average measurements

145

D TABLES

D.1 ADC Measurements

Table 8-I – ADC samples table

No V I

1 2480 2047 2 2996 2182 3 3422 2284 4 3714 2370 5 3845 2393 6 3794 2382 7 3571 2327 8 3204 2230 9 2721 2109

10 2170 1969 11 1532 1805 12 864 1635 13 301 1492 14 0 1413 15 0 1417 16 0 1416 17 99 1429 18 590 1557 19 1226 1723 20 1896 1898 21 2476 2045 22 2995 2183 23 3421 2291 24 3716 2365 25 3844 2400 26 3793 2382 27 3567 2328 28 3194 2227 29 2707 2107 30 2161 1966 31 1523 1802 32 849 1628 33 294 1485

Tables

146


No V I

34 0 1403 35 0 1407 36 0 1411 37 99 1442 38 611 1570 39 1243 1732 40 1910 1901 41 2485 2049 42 3004 2184 43 3428 2288 44 3719 2370 45 3842 2393 46 3793 2384 47 3570 2325 48 3196 2235 49 2710 2106 50 2162 1967 51 1526 1803 52 853 1629 53 293 1490 54 0 1407 55 0 1411 56 0 1413 57 100 1433 58 606 1569 59 1239 1730 60 1905 1900 61 2482 2050 62 3001 2182 63 3427 2295 64 3719 2370 65 3844 2400 66 3796 2386 67 3571 2327 68 3198 2235 69 2715 2109 70 2165 1966 71 1530 1803 72 862 1632 73 302 1492 74 0 1412 75 0 1411 76 0 1405 77 98 1434 78 599 1567 79 1238 1727 80 1902 1899 81 2479 2050 82 3000 2180

Tables

147


No V I

83 3425 2287 84 3717 2365 85 3844 2397 86 3794 2389 87 3573 2332 88 3200 2230 89 2716 2108 90 2166 1967 91 1534 1806 92 863 1635 93 294 1483 94 0 1416 95 0 1413 96 0 1416 97 102 1441 98 596 1562 99 1226 1723

100 1899 1898

Tables

148

D.2 Frequency measures Note that the measurements made by the load controller are the ones that are in

integer units and the values in Hz are calculated as explained in the respective section.

Table 8-II - Instant frequency measurements

No Instant frequency (int) Averaged freq (int) Instant freq. (Hz) averaged freq. (int) 1 62509 62503 49,993 49,998 2 62492 62502 50,006 49,998 3 62495 62503 50,004 49,998 4 62510 62503 49,992 49,998 5 62498 62500 50,002 50,000 6 62498 62500 50,002 50,000 7 62523 62500 49,982 50,000 8 62509 62500 49,993 50,000 9 62506 62500 49,995 50,000

10 62505 62500 49,996 50,000 11 62498 62500 50,002 50,000 12 62519 62501 49,985 49,999 13 62502 62500 49,998 50,000 14 62520 62501 49,984 49,999 15 62509 62500 49,993 50,000 16 62460 62501 50,032 49,999 17 62509 62502 49,993 49,998 18 62495 62503 50,004 49,998 19 62512 62503 49,990 49,998 20 62521 62503 49,983 49,998 21 62509 62502 49,993 49,998 22 62491 62502 50,007 49,998 23 62492 62503 50,006 49,998 24 62491 62503 50,007 49,998 25 62509 62503 49,993 49,998 26 62498 62503 50,002 49,998 27 62502 62504 49,998 49,997 28 62495 62504 50,004 49,997 29 62527 62504 49,978 49,997 30 62500 62504 50,000 49,997

Tables

149

Table 8-III - Averaged frequency measurements

No. Frequency (Int) Frequency (Hz) 1 62455 50,0360259 2 62454 50,0368271 3 62454 50,0368271 4 62454 50,0368271 5 62454 50,0368271 6 62455 50,0360259 7 62456 50,0352248 8 62456 50,0352248 9 62457 50,0344237 10 62456 50,0352248 11 62456 50,0352248 12 62455 50,0360259 13 62455 50,0360259 14 62455 50,0360259 15 62455 50,0360259 16 62454 50,0368271 17 62454 50,0368271 18 62454 50,0368271 19 62455 50,0360259 20 62455 50,0360259 21 62455 50,0360259 22 62455 50,0360259 23 62454 50,0368271 24 62455 50,0360259 25 62455 50,0360259 26 62455 50,0360259 27 62454 50,0368271 28 62455 50,0360259 29 62454 50,0368271 30 62454 50,0368271 31 62454 50,0368271 32 62454 50,0368271 33 62454 50,0368271 34 62454 50,0368271 35 62453 50,0376283 36 62452 50,0384295 37 62452 50,0384295 38 62452 50,0384295 39 62453 50,0376283 40 62454 50,0368271 41 62456 50,0352248 42 62456 50,0352248 43 62457 50,0344237 44 62455 50,0360259 45 62456 50,0352248 46 62455 50,0360259 47 62455 50,0360259

Tables

150


No. Frequency (Int) Frequency (Hz) 48 62456 50,0352248 49 62455 50,0360259 50 62456 50,0352248 51 62456 50,0352248 52 62456 50,0352248 53 62457 50,0344237 54 62457 50,0344237 55 62457 50,0344237 56 62457 50,0344237 57 62456 50,0352248 58 62456 50,0352248 59 62457 50,0344237 60 62457 50,0344237 61 62458 50,0336226 62 62458 50,0336226 63 62459 50,0328215 64 62459 50,0328215 65 62458 50,0336226 66 62457 50,0344237 67 62457 50,0344237 68 62456 50,0352248 69 62457 50,0344237 70 62457 50,0344237 71 62457 50,0344237 72 62458 50,0336226 73 62458 50,0336226 74 62457 50,0344237 75 62456 50,0352248 76 62456 50,0352248 77 62456 50,0352248 78 62456 50,0352248 79 62456 50,0352248 80 62456 50,0352248 81 62456 50,0352248 82 62456 50,0352248 83 62456 50,0352248 84 62455 50,0360259 85 62456 50,0352248 86 62455 50,0360259 87 62455 50,0360259 88 62455 50,0360259 89 62453 50,0376283 90 62452 50,0384295 91 62452 50,0384295 92 62451 50,0392308 93 62452 50,0384295 94 62451 50,0392308 95 62450 50,040032 96 62450 50,040032

Tables

151



Tables

152



Tables

153


No. Frequency (Int) Frequency (Hz) 195 62453 50,0376283 196 62452 50,0384295 197 62452 50,0384295 198 62451 50,0392308 199 62452 50,0384295 200 62452 50,0384295

Tables

154

Note that the values in integer units are the measurements done by the load controller and the values in the S.I are calculated as explained in the respective section.

Table 8-IV - RMS measurements

voltage (int) Voltage (V) current (int) Current (A) power (Int) Power (W)

1410 224,503227 363 2,21557617 622406 604,8634 1410 224,503227 363 2,21557617 622408 604,865344 1410 224,503227 363 2,21557617 622424 604,880893 1410 224,503227 363 2,21557617 622165 604,629193 1410 224,503227 364 2,22167969 623789 606,20742 1410 224,503227 364 2,22167969 623741 606,160773 1410 224,503227 364 2,22167969 623300 605,732203 1409 224,344005 364 2,22167969 623573 605,997508 1409 224,344005 364 2,22167969 623138 605,574769 1409 224,344005 364 2,22167969 623093 605,531037 1409 224,344005 363 2,21557617 623091 605,529093 1409 224,344005 364 2,22167969 623098 605,535896 1409 224,344005 364 2,22167969 623224 605,658345 1410 224,503227 363 2,21557617 622940 605,382349 1410 224,503227 363 2,21557617 622699 605,148142 1410 224,503227 363 2,21557617 622584 605,036383 1410 224,503227 363 2,21557617 621658 604,136483 1410 224,503227 363 2,21557617 621646 604,124821 1409 224,344005 362 2,20947266 620754 603,257962 1408 224,184783 362 2,20947266 620712 603,217146 1408 224,184783 362 2,20947266 620712 603,217146 1408 224,184783 362 2,20947266 620718 603,222977 1409 224,344005 362 2,20947266 620820 603,322102 1409 224,344005 362 2,20947266 621078 603,57283 1409 224,344005 362 2,20947266 620208 602,727351 1409 224,344005 361 2,20336914 618550 601,116082 1409 224,344005 361 2,20336914 618746 601,306558 1409 224,344005 361 2,20336914 619261 601,807042 1409 224,344005 361 2,20336914 619377 601,919773 1410 224,503227 361 2,20336914 619337 601,8809 1410 224,503227 361 2,20336914 619337 601,8809 1409 224,344005 361 2,20336914 619335 601,878957 1409 224,344005 361 2,20336914 619405 601,946984 1409 224,344005 362 2,20947266 619853 602,382357 1409 224,344005 362 2,20947266 620191 602,71083 1409 224,344005 361 2,20336914 618636 601,199658 1409 224,344005 361 2,20336914 618278 600,851748 1409 224,344005 361 2,20336914 617978 600,560204 1410 224,503227 361 2,20336914 618528 601,094702 1410 224,503227 361 2,20336914 618545 601,111223 1410 224,503227 361 2,20336914 618545 601,111223 1410 224,503227 361 2,20336914 618538 601,10442 1409 224,344005 361 2,20336914 618436 601,005295 1409 224,344005 361 2,20336914 618489 601,056801 1409 224,344005 361 2,20336914 618439 601,00821 1410 224,503227 362 2,20947266 620316 602,832307

Tables

155

Table 8-IV - RMS measurements

voltage (int) Voltage (V) current (int) Current (A) power (Int) Power (W)

1410 224,503227 362 2,20947266 619299 601,843971 1410 224,503227 361 2,20336914 618714 601,27546 1410 224,503227 361 2,20336914 618733 601,293924 1410 224,503227 361 2,20336914 618763 601,323079 1410 224,503227 361 2,20336914 618763 601,323079 1410 224,503227 361 2,20336914 618761 601,321135 1410 224,503227 361 2,20336914 618500 601,067491 1409 224,344005 360 2,19726563 617741 600,329884 1409 224,344005 361 2,20336914 617917 600,500923 1409 224,344005 361 2,20336914 618790 601,349318 1409 224,344005 361 2,20336914 619367 601,910055 1409 224,344005 362 2,20947266 620667 603,173414 1410 224,503227 362 2,20947266 620396 602,910052 1410 224,503227 362 2,20947266 620406 602,91977 1410 224,503227 362 2,20947266 620406 602,91977 1410 224,503227 362 2,20947266 620402 602,915883 1410 224,503227 361 2,20336914 620345 602,86049 1409 224,344005 361 2,20336914 620057 602,580607 1409 224,344005 361 2,20336914 619835 602,364864 1409 224,344005 361 2,20336914 619448 601,988772 1409 224,344005 361 2,20336914 620337 602,852715 1409 224,344005 361 2,20336914 620398 602,911996 1409 224,344005 362 2,20947266 620589 603,097612 1409 224,344005 362 2,20947266 620599 603,107331 1409 224,344005 362 2,20947266 620599 603,107331 1409 224,344005 362 2,20947266 620594 603,102472 1409 224,344005 362 2,20947266 620710 603,215202 1410 224,503227 362 2,20947266 621041 603,536873 1410 224,503227 363 2,21557617 622379 604,837161 1410 224,503227 362 2,20947266 621486 603,96933 1410 224,503227 362 2,20947266 621092 603,586435 1410 224,503227 362 2,20947266 620827 603,328904 1410 224,503227 362 2,20947266 620902 603,40179 1410 224,503227 362 2,20947266 620947 603,445522 1410 224,503227 362 2,20947266 620947 603,445522

Tables

156

D.3 Frequency decay

Table 8-V - Frequency decay

No fequency decay 1 0,03970647 2 -0,03954634 3 0 4 0 5 0 6 0,03970647 7 0,03971905 8 0 9 0,03973164 10 -0,0395714 11 0 12 -0,03955887 13 0 14 0 15 0 16 -0,03954634 17 0 18 0 19 0,03970647 20 0 21 0 22 0 23 -0,03954634 24 0,03970647 25 0 26 0 27 -0,03954634 28 0,03970647 29 -0,03954634 30 0 31 0 32 0 33 0 34 0 35 -0,03953382 36 -0,03952131 37 0 38 0 39 0,03968133 40 0,0396939 41 0,07943811 42 0 43 0,03973164 44 -0,07911773 45 0,03971905 46 -0,03955887

Tables

157


No fequency decay 47 0 48 0,03971905 49 -0,03955887 50 0,03971905 51 0 52 0 53 0,03973164 54 0 55 0 56 0 57 -0,0395714 58 0 59 0,03973164 60 0 61 0,03974424 62 0 63 0,03975685 64 0 65 -0,03959649 66 -0,03958394 67 0 68 -0,0395714 69 0,03973164 70 0 71 0 72 0,03974424 73 0 74 -0,03958394 75 -0,0395714 76 0 77 0 78 0 79 0 80 0 81 0 82 0 83 0 84 -0,03955887 85 0,03971905 86 -0,03955887 87 0 88 0 89 -0,07906764 90 -0,03952131 91 0 92 -0,03950881 93 0,03966878 94 -0,03950881 95 -0,03949631

Tables

158


No fequency decay 96 0 97 -0,03948383 98 0 99 0 100 0 101 -0,03947135 102 -0,03945888 103 0,03961863 104 0,03963116 105 0 106 -0,03947135 107 -0,03945888 108 0 109 0 110 -0,03944642 111 0 112 0 113 -0,03943396 114 0 115 0 116 0,03959361 117 0,03960612 118 0,03961863 119 0 120 0,03963116 121 0 122 0,03964369 123 0 124 0 125 0,03965623 126 0 127 0,03966878 128 -0,03950881 129 -0,03949631 130 0 131 0,03965623 132 0,03966878 133 0 134 0,03968133 135 -0,03952131 136 0,03968133 137 0,0396939 138 0 139 0 140 0,03970647 141 -0,03954634 142 -0,03953382 143 0,0396939 144 -0,03953382

Tables

159


No fequency decay 145 0 146 -0,03952131 147 -0,03950881 148 0 149 0 150 0,03966878 151 0 152 0 153 -0,03950881 154 0,03966878 155 -0,03950881 156 0 157 0 158 0,03966878 159 -0,03950881 160 0,03966878 161 -0,03950881 162 0 163 0,03966878 164 0 165 0 166 0 167 0 168 0 169 -0,03950881 170 0 171 0,03966878 172 0 173 0,03968133 174 0 175 0 176 0 177 0 178 0,0396939 179 -0,03953382 180 0,0396939 181 0 182 0 183 -0,03953382 184 0,0396939 185 0 186 0 187 -0,03953382 188 0 189 -0,03952131 190 0 191 0 192 -0,03950881 193 0

Tables

160


No fequency decay 194 0,03966878 195 0,03968133 196 -0,03952131 197 0 198 -0,03950881 199 0,03966878 200 0

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Theses 8 : Alejandro Nieto Gutiérrez

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Transcript of Theses 8 : Alejandro Nieto Gutiérrez