Thermal Network Extraction in Ultra-- Thin--Body SOI...

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Thermal Network Extraction in Ultra Thermal Network Extraction in Ultra- Thin Thin-Body SOI MOSFETs Body SOI MOSFETs Y. S. Chauhan 1,2 , M. A. Karim 2 , A. M. Y. S. Chauhan 1,2 , M. A. Karim 2 , A. M. Niknejad 2 and C. C. Hu 2 1 Indian Institute of Technology (IIT) Kanpur, India 2 University of California Berkeley, USA

Transcript of Thermal Network Extraction in Ultra-- Thin--Body SOI...

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Thermal Network Extraction in UltraThermal Network Extraction in Ultra--ThinThin--Body SOI MOSFETsBody SOI MOSFETs

Y. S. Chauhan1,2, M. A. Karim2, A. M. Y. S. Chauhan1,2, M. A. Karim2, A. M. Niknejad2 and C. C. Hu2

1Indian Institute of Technology (IIT) Kanpur, India

2University of California Berkeley, USA

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OutlineOutline

• Introduction

• Thermal Network Characterization

• Results

• Other News

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IntroductionIntroduction

• Carrier scattering leads to heat generation

• Dominant at drain end of MOSFETdue tohigh fieldhigh field

• Temperature increase affects deviceparameters e.g. threshold voltage, mobility etc.

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Power Density and scalingPower Density and scaling

2,300 transistors in 2,300 transistors in Intel Intel 4004 4004

processor (10processor (10µµm)m)

1971

1.4 billion transistors in Intel Ivy Bridge 4C (22nm)

SourceSource:: E. Pop et al., “Heat Generation and Transport in Nanometer-ScaleTransistors”, Proceedings of the IEEE , August 2006.

Hot Plate

Nuclear Reactor

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FigureFigure : Trend of on chip power densityover the past 10 years. Solid line marksan exponential trend.

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Self Heating & Technology ScalingSelf Heating & Technology Scaling

Figure: Figure: Increase in ∆T with technology scaling

Source: Source: O. Semenov et al., IEEE Tras. on Device and Materials Reliability, March 20069/21/2012 5Yogesh S. Chauhan

FigureFigure:: Performance degradation of athree stage ring oscillator due to selfheating effect versus technology scaling

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Self Heating: Effect of Structure/TechnologySelf Heating: Effect of Structure/Technology

Bulk MOSFET SOI MOSFET FinFET

Evolution of MOSFET ArchitectureEvolution of MOSFET Architecture

• Technology scaling achieved by – New materials (SOI, High-K dielectric, Strained Silicon etc.)– Highly confined geometry

• New materials and greater confinement increased self heating effect9/21/2012 6Yogesh S. Chauhan

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Confinement & Thermal ConductivityConfinement & Thermal Conductivity• Bulk Si – 50% of the heat conduction is carried by phonons witha mean-free-

path greater than about 1 µm.

• For film thickness is smaller than∼200nm, 50% of the heat is carried byphonons with mean-free-paths longer than the film thickness.

Material Thermal conductivity

(W/m-K)

Si(Bulk) 149Si(Bulk) 149

Ge 60.2

SiO21.4

HfO2(>500nm) 1.2

HfO2(3nm) 0.27-0.49

SourceSource:: Ch. Jeong, S. Datta, M. Lundstrom “Thermal conductivity of bulk and thin-film silicon:A Landauer approach” JOURNAL OF APPLIED PHYSICS 111, 093708 (2012)9/21/2012 7Yogesh S. Chauhan

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Impact of Self HeatingImpact of Self Heating

Note decrease in current with VDS

Negative gds9/21/2012 8Yogesh S. Chauhan

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Self Heating MeasurementSelf Heating Measurement

• Gate Current measurement– Requires dedicated structures– Measures gate temperature

Ref.: S. Khandelwal et al., "Scalable Thermal Resistance Model for singleand multi-finger Silicon-on-Insulator MOSFETs", IEEE ICMTS, April

• Pulsed measurement technique– DC structures can be used– Requires dedicated setup– Works upto limited frequencies.

and multi-finger Silicon-on-Insulator MOSFETs", IEEE ICMTS, April2011

Ref.: C. Anghel et al., “Self-heating characterization andextractionmethod for thermal resistance and capacitance in HVMOSFETs”,IEEE EDL 20049/21/2012 9Yogesh S. Chauhan

FigureFigure:: Output characteristics of n-channelDMOSFET. Comparison b/w steady state DCmeasurement and different pulse widthmeasurement. Insetthemeasurementsetup.

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Self Heating MeasurementSelf Heating Measurement

• Small signal conductance technique– DC structures can be used

– Widely used technique

– What if there is no clear self heating free region?– What if there is no clear self heating free region?

• S- parameter measurement technique– Versatile technique

– Requires dedicated RF structures and measurements

Ref.: W. Redman-White et al., “Direct Extraction of MOSFET Dynamic Thermal Characteristics from Standard Transistor Structuresusing Small Signal Measurements”, Electronics Letters, June 1993.Ref.: Wei Jint et al.,"Self-Heating Characterization for SOI MOSFET Based on AC Output Conductance", IEDM 1999

Ref. 1: M. A. Karim et al., "Extraction of Isothermal Condition and ThermalNetwork in UTBB SOI MOSFETs", IEEE EDL 2012Ref. 1: A.J. Scholten et al., "Experimental assessment of self-heating in SOI FinFETs", IEDM 2009Ref. 2: N. Rinaldi et al., “Small-Signal Operation of Semiconductor Devices including Self-heating, with Application to ThermalCharacterization and Instability Analysis”, IEEE TED 20019/21/2012 10Yogesh S. Chauhan

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SS--parameter measurementparameter measurement

• S-parameters measured using vector networkanalyzer (VNA) (e.g. Agilent E5071C ENAwithfrequency range of 100 kHz–8.5 GHz)

• De-embedding– Use de-embedding to remove parasitics– Probe/wire parasitics are de-embedded using

calibration substrate– Pads to device parasitics are de-embedded using

OPEN-SHORT de-embedding

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Self Heating: OpenSelf Heating: Open--Short DeShort De--embeddingembedding

DeviceDevice OpenOpen ShortShort

Courtesy: Agilent Technologies9/21/2012 12Yogesh S. Chauhan

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Issues in thermal network extractionIssues in thermal network extraction

• No self heating free region in gds due to parasitics inshort channel devices

• Electrical contribution in CDD cannot explain 2-3order decrease Ref.: A.J. Scholten et al., "Experimental assessment of self-

heating in SOI FinFETs", IEDM 2009

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Issues in thermal network extractionIssues in thermal network extraction

• Impact of choosing arbitrary isothermalfrequency

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FigureFigure:: Extraction of DC thermal resistance (RTH0) using differentarbitrary isothermal frequencies.

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Our Approach: Thermal Network Our Approach: Thermal Network ExtractionExtraction

• Thermal contribution in Im(YDD)dominates over electrical (substrateand/or gate resistance network) at low-frequency

• Im(YDD) at VGS=1.4V ∂ Im(YDD) atVGS=1.2VVGS=1.2V– Proportionality constant depends on

the ratio of currents• Around isothermal frequency, electrical

contribution start dominating overthermal contribution to Im(YDD), andproportionality relationship becomesinvalid

• Frequency at which splitting happens isthe isothermal frequency FigureFigure:: Measured Im(YDD)

of UTBSOI MOSFET9/21/2012 15Yogesh S. Chauhan

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Our Approach: Thermal Network Our Approach: Thermal Network ExtractionExtraction

• Simultaneous fitting of Re(YDD) and Im(YDD) as both are sensitive to change in temperature.

( )YVIdIYYZ

DS

iso

DDDDth

.+

−=

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( )YVIdTdI

DDDSDSabm

DS .+

( )( ) ( ) ( )

( )( ) ( )[ ] ( )

( )DnReDnImYYRe

DnReDnImDnReZIm

YImiso

DDDD22

thDD

−+

+=

( )YVIdTdIDn DDDSDS

amb

DS .+=Where,

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Self Heating: Thermal networkSelf Heating: Thermal network

Equivalent Thermal resistance Rth

Thermal impedance of nth order thermal N/W

( ) ( )( ) ( ) ( )∑

ππ∑π == +

−+

=n

1i2

thithi

2thi

2

thin

1i2

thithi

2thi

th

CRf2CRf2j

CRf2RZ

11( )∑π= +

=n

1ithithi

thith

CRf2jRZ

1or

Equivalent Thermal resistance Rth

Equivalent Thermal capacitance Cth

DC Thermal resistance RTH0

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( ) ( )∑π= +

=n

1i2

thithi

2thi

CRf2R)ZRe(

1th

( ) ( ) ( )∑ππ = +

=n

1i2

thithi

2thi

2

thith

CRf2CR

f2Z

1

)Im(

∑=

===

n

1ithi0fth RRRTH0

Figure: Figure: nth order thermal network

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Order of thermal networkOrder of thermal network

FigureFigure:: Fitting of Im(YDD) using various-orderthermal networks independently. Results are shownfor the self-heating dominated segment of thespectrum

Figure: Figure: nth order thermal network

Accuracy increase with orderof network but computationalefficiency of the model goesdown

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ResultsResults• Third order network extracted by simultaneous fitting

of Re(YDD) and Im(YDD)

FigureFigure:: Measured and extracted Re(YDD) andIm(YDD) on 30nm and 100nm lengthUTBSOI devices. VGS=VDS=1.2V.

Figure: Figure: DC temperature rise for 30nm and 100nm length devices due to self heating effect.

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Self Heating Self Heating –– Should we care?Should we care?

• Digital circuits operate in 1-2 GHz range– No effect of self heating ☺

• RF circuits operate in 5-100 GHz range– No effect of self heating ☺– No effect of self heating ☺

• Analog circuits operate in KHz-MHz range– Self heating is dominant up to ~30-40 MHz

– Analog designers should be careful �

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ConclusionConclusion• A better approach for thermal network extraction

was presented• Temperature may rise by more than 100ºC due to self

heating effect in SOI devices– Idsatdecreases around 4-5%

• Digital and RF circuits doesn’t get affected by SHE• Digital and RF circuits doesn’t get affected by SHE– Analog circuits do have performance degradation

• Ref.• M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D.

Lu, B. Y. Nguyen, O. Faynot, A. M. Niknejad, and C. Hu, “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs”, IEEE Electron Device Letters, Vol33, No.9, Sept. 2012.

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Other NewsOther News

• Released BSIM6.0.0-beta8in Aug. 2012 with improved global scaling– Received Excellent feedback on the model

• Released CMC standard BSIM-CMG 106.1.0 • Released CMC standard BSIM-CMG 106.1.0 in Sept. 2012

• Released BSIM4.7.1-beta for testing

• Released BSIMSOI4.5-beta for testing

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AcknowledgmentAcknowledgment

• Chandan Yadav (IIT Kanpur)

• Sourabh Khandelwal (NTNU, Norway)

• Bich-Yen (SOITEC, USA)

• Olivier Faynot(LETI, Grenoble)• Olivier Faynot(LETI, Grenoble)

• Darsen Lu (IBM, Fishkill)

• Maryam(Sahar) Tabesh (UCB)

• Cristian Marcu (UCB)

• Amin Arbabian (UCB)

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