Thermal and Electrical Co-Design of a Modular High-DensitySingle-Phase Inverter Using Wide-Bandgap Devices

Steven Chung1, Miad Nasr1, David Guirguis1, Masafumi Otsuka1, Shahab Poshtkouhi1, David K. W. Li1,Vishal Palaniappan1, David Romero1, Cristina Amon1, Ray Orr2, Olivier Trescases1

1University of Toronto, 10 King’s College Road, Toronto, ON, M5S 3G4, Canada2Solantro Semiconductor, Ottawa, ON, K2E 7Y1, Canada

Abstract— This paper explores the multi-disciplinary designchallenges in building a 240 VAC, 2 kVA modular single-phaseinverter with high power-density using wide-bandgap transistors.The compromise between the electrical and mechanical designis extremely important in any high-density power converter.In this work the electrical and mechanical systems wereiteratively co-designed using detailed 3D thermal and air-flowsimulations. Custom copper heat-sinks and heat-pipes weredeveloped for optimal thermal management. The inverter usesthree soft-switching sub-inverters in parallel, which are controlledusing a novel digital Hysteretic Current Mode Control (HCMC)scheme. To achieve a flat high efficiency curve with low THD overa wide load range, two operating modes are used: 1) BoundaryConduction Mode (BCM) with a slight negative inductor valleycurrent for soft-switching, and 2) Continuous Conduction Mode(CCM) to limit the required saturation current in the inductors.The design of an active power decoupling scheme to minimizeinput capacitance is also discussed. The designed single-phaseinverter has a volume of 33.1 in3 and resulting theoreticalpower-density of 60.3 W/in3 at 2 kW load. A measured efficiencyof 97.7% is achieved for a single sub-inverter with 4.5% THDat 632.7 W.

I. INTRODUCTION

Emerging wide-bandgap, high-voltage Gallium Nitride(GaN) and Silicon Carbide (SiC) devices offer theopportunity to shrink inverters by scaling up the switchingfrequency, fs, and reducing the size of passive components[1]–[5]. Wide-bandgap devices have been demonstrated fora wide-range of low and medium-power Power FactorCorrection (PFC) ac-dc converters below 10 kW [6]–[8]. Fourmajor challenges are addressed in this work to achieve a highdensity:

1) precise current-mode control to balance efficiency, sizeand Total Harmonic Distortion (THD),

2) active thermal management,3) 120 Hz power decoupling, and4) EMI mitigation.

The target outcome of this work is a compact single-phaseinverter design. This paper covers the electrical andmechanical co-design of the inverter, as well as the initialtesting and integration. The electrical architecture and controlschemes of the inverter are discussed in Section II. Themechanical design, methodology and thermal simulationsare presented in Section III. Initial experimental results ofefficiency and Total Harmonic Distortion (THD) optimizationof a single sub-inverter are presented in Section IV.

+Vin

-

CONTROL

LOGIC

>+-

>+-

D/A

D/A

Current Loop

Phase 1: Sub-inverter

A/D

DTControl

DTControl

HFcap

EMI

Filter

Digital

Current

Modulator

amp

Load

Vsense

A/D

Mode Selection,

Voltage Loop,

Phase-Shedding

+

Vbus

-

Phase 2-3: Sub-inverters

phase_en<2:0>

sync

120 Hz Active Power Decoupling

Rsense

iL(t)

+Vbus

-

Vdrive

VDD

Vfan

L2

Vhigh

Vlow

L1

comp_high

comp_low

Vsense

Rin

HS1 HS2

LS1 LS2

Auxiliary Power Unit

(HF Flyback)

+Vac

-

(a)33µH

33µH

470µH

33nF

33nF+

10nF

10nF-

acV2µF

(b)

Fig. 1. The modular inverter’s (a) system architecture composed of threesub-inverters and one active power decoupling block and (b) the EMI filterblock.

II. ELECTRICAL DESIGN

The proposed system architecture is shown in Fig. 1(a). Amodular approach is used to optimize the mechanical designby distributing the thermal losses throughout the inverter’svolume. Three independently controlled sub-inverters, eachdesigned for a rated power of 0.67 kVA, are connected inparallel and share a common EMI filter to generate a low-THDac output voltage, Vac. The master controller provides a 60Hzsynchronization pulse to the slave controllers to allow forphase locking. The digital current reference is communicatedby the master to the slave sub-inverters as part of the outervoltage loop. An interface board is used to route multiplecontrol signals and to distribute various low-voltage suppliesneeded for the digital controllers, sensors and data-converters.The sub-inverters can be turned off at light loads for improvedefficiency, which is commonly referred to as phase-sheddingin multi-phase dc - dc converters [9], [10]. The EMI filter isshown in Fig. 1(b).

Both GaN and SiC technologies are considered for thepower transistors. The chosen 650 V, 55 mΩ GaN MOSFEThas an extremely low package volume of 41.6 mm3 anda superior RonQgate figure-of-merit (FOM) of 357 mΩ·nC[11]. The chosen 900 V, 65 mΩ SiC MOSFET has a volumeof 722.5 mm3 and RonQgate FOM of 1950 mΩ·nC [12].The GaN device was used in the initial design and thermalmodeling and was subsequently replaced with the SiC powerdevices during the testing phase for improved reliability.

HS1 HS2

LS1 LS2

V

R

ac

sense

I

IR

L

Vbus

L L

+ -

Vx1 Vx2

Fig. 2. Simplified inverter topology with common low-side sense resistor,Rsense, for current mode control (the EMI filter effect has been ignored).

A. Sub-Inverter Design and Control

Each sub-inverter power-stage is a full-bridge topology thatcan be used in four-quadrant operation, as shown in Fig. 2.Unlike conventional sinusoidal Pulse-Width-Modulation(SPWM), each sub-inverter operates in Hysteretic CurrentMode Control (HCMC) with a variable switching frequency,which is more common in PFC applications [13]. The idealswitching operation is illustrated in Fig. 3. The inductorcurrent, IL, is sensed using a single low-side shunt resistor,Rsense. Both the rising and falling inductor currents canbe detected through resistor current IR. When the inductorcurrent reaches the desired peak or valley current, the switchestoggle. The inductor slopes are given by

m1 =Vbus − Vac

2L, (1)

m2 =Vbus − (−Vac)

2L. (2)

Each sub-inverter operates in one of two possible modesduring the ac line cycle: 1) Boundary Conduction Mode(BCM) or 2) Continuous Conduction Mode (CCM). Whenoperating in BCM, a slight negative valley current, Ivalley ,is imposed to achieve zero-voltage switching turn-on on bothswitching transitions through the resonance of the switchingnode capacitance and main inductor. The dead times, td1 andtd2, are used to allow such resonant soft-switching, as shownin Fig. 3(a). During the transition period, the sensed voltageacross Rsense instantaneously changes polarity as one set of

switches commutates. In CCM, the inductor current does notchange polarity throughout the switching period. During apositive line cycle, the sensed resistor current is positive wheninductor current rises, but is inverted when inductor currentfalls, as shown in Fig. 3(b). In CCM, the soft-switching canonly be maintained for the peak inductor switching transition.A small dead time, tmin, is used at the inductor valleyswitching transition to avoid free-wheeling diode conduction.

IL

IR

0

+Ipk

+Ivly

-Ivly

-I pk

HS1

LS1

HS2

LS2

0

+Vbus Vx1 Vx2

td1 td1

td2

Iavgm1 m2

(a)HS1

LS1

HS2

LS2

IL

IR

0

+Ipk

+Ivly

-I vly

-I pk

0

+Vbus Vx1 Vx2

td1

td1

tmin

Iavg

hard switching

soft switching

ΔI

(b)

Fig. 3. Ideal switching waveforms for (a) BCM and (b) CCM operation.

The off-grid inverter controller is designed with theassumption of linear loads, hence the average inductor current,Iavg, is sinusoidal. To maintain a sinusoidal average current,Ipk is modulated according to

Ipk = 2(Iavg + Ivly), (3)

where Ivly is a constant negative current in BCM. In CCM,sinusoidal current is maintained by setting a fixed ripplecurrent, ∆I , around Iavg such that

Ipk = Iavg +∆I

2, (4)

and

Ivly = Iavg −∆I

2, (5)

as shown in Fig. 3(b).The inductors are designed to optimize 1) the volume,

2) the core losses, 3) the saturation current, 4) theinter-winding capacitance and 5) the inductance based on thevariable-frequency HCMC scheme. Type P61 high-frequencyFerrite cores are used for this design. Each sub-inverteremploys two 105 µH custom inductors. Each inductor isdesigned to have a saturation current of 6 A to limit thecore losses at higher ripple currents, which limits the averageinductor current to slightly less than 3 A in BCM. Toreach average currents above 3 A, the sub-inverter mustoperate in CCM at the high current peaks and troughsand in BCM through the zero crossings, which is referredto as dual-mode operation. The ideal inductor current forthis dual-mode, BCM/CCM, operation is shown in Fig. 4.The resonant transitions during the dead-times can causesignificant distortion with this open-loop approach, howeverthe use of low-capacitance wide-bandgap devices significantlysuppresses this effect.

At lower output power levels, operating purely in BCMresults in the lowest switching losses, at the expense of higherpeak current, higher RMS conduction losses and higher corelosses in the inductors. As load power increases, inductor corelosses increase with inductor ripple currents. In dual-modeoperation, the transition to CCM limits the saturation currentand minimizes the inductor core losses at the highest currentlevels, but causes hard-switching in the MOSFETs for half ofthe switching transitions. The sub-inverter can maintain higherefficiency over the load range by operating in dual-modeoperation.

BCM

CCMiL(t)

t

Fig. 4. Ideal dual-mode BCM/CCM operation during the ac line cycle.

The major advantage of the dual-mode scheme is that thetrade-off between efficiency and THD can be optimized at

every power level. Additionally, the inverter has a variableswitching frequency based on HCMC operation, which helpsto reduce the EMI filter size due to the spread-spectrum effect[14]. The frequency is limited to 500 kHz for control stabilityand to limit switching losses. The boundary between BCMand CCM is optimized according to the operating conditionsbased on simulations and testing results.

The analog current sensing circuit is realized with a highfrequency amplifier whose output is fed to two comparatorswith a 4.5 ns propagation delay. The comparator trigger levelsare digitally controlled on a cycle-by-cycle basis using apair of 12-bit digital-to-analog converters (DACs), and thecomparator outputs are fed to a digital controller for precisetiming control. A pre-calibrated digital feed-forward scheme,which accounts for the input and output voltage variations, canbe used to precisely set the dead-times with 7 ns resolutionin all operating modes to minimize the MOSFET switchinglosses under all conditions.

Cout

1 µF

CAPD

470 µF

Ceramic

Cbus

330 µFElectrolytic

Vin

10

Rsense

Sub-inverter

1-3

A/DLPF+

-

100 V

A/D LPF

Feed-

forward

+-

A/D LPF

Control Logic

c1

c2

c1-2

c3-4

Vcap

(a)

0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.034

5

6

I bus(A)

0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03390

400

410

Vbus(V)

0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.030

100

200

Vcap(V)

0.01 0.012 0.014 0.016 0.018 0.02 0.022 0.024 0.026 0.028 0.03500

0

500

Time (s)

PAPD(W)

(b)

Fig. 5. (a) APD architecture and high-level control scheme. (b) Simulatedperformance at full load showing an input voltage ripple below 3%.

B. Active Power Decoupling for 120 Hz Component

Assuming an equivalent source resistance, Rin, of 10 Ω,a dc input voltage of 450 Va and an ac load power of 2kW, an input capacitance of 1.32 mF is required to keepthe input voltage and current ripple below 3% and 20%,respectively. It is well known that this capacitance can be

drastically reduced by using Active Power Decoupling (APD)methods, where the 120 Hz ripple is steered into a secondarycapacitor having a much larger ripple voltage [15]–[17]. Thelosses associated with this scheme can easily outweigh thecapacitance volume reduction. A Partial Power Processing(PPP) approach is proposed for the APD in this work, as shownin Fig. 5(a).

The APD capacitor-bank is realized using 222×1µF, 450 Vceramic capacitors connected in parallel in a 3D structure. Themain advantage of this series-parallel approach is the reducedprocessed power requirement compared to the conventionalparallel or series-connected approach [18]. The double controlloop strategy uses a feedback-loop as well as feedforward pathin order to 1) keep the bus voltage ripple to a minimum, and 2)maintain a target dc bias voltage (100 V) on the node betweenCout and CAPD. An electrolytic bus capacitor of 330 µF isused together with the APD capacitor bank.

Based on this design, the APD processes only ≈300 WRMS or roughly 3× lower than a conventional design, at thefull 2 kW load power, as shown in Fig. 5(b). The value of Cbus

can be further reduced by processing more power in the APDstage. In this design, the chosen capacitor values and thermaloverhead imposed by the losses in the APD stage gives thebest trade-off for optimized volume. Experimental validationof the APD stage is outside the scope of this paper.

III. THERMAL DESIGN

The main design objectives for the thermal design are to1) achieve a uniform heat distribution inside the enclosure,2) take advantage of the two main heat transfer modes,

convection and radiation.The design approach maximizes heat removal through forcedconvection, and distribute it evenly across the outer surfaces.This leads to maximized free convection and radiation in orderto limit the temperature of outer enclosure and exhaust air to60oC.

A vertical tower shape was chosen, as shown in Fig. 6(a),with an aspect ratio that optimizes both free convection fromthe outer surfaces as well as the time-of-residence of theair flow inside the device. Active cooling through forcedconvection, custom heat spreaders and copper heat-pipes wereused to achieve a volume of a volume of 33.1 in3. Thisresults in a power-density of 60.34 W/in3 with the 650 V GaNdevices, assuming 100 W of total losses at the full load of 2kW, corresponding to an efficiency of 95%.

A. Enclosure-level Cooling

The enclosure is made from pure copper with optimized airinlets and outlets. The aspect ratios were chosen to increaseavailable surface area from the side faces for convection andradiation, while leaving adequate height for proper forcedconvection. For better thermal management, the device isdivided vertically into two stages: the EMI filter and buscapacitance are placed at the bottom, and the power boardsand inductors are placed in the upper stage. The PCBof the auxiliary power supply separates the two stages; it

!

!

!

!

!

!

!

!

Fig. 7. 3D drawing of the

Heat sink assembly

Power stages/sub-

inverters

Air guidance and

auxiliary power PCB

EMI Filters, Input capacitor

and capacitor bank

for active power

decoupling

of the enclosure.

Input capacitor

Inductors

(a)!"#$%&"$'( )*+%&"$'(

!,-%".&$/0$/(1234235(

(b)

Fig. 6. (a) 3D CAD model of the outer and inner assemblies (top fan removedto show the internal design). (b) Partially assembled inverter and power-stage.

has a circular cut-out in the center to allow air flow. Ahigh-performance heat-pipe is placed at the center of theinverter, as shown in Fig. 6, to balance heat in the two stages,improving heat distribution uniformity inside the box.

B. Power-board and Passive Component Cooling

Each sub-inverter is implemented with two back-to-back2×2 inch PCBs; a control board and a power board. A specialPCB fabrication process was used to reduce the power boardthickness to 0.5 mm while maintaining 4 oz./ft2 copper weightto improve back-side cooling and reduce the conductionlosses. A modular concept was used for efficient componentspace utilization, uniform heat distribution, and to easethe coordination of the multi-disciplinary electrical-thermaldesign effort. All power boards are mounted vertically tothe sides of the enclosure and attached to low profile, purecopper heat-sinks with embedded heat-pipes. The eight powerinductors attach to a central heat sink with spacers. The EMIfilter coils are attached to a small heat-sink that connects to acentral heat pipe. Power transistors are cooled from the bottomside via the PCB to the heat-sink and from the upper side viaa thermally conductive heat spreader. An exhaust air fan on

(a)

(b)

Fig. 7. (a) Simulated temperature contours for the outer enclosure at therated power. (b) Air velocity 2 mm outside the box.

the top of the box, and two smaller intake fans at the bottomare used for active cooling. The fans consume 3.5 W in total.Extensive thermal simulations of the full system were donein ANSYS, including all major power-dissipating electroniccomponents, a faithful representation of internal componentsand air flow paths, and the power flow curves of the fans.

Thermal simulations show that with a maximum distributedpower loss of 100 W, the surface temperature of theenclosure would be less than 40oC, with the maximum surfacetemperature of 55.2oC at the air outlet as shown in Fig. 7(a).The air velocity vectors reach 4.65 m/s at the air outlet asshown in Fig. 7(b).

IV. EXPERIMENTAL RESULTS

The experimental results are based on the 900V, 65 mΩ SiCdevices. A single sub-inverter with SiC transistors is shown

in Fig. 8. A bus voltage of 400 V is used throughout themeasurements. The trade-off between high efficiency and lowTHD is explored in detail.

An FPGA controller is used for maximum flexibility in thisinitial project phase, however the long-term objective is todeploy the controller on a highly integrated ASIC that includeall the on-chip mixed-signal circuits for high-performancecurrent-mode control [19].

Fig. 8. Single power-stage with SiC devices mounted to heat-sink.

0

Vhigh

Vlow

CCM BCM

1/120Hz

(a)

IL

Vsense

comp_high

comp_low

ΔIpk

+Ivly

+I

(b)

Fig. 9. Current mode waveforms (a) peak and valley envelopes for inductorcurrent for a line cycle in dual-mode (BCM/CCM) operation and (b) IL andIR with corresponding comparator output signals in BCM operation.

A. Inverter implementationThe ideal inductor waveforms shown in Fig. 4 and Fig. 3

are realized with a pair of 12-bit DACs that shape the inductor

(a)

(b)

Fig. 10. Sub-inverter operation (a) in BCM at 330 W (47% rated power)and (b) in dual-mode BCM/CCM operation at 632.7 W (95% rated power).

peak and valley current envelopes. The Vhigh and Vlow DACoutputs that shape Ipk and Ivly over the ac line cycle are shownin Fig. 9(a) for dual-mode operation. The inductor current ILand the sensed IR signal Vsense, along with correspondingcomparator outputs, are shown in Fig. 9(b).

To avoid switching frequencies above 500 kHz at thezero crossings, a zero-current region is imposed, and ∆I ismaintained to 2 A. The presence of the zero-current regionintroduces nonlinearity to (3) that adds undesirable THD toIavg .

A measured voltage THD of 5.3% is achieved for asub-inverter processing 330W, 47% of rated power, in BCMoperation, as shown in Fig. 10(a). At high load power, thesub-inverter spends a smaller portion of the line cycle withinthe zero-current region, resulting in a lower THD. A voltageTHD of 4.5% is achieved for a sub-inverter processing 632.7W, 95% of load power, in dual-mode operation as shown inFig. 10(b).

The measured output voltage THD versus load power isshown in Fig. 11(a), where Ipk directly follows the modulationdefined by (3). This modulation is referred to as Scheme 1.The THD is ≥ 6% at 177.7 W and falls below 5% above 200W. The average THD is 4.2%, while a THD of 3% is achievedat the highest load level of 600 W. The sub-inverter efficiencyis shown in Fig. 11(a). The weighted CEC efficiency is 95.4%,and the efficiency falls below 95% above 550 W.

B. Efficiency optimization

Two avenues for inverter efficiency optimization areexplored through:

150 200 250 300 350 400 450 500 550 60094

95

96

97

98

99

Output power [W]

Eff

icie

ncy

[%

]

150 200 250 300 350 400 450 500 550 6001

2

3

4

5

6

7

TH

D[%

]

BCM only

Dual BCM/CCM

Peak efficiency

THD

(a)

0 100 200 300 400 500 600 70094

95

96

97

98

99

Output power [W]

Eff

icie

ncy [

%]

0 100 200 300 400 500 600 7004

5

6

7

8

9

10

TH

D[%

]

BCM only

Dual BCM/CCM

Peak efficiency

THD

(b)

Fig. 11. Efficiency and THD versus load in pure BCM and dual BCM/CCMoperation for Iavg modulation for (a) Scheme 1, optimized for THD and (b)Scheme 2, optimized for efficiency.

1) modifying the Iavg modulation to trade off THD forefficiency, and

2) optimizing the transition between BCM and CCMmodes.

The trade-off between THD and efficiency can be exploredby modifying (3) to

Ipk = 2(Iavg) + C, (6)

where C, an adjustable constant, replaces 2Ivly in theoriginal equation. For the same Iavg , a C value of less than2Ivly lowers Ipk and inductor ripple current, ∆I , which resultsin less inductor core losses and higher THD. This is referred toas Scheme 2. With the adjustment, a 3% increase in efficiencyis achieved at 600 W load power while maintaining sub-5%THD.

The efficiency and voltage THD versus load power areshown in Fig. 11(b) for Scheme 2. The CEC efficiency forScheme 2 is 1.9% higher than for Scheme 1 CEC efficiency,however the average THD in Scheme 2 is 6.31%.

As expected, BCM is more efficient at low output powerdue to the soft-switching, while CCM operation is moreefficient for high loads with smaller inductor ripple currents, as

(a)

(b)

Fig. 12. Thermal capture of inductors (left) and power-stage (right) (a)processing 170-W, 25% of rated power in BCM operation only and (b)processing 600-W, 90% of rated power in dual-mode BCM/CCM operation.

shown in Fig. 11(b). The optimum transition from pure BCMoperation to dual BCM/CCM operation occurs around 350 W,which corresponds to a ∆I of approximately 6 A, the inductorsaturation current. For load power below 350 W, efficiency indual-mode operation drops below 96%.

The measured thermal profile of the sub-inverter showsthat the inductor core losses make up a majority of losses inBCM operation, as depicted in Fig. 12(a). The SiC MOSFETsremain below 40oC, while the inductor cores heat to 67.9oC.When the sub-inverter processes 632.7 W (95.9% rated power)at 97.7% efficiency in dual-mode operation, the MOSFETsheat up to 57.6oC due to partial hard-switching, and theinductors cool to near 50oC, as shown in Fig. 12(b).

The sub-inverter controller can optimize for efficiency andTHD by modifying the Iavg modulation scheme depending onthe load power, while maintaining the BCM/CCM transitionlevel at 350 W. By utilizing scheme 1 and 2 for underand above 320 W load power, respectively, the sub-inverterachieves CEC efficiency of 96.5% with an average THD of4.8%, as shown in Table. I. The input voltage is measured fora single sub-inverter with a 330 µF electrolytic capacitor onVbus and a 10 Ω resistor in series with Vin and Vbus, withoutAPD.

The parallel operation of two sub-inverters is demonstratedin both pure BCM and dual-mode operation as shownin Fig. 13. Future work will include efficiency and THD

TABLE IEXPERIMENTAL SIC SUB-INVERTER SPECIFICATIONS

Parameter Value UnitInput voltage, Vin 400 VDC

Output voltage, Vac 240 VRMS

Peak output power 667 WInput voltage ripple 15 Vpp

CEC efficiency 96.5 %Peak efficiency (318.8 W) 97.9 %Average voltage THD 4.8 %

optimization with three sub-inverters in parallel, with theoption to use phase-shedding to optimize efficiency over theload range.

Vac

IL1

IL2

(a)

Vac

IL1

IL2

(b)

Fig. 13. Parallel sub-inverter operation in (a) pure BCM operation and (b)dual-mode operation.

V. CONCLUSIONS AND FUTURE WORK

A HCMC dual-mode scheme was presented anddemonstrated. An efficiency of 97.7% is achieved for632.7 W (95% of rated load) with 4.5% THD for a singleSiC based sub-inverter. A weighted CEC efficiency of96.5% and an average THD of 4.8%, are achieved for theload power between 100 W and 632 W. The original GaNbased inverter has a volume of 33.1 in3 and can achieve atheoretical power density of 60.3 W/in3 while maintainingan enclosure temperature below 60oC, based on thermalsimulations. Adapting the original GaN-based mechanicaldesign to accommodate the larger SiC transistors results in anincreased volume to 39.6 in3, and a decreased power-densityof 50.5 W/in3. An optimized mechanical platform for themodular inverter was designed and assembled. Future workincludes experimental realization of the full three parallel

sub-inverter solution, as well as implementation of the activepower decoupling circuit using the same SiC power-stage andinductors.

ACKNOWLEDGEMENTS

This work was supported by Solantro Semiconductor andthe Ontario Centres of Excellence.

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