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  • The SPARC Architecture Manual

    Version 9

    SPARC International, Inc. San Jose, California

    David L. Weaver and Tom Germond

    Editors

    SA-V09-R147-Jul2003

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    The SPARC Architecture Manua

    Version 9

    SPARC International, Inc. San Jose, California

    David L. Weaver / Tom Germond

    Editors

    SA-V09-R147-Jul2003

    PT R Prentice Hall, Englewood Cliffs, New Jersey 076

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    SPARC® is a registered trademark of SPARC International, Inc.

    The SPARC logo is a registered trademark of SPARC International, Inc.

    UNIX® is a registered trademark of UNIX System Laboratories, Inc.

    Copyright © 1994 SPARC International, Inc.

    Published by PTR Prentice Hall Prentice-Hall, Inc. A Paramount Communications Company Englewood Cliffs, New Jersey 07632

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    Printed in the United States of America

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    ISBN 0-13-825001-4

    PRENTICE-HALL INTERNATIONAL (UK) LIMITED, London PRENTICE-HALL OF AUSTRALIA PTY. LIMITED, Sydney PRENTICE-HALL CANADA INC., Toronto PRENTICE-HALL HISPANOAMERICANA, S.A.,Mexico PRENTICE-HALL OF INDIA PRIVATE LIMITED, New Delhi PRENTICE-HALL OF JAPAN, INC., Tokyo SIMON & SCHUSTER ASIA PTE. LTD., Singapore EDITORA PRENTICE-HALL DO BRASIL, LTDA., Rio de Janeiro

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    Contents

    Introduction ............................................................................................................. 0.1 SPARC .................................................................................................... 0.2 Processor Needs for the 90s and Beyond ................................................ 0.3 SPARC-V9: A Robust RISC for the Next Century ................................

    0.3.1 64-bit Data and Addresses ....................................................... 0.3.2 Improved System Performance ................................................ 0.3.3 Advanced Optimizing Compilers ............................................ 0.3.4 Advanced Superscalar Processors ............................................ 0.3.5 Advanced Operating Systems .................................................. 0.3.6 Fault Tolerance ........................................................................ 0.3.7 Fast Traps and Context Switching ........................................... 0.3.8 Big- and Little-Endian Byte Orders .........................................

    0.4 Summary .................................................................................................

    Editors’ Notes .......................................................................................................... Acknowledgments ............................................................................................... Personal Notes ....................................................................................................

    1 Overview ............................................................................................................ 1.1 Notes About this Book ............................................................................

    1.1.1 Audience .................................................................................. 1.1.2 Where to Start .......................................................................... 1.1.3 Contents ................................................................................... 1.1.4 Editorial Conventions ..............................................................

    1.2 The SPARC-V9 Architecture ................................................................. 1.2.1 Features .................................................................................... 1.2.2 Attributes .................................................................................. 1.2.3 System Components ................................................................ 1.2.4 Binary Compatibility ............................................................... 1.2.5 Architectural Definition ........................................................... 1.2.6 SPARC-V9 Compliance ..........................................................

    2 Definitions ..........................................................................................................

    3 Architectural Overview .................................................................................... 3.1 SPARC-V9 Processor .............................................................................

    3.1.1 Integer Unit (IU) ......................................................................

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    3.1.2 Floating-Point Unit (FPU) ...................................................... 3.2 Instructions ..............................................................................................

    3.2.1 Memory Access ....................................................................... 3.2.2 Arithmetic/Logical/Shift Instructions ...................................... 3.2.3 Control Transfer ....................................................................... 3.2.4 State Register Access ............................................................... 3.2.5 Floating-Point Operate ............................................................. 3.2.6 Conditional Move .................................................................... 3.2.7 Register Window Management ................................................

    3.3 Traps .......................................................................................................

    4 Data Formats ..................................................................................................... 4.1 Signed Integer Byte ................................................................................. 4.2 Signed Integer Halfword ......................................................................... 4.3 Signed Integer Word ............................................................................... 4.4 Signed Integer Double ............................................................................ 4.5 Signed Extended Integer ......................................................................... 4.6 Unsigned Integer Byte ............................................................................ 4.7 Unsigned Integer Halfword ..................................................................... 4.8 Unsigned Integer Word ........................................................................... 4.9 Unsigned Integer Double ........................................................................ 4.10 Unsigned Extended Integer ..................................................................... 4.11 Tagged Word .......................................................................................... 4.12 Floating-Point Single Precision .............................................................. 4.13 Floating-Point Double Precision ............................................................. 4.14 Floating-Point Quad Precision ................................................................

    5 Registers............................................................................................................. 5.1 Nonprivileged Registers ..........................................................................

    5.1.1 General Purposer Registers ..................................................... 5.1.2 Specialr Registers ................................................................... 5.1.3 IU Control/Status Registers ..................................................... 5.1.4 Floating-Point Registers .......................................................... 5.1.5 Condition Codes Register (CCR) ............................................ 5.1.6 Floating-Point Registers State (FPRS) Register ...................... 5.1.7 Floating-Point State Register (FSR) ........................................ 5.1.8 Address Space Identifier Register (ASI) ................................. 5.1.9 TICK Register (TICK) .............................................................

    5.2 Privileged Registers ................................................................................ 5.2.1 Processor State Register (PSTATE) ........................................ 5.2.2 Trap Level Register (TL) ......................................................... 5.2.3 Processor Interrupt Level (PIL) ............................................... 5.2.4 Trap Pro