THE SPARC ARCHITECTURE:

THE SUPERSPARC MICROPROCESSOR

Presented ByOZAN AKTAN

ozan.aktan@boun.edu.tr

THE OUTLINE INTRODUCTION THE SPARC PROCESSOR

The Modules Integer Unit (IU)

The Register Window Concept Floating Point Unit (FPU) Coprocessor

Instructions Traps

THE SUPERSPARC PROCESSOR System Interconnect IU Capabilities FPU Capabilities Cache & Memory Organization

CONCLUSIONS

INTRODUCTION

SPARC stands for Scalable Processor ARChitecture.

SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II designs engineered at the University of California at Berkeley from 1980 through 1982.

SPARC is a CPU instruction set architecture (ISA), derived from a Reduced Instruction Set Architecture (RISC).

The SPARC architecture is a public property in the sense that the semiconductor manufacturers are encouraged to produce their own implementation of the SPARC architecture.

THE DESIGN GOALS

Provide the scalability of the cost/performance ratio of successive implementations with the current improvements in circuit technology.

Construct a simple instruction set, well-matched to compiler technology, allowing for implementations with very high MIPS rates and short development cycles.

Enable easily pipelined, cost-effective, high-performance implementations across a range of device integration levels and technologies.

THE SPARC PROCESSOR

The SPARC processor is divided into three parts: an Integer Unit (IU) a Floating-Point Unit (FPU) an optional CoProcessor (CP), each with its own

registers. (32-bits wide). The SPARC processor can be in either of 2 modes:

Supervisor mode: The processor can execute any instruction, including the privileged instructions.

User mode: “User Application” programs will be executed in user mode.

THE MODULES

Integer Unit (IU)

Floating-Point Unit

(FPU)

CoP

rocessor

(CP

)

THE MODULES

Integer Unit (IU)

Floating-Point Unit

(FPU)

CoP

rocessor

(CP

)

THE MODULES

Integer Unit (IU)

Floating-Point Unit

(FPU)

CoP

rocessor

(CP

)

THE MODULES

Integer Unit (IU)

Floating-Point Unit

(FPU)

CoP

rocessor

(CP

)

THE INTEGER UNIT (IU)

Contains the general purpose registers and controls the overall operation of the processor.

Executes the integer arithmetic instructions and computes memory addresses for loads and stores.

Maintains the program counters and controls instruction execution for the FPU and the CP.

May contain from 40 to 520 general-purpose 32-bit registers which corresponds to a grouping of the registers into 8 global registers and a circular stack of from 2 to 32 sets of 16 registers, known as register windows.

Integer Unit (IU)

THE REGISTER WINDOW CONCEPT

Each instruction can access the 8-globals and a register window into the 24 registers.

A register window comprises a 16-register set- divided into 8 in and 8 local registers- together with the 8 in registers of an adjacent register set, addressable from the current window as its out registers.

Integer Unit (IU)

THE REGISTER WINDOW CONCEPT (CONT.)

The active window is identified by the 5-bit Current Window Pointer (CWP).

Decrementing the CWP at procedure entry causes the next window to become active.

Incrementing the CWP at procedure entry causes the previous window to become active.

Register window overflow and underflow conditions are handled in software by a kernel trap handler.

The Window Invalid Mask (WIM) can tag any window so that an overflow or underflow trap is generated whenever the CWP is about to point a tagged window.

Integer Unit (IU)

THE ADVANTAGES OF USING MULTIPLE WINDOWS

Make very fast procedure calls as they avoid the need to save a processor’s current in memory, further reducing off-chip traffic.

Instead, the state variables are held in the current window, and the next window is opened for the new procedure.

A refinement on this idea in that the input and output registers of adjacent windows overlap, allowing variables and parameters to be passed to the next process without physically moving data.

Integer Unit (IU)

THE SPARC’s CIRCULAR REGISTER WINDOWS

The additional registers are hidden from view until you call a subroutine or other function. Where other processors would push parameters on a stack for the called routine to pop off, SPARC processors just "rotate" the register window to give the called routine a fresh set of registers.

The old window and the new window overlap, so that some registers are shared.

Integer Unit (IU)

THE FLOATING-POINT UNIT (FPU)

The FPU has thirty-two 32-bit-wide registers. Double-precision values occupy an even-

odd pair and extended-precision values occupy an aligned group of four registers.

The FPU’s registers are accessed externally only via load and store instructions; there is no direct path between the IU and the FPU.

If the enable floating-point (EF) bit in the PSR is 0, an attempt to execute a floating point instruction will generate an fp-disabled trap.

Floating-Point Unit

(FPU)

THE COPROCESSOR

The coprocessor instructions mirror the floating-point instructions ;

Load/store coprocessor, Branch on coprocessor condition codes, Coprocessor operate (CPop).

Coprocessor operate instructions can execute concurrently with integer instructions.

The coprocessor unit has its own set of 32-bit registers.

The actual configuration of registers is implementation-dependent.

CoProcessor (CP)

INSTRUCTIONS

Instructions fall into six basic categories: Load/Store Arithmetic/Logical/Shift Control Transfer Read/Write Control Register Floating-point Operate Coprocessor Operate

TRAPS

A trap is an unexpected procedural call. Traps

decrement the CWM to the next register window.

cause the hardware to write the trapped program counters and state of the registers into the local registers of the new window.

A comparison is made between the interrupt request level (bp_IRL) and the processor interrupt level (PIL) field of the PSR.

A CASE STUDY: The SuperSPARC Microprocessor

A highly integrated superscalar microprocessor fully compatible with the SPARC v8 architecture.

The processor contains an integer unit, double precision floating

point unit, fully consistent instruction

and data caches a SPARC reference memory

management unit a dual mode bus interface

supporting either the SPARC standard MBUS, or an interface optimized for connection to a companion second level cache controller chip.

SYSTEM INTERCONNECT

The dual bus interface allows for systems to be designed either with or without an external cache.

Processor modules, are constructed of the SuperSPARC processor and optionally an external cache built from synchronous SRAM and the SuperSPARC cache controller chip.

The primary bus used by these modules is the “Level2” SPARC Mbus which is a 64-bit multiplexed, cache consistent bus interface specification.

INTEGER UNIT CAPABILITIES

The integer unit dynamically selects “a group” of up to three instructions in each cycle.

This is accomplished by grouping logic which scans the next available instructions, and selects from zero to three for execution.

The remaining instructions from either the sequential or target instruction queue are recirculated back into the sequential target queue.

INTEGER EXECUTION ORGANIZATON

Allows for most combinations of independent, as well as dependant integer operations to be completed.

Memory reference address calculations are performed using a dedicated set of register file ports, and a dedicated virtual address adder.

The virtual address is then used by the cache and MMU to access load/store data.

BASIC INTEGER PIPELINE OPERATION

Reads instructions from the instruction cache

Determines instruction grouping

Allocates ALU and register file ports

Reads ALU operands from the register file.

Updates the integer register file with the proper results.

1st stage of integer execution, which accounts for the 1st level of ALU

Cascaded ALU operations in the 2nd level ALU

FLOATING POINT UNIT CAPABILITIES

Capable of executing single and double precision floating point operations.

Optimized for double precision operations. The FPU provides a 4-entry floating point

instruction queue and a five port floating point register file.

One unique feature of the FPU is that dependant floating point instructions may be issued in the same instruction group. An example is given below.

CACHE & MMU OPERATION

SuperSPARC uses fully physically addressed caches.

The caches are organized as set associative caches, each set of the cache is required to be equal to the minimum page size. (4KBytes)

The Caches are accessed in parallel with the MMU.

CONCLUSIONS

The SPARC architecture allows for high performance processor and system implementations at a variety of technology points

The SPARC Architecture is presented. The basic modules of SPARC processor, namely the

integer, floating point and coprocessor units are studied, in detail.

The register window concept, which differs the SPARC processor from other processors is described.

The internal operation and capabilities of SuperSPARC microprocessor has been given.

REFERENCES

The SPARC Architecture Manual Version 8, Sun Microsystems

The SuperSPARC microprocessor, Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers. , 24-28 Feb. 1992 Pages:136 – 141

Bright Sparc [RISC-based microprocessor], IEEE Review, Volume: 36, Issue: 9, 4 Oct. 1990 Pages:331 – 335

The Scalable Processor Architecture (SPARC), Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers , 29 Feb.-3 March 1988 Pages:278 - 283

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