The Single-Cycle Datapath and Control Unit (Lecture #10) ECE 445 – Computer Organization The...

The Single-Cycle Datapath and Control Unit

(Lecture #10)

ECE 445 – Computer Organization

The slides included herein were taken from the materials accompanying Computer Organization and Design, 4th Edition, by Patterson and Hennessey,

and were used with permission from Morgan Kaufmann Publishers.

Fall 2010 ECE 445 - Computer Organization 2

Material to be covered ...

Chapter 4: Sections 1 – 4

Appendix D: Sections 1 – 3, 5


Introduction CPU performance factors

Instruction count Determined by ISA and compiler

CPI and Cycle time Determined by CPU hardware

We will examine two MIPS implementations A simplified version - single-cycle A more realistic version - pipelined

Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j

§4.1 Introduction


Instruction Execution

PC instruction memory, fetch instruction ALL instructions must be fetched

Register numbers register file, read registers ALL instructions must be decoded

Depending on instruction class Use ALU to calculate

Arithmetic result Memory address for load/store Branch target address

Access data memory for load/store PC target address or PC + 4


CPU Overview (Datapath)


Multiplexers Can’t just join wires

together Use multiplexers


CPU Overview (Control)


Logic Design Basics§4.2 Logic D

esign Conventions

Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses

Combinational element Operate on data Output is a function of input

State (sequential) elements Store information


Combinational Elements

AB

Y

I0I1

YMux

S

MultiplexerY = S ? I1 : I0

A

B

Y+

A

B

YALU

F

AdderY = A + B

Arithmetic/Logic UnitY = F(A, B)

AND-gateY = A & B


Sequential Elements Register: stores data in a circuit

Uses a clock signal to determine when to update the stored value

Edge-triggered: update when Clk changes from 0 to 1

D

Clk

Q

Clk

D

Q

What if the D Flip-Flop must retain its current value (rather than store a new one)?


Sequential Elements Register with write control

Only updates on clock edge when write control input is 1

Used when stored value is required later

D

Clk

Q

Write

Write

D

Q

Clk

How is the Write (enable) signal implemented?


Clocking Methodology

Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period


Building a Datapath Datapath

Elements that process data and addressesin the CPU

Registers, ALUs, mux’s, memories, …

Control Unit Controls the behavior of the elements that

comprise the datapath

We will build a MIPS datapath incrementally Refining the overview design

§4.3 Building a D

atapath


Instruction Fetch

32-bit register

Increment by 4 for next

instruction

Program Counter (aka. Instruction Address Register)

Stored ProgramComputer


R-Format Instructions

Some examples: add $s0, $t1, $t0 sub $s3, $s1, $t1 and $t2, $t3, $s1 or $t5, $s6, $s7 sll $t1, $t0, 3


R-Format Instructions

Read two register operands (rs and rt) Perform arithmetic/logical operation Write register result (rd)


Load/Store Instructions

These are I-Format instructions Some examples:

lw $s0, 32 ($t1) sw $s1, 40 ($t2)


Load/Store Instructions Read register operands Calculate address using 16-bit offset

Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory


Branch Instructions

These are I-Format instructions Some examples:

beq $s2, $t3, L1 bne $t3, $t4, Else


Branch Instructions

Read register operands Compare operands

Use ALU Subtract and check Zero output

Calculate target address Sign-extend displacement Shift left 2 bits (word displacement) Add to PC + 4

Already calculated by instruction fetch

What does theZero output indicate?


Branch Instructions

Justre-routes

wires

Sign-bit wire replicated


Composing the Elements Simple datapath does an instruction in one

clock cycle Each datapath element can only do one function at

a time Hence, we need separate instruction and data

memories Read instruction memory (every instruction must be

fetched) Read or Write data memory (for lw and sw,

respectively)

Use multiplexers where alternate data sources are used for different instructions


R-Type/Load/Store Datapath


R-Type Instructions

ControlUnit

[31..26] control signals

[31..0]

[25..21]

[20..16]

[15..11]

rs

rt

rd


Example: add $s0, $t0, $t1

add

$s0

$t1

$t0[$t0]

[$t1]

[$t0] + [$t1]

[$t0] + [$t1]


Example: sub $s3, $s2, $s1

sub

$s2

$s1

$s2[$s2]

[$s1]

[$s2] - [$s1]

[$s2] - [$s1]


Example: and $t0, $s1, $s2

and

$t0

$s2

$s1[$s1]

[$s2]

[$s1] & [$s2]

[$s1] & [$s2]


Example: or $s5, $t3, $s3

or

$s5

$s3

$t3[$t3]

[$s3]

[$t3] | [$s3]

[$t3] | [$s3]


Example: sll $s3, $t1, 2

sll

$s3

Can the shift operations be implemented with this datapath?

$t1


R-Type/Load/Store Datapath

Which datapath components are not required for R-type instructions?


Questions?

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