Von Neumann Architecture

MainMemory

OutputDevices

InputDevices

BackingStorage

The ProcessorArithmetic and Logic Unit (ALU)

Carries out calculations e.g.

10110011+ 11110010

Performs logical operations e.g. AND, OR, NOT

ALU

The Processor

ALUControl

Unit

Control Unit

Manages the fetchingdecodingandexecutingof instructions

The Processor

ALUControl

Unit

MemoryData

Register

MemoryAddressRegiste

rOther

Registers

Registers

Very fast temporary storage locations which hold:

• data being processed

• instructions being executed

• addresses of memory locations to be accessed

The Processor

ALUControl

Unit

MemoryData

Register

MemoryAddressRegiste

rOther

Registers

Internal Buses

Used to transmit information

The Processor & Main Memory

ALUControl

Unit

MemoryData

Register

MemoryAddressRegiste

rOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

32 Lines

Data Bus

16 Lines

Control Bus6

Lines

Each memory location is represented by a unique address.

The Address Bus

MemoryAddressRegister

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

• information is carried from the processor to the main memory

• this informs the main memory which memory location will be read or used to store data

• each wire on the bus carries one bit of information at a time

The Address Bus

MemoryAddressRegister

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

• the number of wires in this bus determines the number of memory locations8 lines will allow 256 memory locations 32 lines will allow 68,719,476,736 memory locations

• increasing the width of this bus, increases the number of memory locations that it is possible to address

The Data Bus

MemoryDataRegister

Processor

Main Memory

11110011

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Data Bus

• information is carried to and from the processor and main memory

• this stores data in a memory location and reads data from a memory location

• each wire on the bus carries one bit of information at a time

The Data Bus

MemoryDataRegister

Processor

Main Memory

11110011

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Data Bus

• the description of the computer informs the user of the number of wires in this busa 32 bit computer has 32 wires on the bus

• increasing the width of this bus, increases the quantity of data that can be carried at one time and so increases the performance of the computer system

The Control Bus

ControlUnit

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Control Bus

Each wire on the bus has its own separate function and is activated independently of the others

ReadInforms the memory that data is to be sent to the processor from a particular memory location

WriteInforms the memory that data is to be stored in a particular memory location

ClockGenerates a constant pulse which regulates the flow of information

A clock of 600MHz (megahertz) generates a pulse 600,000,000 times a second

The Control Bus

ControlUnit

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Control Bus

Each wire on the bus has its own separate function and is activated independently of the others

InterruptA message from a peripheral device causes the processor to stop processing the current task. Current data is stored in a temporary area called the stack. The processor deals with the interrupt. The data is then retrieved from the stack and the task is resumed

ResetClears all internal processor registers and returns the computer to its initial switched on state

The Fetch-Execute CycleTo execute a program you must first load the program and any relevant data in to the computer’s memory (RAM) from disk.

The program and data is stored in memory until needed by the processor (the stored program concept).

A program may contain thousands of instructions but the processor can only execute one instruction at a time.

The first instruction is fetched from memory in to the processor where it is decoded and executed.

Then the second instruction is fetched and then executed and so on until the program ends.

This is known as the FETCH – EXECUTE CYCLE.

Memory Read Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

1. The processor sets up the address bus with the required memory address by placing it in the MAR

Memory Read Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

2. The control unit activates the read line on the control bus

Memory Read Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

3. The address bus opens the relevant memory location at that address

11110011

Memory Read Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

4. The contents of the memory location are released, sent along the data bus and into the MDR

11110011

Memory Read Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

5. The data is then decoded and executed

Memory Write Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

1. The processor sets up the address bus with the required memory address by placing it in the MAR

Memory Write Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

2. The processor sets up the data bus with the value to be stored in memory by placing it in the MDR

Memory Write Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

3. The control unit activates the write line on the control bus

Memory Write Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

4. The address bus opens the relevant memory location at that address

Memory Write Operation

ALUControlUnit

MemoryDataRegister

MemoryAddressRegisterOther

Registers

Processor

Main Memory

Address

00000000000000010000001000000011000001000000010100000110000001110000100000001001

Address Bus

Data Bus

Control Bus

5. The contents of the memory location are released, sent along the data bus and into the memory location

11000111

CreditsHigher Computing – Computer Structure – The Processor

Produced by P. Greene for the City of Edinburgh Council 2004

Adapted by M. Cunningham 2010

All images licenced under Creative Commons 3.0• Intel Insides by Ryan Maclean (rcmaclean on Flickr)