The Processor (2) - AndroBenchcsl.skku.edu/uploads/EEE3050S17/Lec07-proc2.pdf · EEE3050: Theory on...

EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong ([email protected])

The Processor (2)

Jinkyu Jeong ([email protected])Computer Systems Laboratory

Sungkyunkwan Universityhttp://csl.skku.edu

EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong ([email protected]) 2

Announcement• Midterm exam– Plan A• When: ?? (18:00~) on 4/24(Mon) or 4/25(Tue)• Where? #400102 (Semiconductor Bldg.)

– Plan B• When: 13:30 ~ 14:45 on 4/24 (Mon)• Where #26310

– Stay tuned on our class web page– http://csl.skku.edu/EEE3050S17/News

• No class on 4/19 (Wed)• Make-up class on 4/26 (Wed.)


OutlineTextbook: P&H 4.5-4.6

• An Overview of Pipelining

• Pipelined Datapath and Control

3


Pipelining Analogy• Pipelined laundry: overlapping execution– Parallelism improves performance

4

• Four loads:– Speedup

= 8/3.5 = 2.3

• Non-stop:– Speedup

= 2n/0.5n + 1.5 ≈ 4= number of stages


MIPS Pipeline• Five stages, one step per stage

1. IF: Instruction fetch from memory2. ID: Instruction decode & register read3. EX: Execute operation or calculate address4. MEM: Access memory operand5. WB: Write result back to register

54 ICE3003: Computer Architecture | Spring 2012 | Jin-Soo Kim ([email protected])

MIPS Pipeline � Five stages, one step per stage

• IF: Instruction fetch from memory • ID: Instruction decode & register read • EX: Execute operation or calculate address • MEM: Access memory operand • WB: Write result back to register

IF ID EX MEM WB IF ID EX MEM WB

IF ID EX MEM WB ...


Pipeline Performance• Assume time for stages is– 100ps for register read or write– 200ps for other stages

• Compare pipelined datapath with single-cycle datapath

6

Instr Instr fetch Register read

ALU op Memory access

Register write

Total time

lw 200ps 100 ps 200ps 200ps 100 ps 800ps

sw 200ps 100 ps 200ps 200ps 700ps

R-format 200ps 100 ps 200ps 100 ps 600ps

beq 200ps 100 ps 200ps 500ps


Pipeline PerformanceSingle-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)


Pipeline Speedup• If all stages are balanced– i.e., all take the same time– Time between instructionspipelined

= Time between instructionsnonpipelined

Number of stages

• If not balanced, speedup is less

• Speedup due to increased throughput– Latency (time for each instruction) does not decrease

8


Pipelining and ISA Design• MIPS ISA designed for pipelining– All instructions are 32-bits• Easier to fetch and decode in one cycle• c.f. x86: 1- to 17-byte instructions– Few and regular instruction formats• Can decode and read registers in one step– Load/store addressing• Can calculate address in 3rd stage, access memory in 4th stage– Alignment of memory operands• Memory access takes only one cycle

9


Pipeline Summary• Pipelining improves performance by increasing

instruction throughput– Executes multiple instructions in parallel– Each instruction has the same latency

• Instruction set design affects complexity of pipeline implementation

• Subject to hazards– Structure, data, control

10

EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong ([email protected])

PipelinedDatapath andControl

11


MIPS Pipelined Datapath

WB

MEM

Right-to-left flow leads to hazards


Pipeline registers• Need registers between stages– To hold information produced in previous cycle

13


IF for Load


ID for Load


EX for Load


MEM for Load


WB for Load

Wrongregisternumber


Corrected Datapath for Load


IF for Store


ID for Store


EX for Store


MEM for Store


WB for Store


Pipeline Operation• Cycle-by-cycle flow of instructions through the

pipelined datapath– “Single-clock-cycle” pipeline diagram• Shows pipeline usage in a single cycle• Highlight resources used

– c.f. “multi-clock-cycle” diagram• Graph of operation over time

• We will now look at multi-clock-cycle diagram– Also called “waterfall” diagram

25


Multi-Cycle Pipeline Diagram• Form showing resource usage

26


Multi-Cycle Pipeline Diagram• Traditional form

27


Single-Cycle Pipeline Diagram• State of pipeline in a given cycle

28


Pipelined Control (Simplified)

29


Pipelined Control• Control signals derived from instruction– As in single-cycle implementation

30


Pipelined Control

The Processor (2) - AndroBenchcsl.skku.edu/uploads/EEE3050S17/Lec07-proc2.pdf · EEE3050: Theory on...

Documents

Transcript of The Processor (2) - AndroBenchcsl.skku.edu/uploads/EEE3050S17/Lec07-proc2.pdf · EEE3050: Theory on...