The New Single-silicon TFTs Structure for Kink- current Suppression with Symmetric Dual-Gate by...

The New Single-silicon TFTs Structure for Kink-cuThe New Single-silicon TFTs Structure for Kink-current Suppression with Symmetric Dual-Gate by Trrent Suppression with Symmetric Dual-Gate by T

hree Split Floating N+ Zoneshree Split Floating N+ Zones

Dept. of Electrical Engineering, Korea Univ. Dae Yeon Lee

Supervised by Man Young Sung (Korea Univ.)Supervised by Man Young Sung (Korea Univ.)

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Semiconductor & CAD Lab.Semiconductor & CAD Lab. Dae Yeon LeeDae Yeon Lee

Contents

Introduction

Background

Proposal

Simulation & Results

Conclusion

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Introduction

The Conventional Single-Gate TFT

* High On-current

* High Electric Field at the Channel/Drain Junction

* Kink-Effect Premature Breakdown !

The Conventional Dual-Gate TFT

* Low On-current

* Low Electric Field at the Channel/Drain Junction

* Stable I-V Characteristic by Kink-Effect Suppression

Goal is the Mixing of The Merit the each two TFTs

1. Kink-Effect Suppression

2. Improved On-Current

High On-Current Reduction of Kink-Effect+

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Back Ground

Lowering the Electric Field by having Dual-Gate Structure

Lowering the Impact Ionization at the Channel/Drain Junction

Lowering the Generated Holes flowed to Source/Channel Junction

Floating N+ region recombines with

the Holes

Defense the lowering the Electrostatic Potential Barrier at the Source/Channel Junction by the

Holes

Proposed TFT structure achieved the reduction of the Kink-Effect so that stable Drain Current in the

Saturation Region

Defense

PBT action

Parasitic Bipolar Transistor

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Proposal

The Dual-Gate TFT with Floating N+ channel

oxide

Gate Gate

Source DrainN+ N+

16um

400nm

3um

100nm

1um

1.65um

MoMo

1um

1.65um

0.7um

700nm

110nm

N+

2um 2um

Total channel length=10um

400nm

P PP PN+ N+

- Off-Set Region

Electrons inject at the Forward Bias

Middle N+ region length < 1.51 umLowering the Electric Field

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Design Rules

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Simulation & Results

Electrostatic Potential Hole concentration Electric Field Drain Current – Drain Voltage Output Characteristics Output Conductance

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Electrostatic Potential

Conventional

Dual-gate TFT

Proposed

Dual-gate TFT

Conventional

Single-gate TFT

VG = 7 V, VD = 12 V

Lowering potential barrier at the source causes the kink effect.

Proposed TFT’s potential barrier enhanced the potential barrier 5 times than

Single - gate TFT and enhanced 18 % that of conventional dual-gate TFT.

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Electrostatic Potential (Zoom In) VG = 7 V, VD = 12 V

The channel region starts from 4.3 um point

The Potential Barrier value for the each TFTs Value is 0.5 V, 2.3 V, 2.8 V at a 5 um

point which starts floating n+ region

SourceChannel

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Hole Concentration

Conventional

Single-gate TFT

Conventional

Dual-gate TFT

Proposed

Dual-gate TFT

> 1017

High Electric field at Drain Junction causes Impact Ionization so that holes flow to

the source junction through channel -> PBT action

Floating N+ regions recombine with holes so that hole concentration at the source

junction can be reduce.

VG = 7 V, VD = 12 V

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Hole Concentration (Zoom In) VG = 7 V, VD = 12 V


The Hole concentration value for the each TFTs Value is 1017 /cm3, 101 /cm3,

10-1 /cm3 at a 5 um point which starts floating n+ region

SourceChannel

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Electric Field

Conventional

Single-gate TFT

Conventional

Dual-gate TFT

Proposed

Dual-gate TFT

High Electric field at Drain Junction causes kink effect.

The usual approach to reduce this effect is to limit the impact ionization

contribution decreasing the electric field at the drain junction.

VG = 7 V, VD = 12 V

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Electric Field (Zoom In) VG = 7 V, VD = 12 V


The electric field value of each TFT is approximately 105 V, 2.8×102 V, and

2.9×102 V.

Channel Drain

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Drain Current – Drain Voltage Output Characteristics

0.870 mA

0.522 mA

The on-current of the proposed dual-gate TFT is 0.870 mA while that of the

conventional dual-gate TFT is 0.522 mA

This result shows a 67 % enhancement in on-current

1.611 mA

VG = 7 V, VD = 12 V

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Conventional

Single-gate TFT

Conventional

Dual-gate TFT

Proposed

Dual-gate TFT

VG=5 V

VD=10V0.824 mA 0.325 mA 0.508 mA

VG=5 V

VD=12V1.078 mA 0.330 mA 0.522 mA

VG=7 V

VD=10V1.257 mA 0.508 mA 0.862 mA

VG=7 V

VD=12V1.611 mA 0.522 mA 0.870 mA

W/L = 2

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The on-current of the proposed dual – gate TFT

at different gate voltage

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Output Conductance Characteristics

Kink starting point

VG = 7 V, VD = 12 V

Reduction of the Output conductance means the reduction of the kink effect

so that we can get a stable drain current in the saturation region.

The output conductance of the conventional single-gate increases about 8.3 V.

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Conclusion

Lowering the High electric Field at the Drain junction by

Dual – Gate TFT structure

Improved Electrostatic Potential

Reduction of the Hole concentration by the holes recombine with

the Floating N+ region in the channel region

On-Current is 0.870 mA in the saturation region while that of the

conventional dual – gate TFT is 0.522 mA at VG = 7 , VD = 12 V

A stable Output Conductance is accomplished by the reduction

of the kink effect

The New Single-silicon TFTs Structure for Kink- current Suppression with Symmetric Dual-Gate by...

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