The NemeriX G3 chipset : a radiation hardened front end ...
Transcript of The NemeriX G3 chipset : a radiation hardened front end ...
AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright © 2008 NemeriX SA - www.nemerix.com - 1 -
The NemeriX G3 chipset : a radiation hardened front
end for GNSS receivers aimed at space application
Angelo Consoli & Francesco Piazza; NemeriXHannes Schwammschneider; Austrian Aerospace
AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright © 2008 NemeriX SA - www.nemerix.com - 2 -
Outline
• G3 Chipset Requirements
• Microelectronic Technology Selection
• Architecture of the 2 ASICs
• First Space Application using the ASICs
AMICSA 2008; August 31 - September 2; Sintra (Portugal) Copyright © 2008 NemeriX SA - www.nemerix.com - 3 -
NemeriX‘s G3 chipset• The chipset consists of 2 ASICs:
– NJ1007R: RF receiver front end
– NJ1017R: AD DA interface
• Requirements– Multifrequency receiver GPS/Galileo/GLONASS
– High RF performances more important than integration level or costeffectiveness
– Radiation tolerant design for space borne applications
• Technology selection criteria:– Shall have good RF performance.
– Shall be available also in small quantities.
– Shall be either radiation tolerant or allow radiation tolerant circuits to be
designed.
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The G3 chipset• Main Reason for a Chipset:
– Prevent interference between AD converters and sensitive RF circuitry.
• NJ1007R:– Pure analog RF ASIC
– S35, SiGe process
• NJ1017R:– Massive digital ASIC.
– C35 process would be fine. S35 was selected in order to produce NJ1007 and NJ1017 on the same wafer. Main advantages:
• Reduced costs
• Easier qualification process
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System configuration
NemeriX‘s RF front end BB processor
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G3 chipset common parameters
MeV/mg/cm2
84Heavy Ions
krad(Si)120Total Dose
Radiation Tolerance
mA<1 (*)DVDD
mA2AVDDNJ1017R Supply current @ 3.6V
µA110 (*)DVDD
mA13.8AVDDNJ1007R supply current @ 3.6V
V1.6 to
AVDD+0.2DVDD
V2.2 … 3.6AVDD
Supply voltage
Power Supply in active mode
(*) Excluding load
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Package solution: 36-CBGA
0.45 ±0.05
0.72±0.07
1.6
0.3
0.85±0.1
6±0.15
5.6±0.05
4.7±0.08
NJ10xxR
SOLDER LID
42 ALLOY / Solder KC-003
CERAMIC
KYOCERA A473
0.40.8
5x0.8=4
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Process selection• General:
– Thin layers (wells, diffusions, oxides). Thick N-well may improve latch-up.
– Retrograded well or buried layer and epi improve latch-up resistance.
– SOI has no mechanism to generate a latch-up.
– Deep trenches improve latch-up somewhat.
• BJT:– Thin base and emitter more robust than thick base (less β degradation).
– Poly emitter (thinner) more robust than a diffused one.
• MOS:– Thin gate oxide better than thick oxide (less charge trapping, less
device degradation).
– Shorter channel transistors (stronger) give improved SEE resistance.
Process: AMS S35, 0.35µm SiGe HBT
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Microsection of the S35 process (NJ1007R)
Metal 1
Oxide + Vias
Oxide + Vias
Substrate
Metal 2
Oxide + Vias
Metal 3
Oxide + Vias
Thick Metal 4
Passivation
Polymide
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NJ1007R – RF receiver front end
RF
Loop
filter
IF
Loop
filter
SAW
RF-Filter IF-Filter 1 IF-Filter 2
RF LO
inductor
IF LO
inductor
SAW
or LC
AVDD
AVSS
RFin
GNSS
Antenna
C1
L1
L2
L3L4
L5 L6
C2
C3
C4 C5
C6 C7
C8 C9 C10 C11
To ADC,
base-band
processor:2 :4bias
reg
:N2
PFC
log:8
(:4):N1
PFC
LNI
LN
O
RF
N
OIP
OIN
OQP
OQN
AGCI
VB
VBG
RENB IENBRL1 RL2 IL1 IL2RPLL IPLLDIO
RCP
AVDD AVSS
LPF
(15MHz)
I
Q
DBMLNA VGA
RF
P
MIX
N
MIX
P
IF1
N
IF1
P
IF2
N
IF2
P
NJ1007
• Integrated LNA
• External filters
• I/Q outputs
• Die size: 1.2 x 1.0 mm
• Signal Bandwidth < 24MHz
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NJ1007R characteristics
dBm-10IP3
dBm-221 dB compression point
dBc<35PLL spurs
dBc/HzdBc/Hz
dBc/Hz
-85-78
-65
100kHz1kHz
10Hz
IF SSB phase noise
MHz/V250IF VCO sensitivity
dBc/HzdBc/Hz
dBc/Hz
-83-57
-50
100kHz1kHz
10Hz
RF SSB phase noise
MHz/V800RF VCO sensitivity
RF-VCO IF-VCO
dB60Gain control range
dB70AGC amplifier gainIF Strip
dBm-181dB compression point
dB9SSB noise figure
dB25Conversion gain
RF Down-converter
dBm-10IP3
dB1.6Noise figure
dB19Gain
LNA
NJ1007(G3RF)
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NJ1017R – AD DA Interface ASIC• 2 ADCs (for I/Q outputs of NJ1007R)
– 3-bit
– Sampling frequency < 50MHz
• 8-bit DAC (for AGC)
• SPI like interface to the base band processor
• PLL (for sampling clock)
E5 D1 F4
C5
C6
D5
D6
E6
F5
F6
B6
A6
A5
B5 C4 D4 E4 B4 A4 B3 A2 D2 D3C3
F2
E3
F3
E1
E2
F1
C1
C2
A1
B1
B2
A3
From RF
front-end
I-In
Q-In
Loop
filter
From RF
front-end
To bb
processor
(I/Q data
and clock)
To SPI-like
interface
DVDD
in
out
DVDD
AVDDDVDD
C1
C2R1
C3
C4
C5
C6
TCXO
3 I[2:0]
Q[2:0]3
SCK
CKD
VBG
SEL[3:0]
RCP
MISO
CS_B
AVSS
DVDD
:2
:16
DIO
bias
VOSC
8bit AGC
DAC
ADC-3bit
(flash)
Q
ADC-3bit
(flash)
I
:4
:63
PFC
AGCO
AVDD
IIP
IQP
LF
MOSIreg
FREF
DVSS
NJ1017R
IIN
IQN
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NJ1017R characteristics
dBdB
dB
-90-60
-65
1MHz10kHz
100Hz
RF SSB phase noise
MHz25 … 100Frequency Range
VCO, PLL
V0 ... 2.1Output Voltage range
LSB3INL
LSB3DNL
AGC8-bit DAC
dB25SFDR
mVpp700Input Voltage range
MHz<50Max sampling freq.
LSB0.5INL
LSB0.5DNL
3-bit ADC
NJ1017(G3AD)
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NJ1007R chip layout
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NJ1007R chip on CBGA substrate
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Close view of bonded NJ1007R
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Overview of G3 chip set Lot Validation
• Project started in 2007
• Lot Validation based on ESCC9000 including
– Wafer Manufacturing
– Wafer Lot Acceptance including Total Ionizing (TID) Dose testing
– Packaging of Evaluation Lot
– Evaluation Test
– Packaging of Flight Lot
– Screening of Flight Lot
– Lot validation of Flight Lot
• Completion expected early 2009
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G3 chip set First Application
• GPS based Precise Orbit Determination (POD) Receiver for ESA-SWARM Mission
• Down-converts and digitizes the GPS L1 and L2 signals by means of Nj1007R and NJ1017R, RF- and mixed-signal ASICs
• AGGA-2 chips and a LEON processor form the heart of the digital signal processing
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G3 chip set First Application
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G3 chip set First Application
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G3 chip set First Application
• Interfaces– UART (RS-422) TC/TM interface
– MIL-STD-1553B TC/TM interface extension
• Electronic Box– Box Size: 322x240x104 mm3
– Weight: < 3.5 kg including antenna
– Power Consumption: < 10W
• Antenna– Patch Excited Cup Antenna with improved multipath suppression from
Saab Space
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Conclusions
• G3 Chipset consists of RF Front-End and AD Converter
• Chipset is Radiation Tolerant (120 krad(Si); 84 MeV/mg/cm2)
• G3 ASICs are Being Qualified to ESCC9000
• First Application for SWARM Mission (under construction)
Thank you for your attentionThank you for your attention