The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The...
Transcript of The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The...
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The InverterThe Inverter
References:Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCBPerspective, J. Rabaey, Prentice Hall © UCBPrinciples of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
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Regions of OperationRegions of Operation
Cutoff Non-saturated Saturated
Vgsp < VtpVin < Vtp + VDDVgsp > Vtp
Vgsp = VtpVin < Vtp + VDD
Cutoff Non saturated Saturated
p-devicein tp DD
Vdsp > Vgsp - VtpVout > Vin - Vtp
gsp tp
Vin > Vtp + VDD
in tp DD
Vdsp < Vgsp - VtpVout < Vin - Vtp
Vgsn > Vtn Vgsn > VtngVin > Vtn
Vdsn < Vgs - VtnV V V
Vgsn < Vtn
Vin < Vtn
n-device
gVin > Vtn
Vdsn > Vgs - VtnV V VVout < Vin - Vtn Vout > Vin - Vtn
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Digital GatesDigital Gates Fundamental Parameters
• Area and Complexity• Robustness and Reliability• Performance• Power Consumption
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Noise in digital Integrated Circuits
unwanted variations of voltages and currents at the logic nodes
v(t)VDD
g g
i (t)
v(t)
(a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise
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DC Operation: V lt T f Ch t i ti (VTC)Voltage Transfer Characteristic (VTC)
Voutout
VOHVout = Vinf
VM Switching Threshold Voltage
VOL
M(≠ Transistor Threshold Voltage)
VOL
VOL VOH Vin
Nominal Voltage Levels
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Mapping between analog and digital signals
V(y)
‘1’ VOH
V1H
V(y)
VOHSlope = -1 = )(gain
dVdV
in
out
UndefinedRegion
V outdV‘0’
VIL
VOL VOL
V V
Slope = -1 = indV
VIL VIH V(x)
Undefined Region(Transition width TW)
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Definitaion of Noise MarginsDefinitaion of Noise Margins
‘1’NMH = VOH -V
NMVOH
1 VIH
NMH VIH
UndefinedRegion
NMLVI
LVO
L‘0’ NML = VIL - VOL0
Gate InputStage M+1
Gate OutputStage M
NML VIL VOL
Stage M+1Stage M
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The Regenerative Property
V0
V1
V2
V3
V4
V5
V6
A chain of inverters
5
3V
0
1 V1
V2
-10 2 4 6 8 10
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Conditions for Regeneration
VVout
f(v) finv(v)
Vout
V3
fi ( )
V1f(V0) V1
V3finv(v)
f(v)
VinVV Vin
(a) Regenerative gate (b) Non-regenerative gate
VinV0V2 V0 V2
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Fan-in and Fan-out
( ) F t N(a) Fan-out N
M
N
(b) Fan-in M
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The Ideal Gate
VVout
g = -∞
Ri = ∞
Ro = 0 g = -∞ o
Vin
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VTC of Real Inverter
5.0
VDD
NML4.0
3.0
2 0V out(V
)
NMH
VM
1.0
2.0
0.0 1.0 2.0 3.0 4.0 5.0
V (V)Vin (V)
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Delay Definitionsy
Vin
50%
t
tpHLtpLH
V t
90%
50%
Vout
50%
10% t
tf tr
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Ring Oscillator
V0 V1 V2 V3 V4 V5
V0 V1 V5
T = 2 x t x NT = 2 x tp x N2Ntp >> tf + tr
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Power Dissipation
P(t) = instantaneous power
Ppeak = ipeakVsupply = max (p(t))
∫∫ ==T
ply
T plyav dtti
TV
dttpT
P0 sup0
sup )()(1TT
Power-Delay Product
PDP = tp x Pav
= Energy dissipated per operation= Energy dissipated per operation
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Static Load MOS InvertersStatic Load MOS Inverters
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Static Load MOS Inverters
Rload Ibias
Vout
Vin
Vout
Vin
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Basic Inverter
Vout
VDD
Vin
• Vin < Vth ; NMOS off; Vout pulled to VDDV V NMOS t fl th h R t• Vin > Vth ; NMOS on, current flows through R to ground
• If R is sufficiently large, Vout could be pulled down y g out pwell below Vth;
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St ti L d MOS IN tStatic Load MOS INverter
RIds
Vout
Vout = Vds
Ids.R = VDD-Vds
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VTC of Resistive Load
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Resistive Load Device
Rload Voh = 5.0V
Vol = ???Vout
VinI = (Vdd-Vol)/R
Vol ???
)( VV
I = β.((Vdd-Vt)Vol-0.5Vol2)
)5.0).(()(
2ololtdd
oldd
VVVVVVR
−−−
=β
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Sizing for VOL
)5.0).(()(
2ololtdd
oldd
VVVVVVR
−−−
=β
Assume: Vdd = 5.0VVt = 1.0V
4β = 10-4A/V
Proper design: Vol < Vt
Let: Vol = 0.5V
R = 24kΩR = 24kΩ
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Resistor and Current-Source Loads
R i t /l th f i i idth li f i• Resistance/length of minimum-width lines of various connecting elements is far less than effective resistance of the switched on MOSFET
• In some memory processes, resistors are implemented by highly resistive undoped polysiliconN ll t i t i CMOS t i l t• Normally use transistors in CMOS to implement resistor and current-source loads
• If biased for use as a resistor called an unsaturatedIf biased for use as a resistor, called an unsaturated load inverter
• If load transistor operates in saturation as a constant current source, called a saturated load inverter
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Pseudo NMOS Inverter
Vout
Vin
Ln = 1
Vin
VDD + Vdsp = Vout⇒ Vdsp = Vout - VDDdsp out DD⇒ Vdsp = Vout + Vgsp
∴Vdsp > Vgsp - Vtp or Vout > - Vtpdsp gsp tp out tp⇒ Non-saturated region
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DC Transfer Characteristics
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Pseudo-NMOS InverterPseudo-NMOS Inverter
Vout
Vin
• DC current flows when the inverter is turned on unlike• DC current flows when the inverter is turned on unlike CMOS inverter
• CMOS is great for low power unlike this circuit (e.g. watch needs low power lap-tops etc)
• Need to be turned off during IDDQ (VDD Supply Current Quiescent) testingCurrent Quiescent) testing
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PMOST Load with Constant VGS
Voh = 5.0VVoh 5.0V
Vol = ???
I = 0.5βp.(Vdd-Vtp)2
I = βn.((Vdd-Vtn)Vol-0.5Vol2)Vout
)5.0)(()(5.0
2
2
ololtndd
tpdd
p
n
VVVVVV−−
−=
ββ
Vin
))(( ololtnddpβ
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Sizing for VOL
)(50 2VV)5.0)((
)(5.02
2
ololtndd
tpdd
p
n
VVVVVV−−
−=
ββ
Assume: Vdd = 5.0VVtn = Vtp = 1.0V
Proper design: Vol < Vth
Let V 0 5VLet: Vol = 0.5V
26.4=nβ 6.pβ
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Sizing for Gate Threshold Voltage (Trip Point)Sizing for Gate Threshold Voltage (Trip Point)
N-device: saturated )( tninout VVV −>
2)(2 tninn
dsn VVI −=β
)( tninout
P-device: non-saturated
2
DDgsp VV −=
]2
)())([(2
DDoutDDouttpDDpdsp
VVVVVVI −−−−−= β
Equating the two currents we obtain,Equating the two currents we obtain,
]2
)())([()(2
22 DDout
DDouttpDDptninn VVVVVVVV −
−−−−−=− ββ
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Sizing for Gate Threshold Voltage
Solving for VSolving for Vout
CVVVV tpDDtpout −++−= 2)(
Where C = k (Vin - Vtn)2
nk β=
p
kβ
=
Also22 )()( tpouttpDDn VVVV +−+βAlso, 2)( tnin
pp
p
n
VV −=
ββ
To make gate threshold voltage = 0.5VDDg g DD
11.6=p
n
ββ
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Noise Margin
βn/βp VIL VIH VOL VOH NML NMH
2 3 4 4 5 1 4 5 2 0 0 52 3.4 4.5 1.4 5 2.0 0.54 1.8 3.3 0.6 5 1.2 2.76 1.4 2.8 0.35 5 1.05 3.28 1 1 2 4 0 24 5 0 86 3 68 1.1 2.4 0.24 5 0.86 3.6
100 0.5 1.1 0.00 5 0.5 3.9
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VTC of Pseudo-NMOS Inverter
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Unsaturated Load Inverter
Vout
Vinin
• High is n threshold down from VDD
• Used when depletion mode transistors were not availableavailable
• Low noise margin• Might be used in I/O structures where p-transistorsMight be used in I/O structures where p transistors
were not wanted
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VTC of Unsaturated Load Inverters
For k = 4VOL = 0.24VVIH = 2.2VV 3 8VVOH = 3.8VVIL = 0.56V
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Current Source LoadCurrent Source Load
Ibias
Vout VoutVout
Vin
out
Vin
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Saturated Load Inverter
VoutVVin
• Vout > Vin - Vtn ⇒ driver transistor in saturation– When Vin is small
• Load transistor permanently in saturation• Load transistor permanently in saturation– Vdsp = Vgsp
– ∴Vdsp < Vgsp - Vtp or 0 < - Vtp ⇒ Saturated region
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When Vin is Small
2)( VVI driverβ 2, )(
2tnin VVI driver
driverds −=β
Load in saturation:Load in saturation:
2, )(
2 tpload
loadds VVVI DDout −−−=β
Equating the currents:
)( VVkVVV )( tnintpDDout VVkVVV −++=
where drivenkββ
=loadβ
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VTC of Saturated Load Inverter
For k = 4VOL = 0.24VVIH = 2.1VVOH = 4 4VVOH = 4.4VVIL = 0.5V
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NMOS Inverter
Use depletion mode transistor as pull-up
Vtdep transistor is < 0 VVtdep transistor is 0 Vdiffusion
VDD
Vout
depletion mode transistor (poly)
Vinenhancement modetransistor
out
in
The depletion mode transistor is always ON:gate and source connected ⇒ Vgs = 0
Vin = 0 ⇒ transistor pull down is off ⇒ Vout is high
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Vout vs Vin using Graphical Method
V = 0 0
Ids (dep) Ids (enh)
Vgs = 0.0
Vgs = -0.2 VDD
Vds (dep)VDD
IdsIds Ids
Vgs (dep) = 0
Vgs (dep) VDDV VVds (dep) VDD - Vds (dep)
Vds (enh) = VDD - Vds (dep)Vds (enh) = VoutVDD -Vds(dep) = Vds(enh) = Vout
In a steady state, Ids of both transistors are equal
Vds (enh) VoutTherefore Vout = VDD - Vds (dep)
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Gate Threshold Voltage
Assume that both driver and load are in saturation with input V
Gate threshold voltage = Vinv= Input voltage at which Vin = Vout
Assume that both driver and load are in saturation with input Vinv
2)( )(
2 tgsdriver
satDS VVI −=β
22 )(2
)(2
2
depload
tinvdriver VVV −=−∴
ββ
V
Hence, loaddeptinv VVV
ββ
−=Vout
VDD
driverβ out
Vin
If βdriver is increased relative to βload then,Vinv decreases
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VTC of NMOS inverter
Sl |G| i V dSlope |G| increases, Vinv decreases
load
driver
ββ
increasing
loadβ
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CMOS INVERTER
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CMOS Inverters
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The CMOS Inverter: A First Glance
S
VD
D
V
CL
Vin D Vout
SS
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Switch Model of MOS Transistor
| V| VGS|
| V | | V || VGS | < | VT | | VGS | > | VT |
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CMOS Inverter: Steady State ResponseCMOS Inverter: Steady State ResponseVDDVDD
VOH = VDDV = 0
Ron
Vout
VOL = 0
VM = f(Ronn, Ronp)VM f(Ronn, Ronp)
Vin = VDD Vin = 0
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PMOS Load LinesIDnVin = VDD - VGSp
Idn = -IDPV = V V
Vout
Vout = VDD-VDSp
out
IDp IDn IDnVin = 0
V = 3
Vin = 0
V = 3
VDSp VDSp Vout
Vin = 3 Vin = 3
Vin = VDD + VGSpIDn = - IDp
Vout = VDD - VDSp
VGSp = -2
VGSp = -5
Dn Dp
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Construction Of Inverter Curves
Ids
VdsVds
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Construction Of Inverter Curves
Ids
VdsVds
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Construction Of Inverter Curves
Ids
VdsVds
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CMOS Inverter Load CharacteristicsIn,p V = 5
PMOS
Vin = 0Vin = 5
NMOS
Vin = 1 Vin = 4
Vin = 2
Vin = 3
Vin = 4Vin = 2 Vin = 3
Vin = 5Vin = 3 Vin = 2 Vin = 1
Vin = 0
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5.0
CMOS Inverter VTC
V out
0.0
Vin5.00.0
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Inverter Supply Current
ply
n=I dp
=Isu
ppI dn
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Small Signal Model for an MOS Transistor
• Vsb = 0• voltage-controlled current source (gm)• output conductance (gds)• interelectrode capacitance
Cgd
G
D
gdsgmVgsCgs + Cgb Cdb
SS
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Output Conductance
2
• By differentiating Ids w.r.t. Vds
• In linear region]
2)[(
2ds
dstgsdsVVVVI −−= β
])[( dstgsds VVVg −−= β)(
1linear VVV
R =β
])[( dstgsdsg β)( dstgs
linear VVV −−β
• In saturation, device behaves like a current source: the current being almost independent of Vdthe current being almost independent of Vds
])(2
[ 2tgsds VVI −=
β
2β
0])(
2[ 2
=−
=ds
tgs
ds
ds
dV
VVd
dVdI
β
I lit d ff t lt i l• In reality, secondary effects result in a slopeλdsds Ig =
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Transconductance
• Expresses relationship between output current and input voltage
)(
constant| dsgs
dsm
Vli
VdVdIg ==
β)(.)(
)(
tgsm
dsm
VVsatgVlinearg
−==
ββ
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MOS Transistor Small Signal Model
G+ r0
gmvgsvgs-gs
S
gm rogm o
Linear kVDS [k(VGS-VT-VDS)]-1
Saturation k(VGS-VT) 1/λID( GS T) D
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CMOS InverterVDD
sVout = VDD - Vsdp
d
Vout VDD Vsdp= VDD + Vdsp
Vin = VDD - Vsgp= V + Vd
VinVout
= VDD + Vgsp
s
Vin = Vgsn, Vout = Vdsn
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Regions of OperationRegions of Operation
Cutoff Non-saturated Saturated
Vgsp < VtpVin < Vtp + VDDVgsp > Vtp
Vgsp = VtpVin < Vtp + VDD
Cutoff Non saturated Saturated
p-devicein tp DD
Vdsp > Vgsp - VtpVout > Vin - Vtp
gsp tp
Vin > Vtp + VDD
in tp DD
Vdsp < Vgsp - VtpVout < Vin - Vtp
Vgsn > Vtn Vgsn > VtngVin > Vtn
Vdsn < Vgs - VtnV V V
Vgsn < Vtn
Vin < Vtn
n-device
gVin > Vtn
Vdsn > Vgs - VtnV V VVout < Vin - Vtn Vout > Vin - Vtn
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5.0 A: nmost off
Inverter Operating Regions
pmost linear reg.
B: nmost saturatedt li
ut
pmost linear reg.
C: nmost saturatedpmost saturatedV o pmost saturated
D: nmost linear reg.pmost saturated
0.0
Vi 5.00.0
pmost saturated
E: nmost linear reg.pmost offVinp
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Inverter Operating Regions
A: nmost offpmost linear region
B: nmost saturatedt li i tpmost linear region
C: nmost saturatedpmost saturated
out out out out out
pmost saturated
D: nmost linear regionpmost saturated
A B C D Epmost saturated
E: nmost linear regionpmost off
Assume infinite ro when a device is in saturation
p
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Region ARegion A(0 ≤ Vin ≤ Vtn)
Idsn = 0 ⇒ n-device is cut-offp-device in linear region
VDD
p device in linear region
Idsn = - Idsp = 0, as Idsn = 0VV
Vdsp = Vout - VDD
VoutVin
With Vdsp = 0, Vout = VDD
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Region B)
2( DD
intnVVV ≤≤
p-device in non-saturated region (Vds ≠ 0)n-device is in saturation
IIdsp
Vin = Vgsn
VoutIdsn
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Region B
)(;2
][ 2nntnin
ndsn LW
tVVI εμββ =
−=
2 nox Lt
Vgsp = (Vin - VDD) & Vdsp = (Vout - VDD)
2
)(
]2
)())([(2
pp
DDoutDDouttpDDinpdsp
Wt
VVVVVVVI
μβ
β −−−−−−=∴
)(p
p
ox
pp Lt
β =
Equating I = -IEquating Idsp = -Idsn
22 )()(2)()( tcin
DDtpDD
intpintpinout VnVVVVVVVVVV −−−−−−+−=β )()
2()()( tci
pDDtpintpintpinout β
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Region DRegion D)
2( tpDDin
DD VVVV−≤<
p : saturationn : non-saturated Idsp
)(21
2tpDDinpdsp VVVI −−−= β
Vout
Idsn
2
]2
)[( outouttninndsn
II
VVVVI
−=
−−= β
22 )()()( tpDDinp
tnintninout
dsndsp
VVVVVVVV
II
−−−−−−=∴
−=
ββ
nβ
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Determining VIH and VIL
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R i ERegion E(Vin >= VDD - Vtp)
p: cut-off Idsp = 0li dn: linear mode
Vgsp = Vin - VDD → more positive than Vtpgsp in DD p tp
Vout = 0
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Region C(B th d i i S t ti )(Both devices in Saturation)
β 2)(2 tpDDin
pdsp VVVI −−−=
β
β
2)(2 tnin
ndsn VVI −=
β
E ti I I
nVVV β++
Equating Idsp = -Idsn
n
ptntpDD
in
VVVV
β
β
+
++
=1
pβ+1
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Gate Threshold Voltage
If βn = βp & Vtn = -Vtp
V2DD
inVV =
Region C exists for one value of Ving in
Possible values of Vout in region C
n-channel Vin - Vout < VtnVout > Vin - Vtn
p-channel Vin - Vout > VtpV < V V
saturation conditions
Vout < Vin - Vtp
Vin - Vtn < Vout < Vin - Vtp
In reality, region C has a finite slope - because in reality Ids increases slightly with Vds in saturation
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Typical Parameter Values (1μm process)
/1085.89.3
sec/50014
2
××=
−=−
n
cmF
Vcm
ε
μ
A200=oxt
)(LW
tnμεβ =
5
14
102.1085.89.3500
WLW
Ltox
××××
= −
−
sec/180 2 −≈p Vcmμ
2/5.88 VALW μ=
82
/9.31 2=∴
n
p
p
VALW
β
μβ
8.2=p
n
ββ
(The ratio varies from 2-3)
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βn/βp Ratioβn βp
increasing V
n
ββ
gVout
V
pβ
increasing
Vin
n
WW
increasing
Vout
pW
Vin
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Effect of βn/βp Ratio βn βp
Vm dependent onp
n
ββ
βwith change in transition still remains sharp and henceswitching performance does not deteriorateIt is desirable to have
pβ
p
n
ββ
It is desirable to have
= 1 p
n
ββ
allows capacitance load to change and discharge in equaltimes by providing equal current source & sink capability⇒
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Gate Switching Threshold
4.0
3.0
M
2.0
VM
0.1 0.3 1.0 3.2 10.01.0 pβkp/kn
ptntpDD rVVVr
Vβ
=++
= with)(
n
pβ
nM r
rV
β=
+= with
1
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Effect of Temperaturep
• Temperature similarly affects mobility of holes and l telectrons
• Temperature increases ⇒ μ decreases ⇒ βdecreasesdecreases
5.1−∝ Tβ
• Ratio βn/βp is independent of temperature to a goodRatio βn/βp is independent of temperature to a good approximation
• Temperature, however, reduces threshold voltages• Extent of region A reduces and extent of region E
increases• VTC shifts to the left as the temperature increases• VTC shifts to the left as the temperature increases
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Switching Characteristics
• Switching speed - limited by time taken to charge and discharge, CL
Ri ti t f t i f 10% t 90% f it• Rise time, tr : waveform to rise from 10% to 90% of its steady state value
• Fall time, tf : 90% to 10% of steady state valueFall time, tf : 90% to 10% of steady state value• Delay time, td : time difference between input
transition (50%) and 50% output level
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CMOS Inverter: Transient Responsep
VDD
t f(R C )tpHL = f(RonCL)= 0.69 RonCL
Vout
VDD1
Ron
DD1
0.5
CL
0.36
Vin = VDD tRonCL
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CMOS Inverter Propagation DelayC OS e te opagat o e ay
VDDiLVC 2/
av
swingLpHL I
VCt
2/=
Vout =+==
2)2/()( DDoutDDout
avVVIVVII
Iav
CL
⎟⎟⎠
⎞⎜⎜⎝
⎛−+=
23
287
2
22tnDDtnDDn VVVVβ
Vin = VDD
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Inverter Propagation Delay
• Assume n-device still in saturation at Vout = VDD/22β 2)(
2 tnDDn
av VVI −=β
DDLVCt
L
tnDDn
DDLpHL
CVV
tβ
≈
−= 2)(
DDnVβ≈
LLH
Ct ≈DDp
pLH Vt
β
⎟⎟⎞
⎜⎜⎛
+≈ LCt 11⎟⎟⎠
⎜⎜⎝
+≈npDD
p Vt
ββ2
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Analysis of Fall Time
VDD
Vout(t)Vin(t)
CL
2non-saturated x2
saturated(Vds = Vgs - Vt)Ids
x1
Application of stepinput
x3 Vout (t) VDD
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Components of Fall Time
tf = tf1 + tf2 Vout drops from Vdd - Vt to 0.1 VDD
Vout drops from 0.9Vdd to Vdd - VtVout drops from 0.9Vdd to Vdd Vt
V V0.9 VDD
V
VDD - Vt0.1 VDD
VVin Vout
tf
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Fall Time for Saturated Region
IP
Ic
Idsn
Input rising
n CL
VoutSaturated, Vout ≥ VDD - Vtn
0)( 2 =+ nout VVdVC β 0)(2
=−+ tnDDL VVdt
C
Integrating from t = t1 (corresponding to Vout = 0.9 VDD) to t = t2( di t V (V V ))(corresponding to Vout = (VDD - Vtn))
∫= DDV
outL
f dVCt9.0
21 )(2
β ∫ −− tnDD VV outtnDDn
f VV 21 )(β
)1.0(2 DDtnL VVC −2)(
)(
tnDDn
DDtnL
VV −=
β
![Page 83: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/83.jpg)
Fall Time for Non-Saturated Region
p
V
n CL
Vout
Non-saturated : 0 ≤ Vout ≤ VDD - Vtn
=−−+ outouttnDDn
outL
VVVVdt
dVC2
0]2
).[(β
∫ −−−
= DD
tnDD
V
VV
tout
out
tnDDn
Lf
VVdV
VVCt
1.0
22 )(β− out
tnDD
VVV )(2
![Page 84: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/84.jpg)
Fall Time for Non-Saturated Region
∫DDV outL dVCt
1.0
∫ −−
−−
=tnDD VV
outtnDD
out
out
tnDDn
Lf
VVV
VVVt 22
)(2)(β
)2019ln()( V
VVVV
C
DD
tnDD
tnDDn
L −−
=β
)2019ln()1(
)(
nnV
C
DDn
L
DDtnDDn
−−
=β
β
)(DDnβ
where n = tn
VV
DDV
![Page 85: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/85.jpg)
Fall Time Computation
⎥⎤
⎢⎡
−+−
=
+=
)2019ln(1)1.0(2
21
nnC
ttt
L
fff
⎥⎦
⎢⎣
+−−
)2019ln(2)1()1(
2 nnnVDDnβ
C
DDn
Lf V
Cktβ
≈
VVVVk 150d53f43 VVVVk tnDD 1~5.0and5~3for 4~3 ===
![Page 86: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/86.jpg)
Rise Time
⎥⎦
⎤⎢⎣
⎡−+
−−
−= )2019ln(
21
)1()1.0(
)1(2 p
pp
pVCt
DDp
Lr β ⎦⎣ )()( ppDDpβ
with tp
VV
p||
=DDV
Lr V
Cktβ
≈DDpVβ
For equally sized n- and p transistorsβ ≈ 2ββn ≈ 2βp
rtt ≈2ft ≈
![Page 87: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/87.jpg)
Sizing for Identical Rise/Fall Timeg
For same tf and trβ 1=
p
n
ββ
Increase the width of p-device to
WW 32≈ np WW 32 −≈
![Page 88: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/88.jpg)
Delay Time: First Order Approximation
• Gate delay is dominated by the output rise and fall time
2r
drtt =
2f
df
tt =
2f
![Page 89: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/89.jpg)
General Delay Time Computation
• Similar to the computation of rise/fall timesSimilar to the computation of rise/fall times– Saturation region from t = t1 (corresponding to Vout = VDD) to t
= t2 (corresponding to Vout = (VDD - Vtn))Linear region from t = t (corresponding to V = (V V ))– Linear region from t = t2 (corresponding to Vout = (VDD - Vtn)) to t = t3
∫ −−=− DD
tnDD
V
VV outtnDDn
L dVVV
Ctt 212 )(2
β
2)()(2
tnDDn
tnL
VVVC−
=β )( tnDDnβ
![Page 90: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/90.jpg)
Delay Time Computation
∫V dVC '
∫ −−
−−
=− out
tnDD
V
VV
outtnDD
out
out
tnDDn
L
VVV
VdV
VVCtt
'2'23
)(2)(β
tnDD
)22ln()(
outtnDD
DD
L
VVVV
VVC −−
−=
β
))1(2ln()1(
)(
O
O
DDn
L
outtnDDn
VVn
nVC
VVV−−
−=
β
β
)( ODDn VVβ
where outO
tn
VVV
VVn == ,
DDDD VV
![Page 91: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/91.jpg)
Delay Time
C
DDn
LnDn V
CAtttβ
=−= 13
Delay ∝ CL (optimize CL to decrease delay)
(decrease VDD increases delay)
(if W ↑ or L ↓ delay decreases)DDV1
∝
1 (if W ↑ or L ↓, delay decreases)
Three major parameters for optimizing speed of CMOSβ
∝
![Page 92: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/92.jpg)
Components of CL
Cw = wiring capacitance
Cg = gate capacitance = CoxWL
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Miller Effect
• Effective voltage change over the gate-drain capacitor is actually twice the output voltage swingcapacitor is actually twice the output voltage swing
• Contribution of gate-drain capacitor should be counted twice
![Page 94: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/94.jpg)
Junction Capacitancep
• Non-linear capacitor modeled by linear capacitor with the same change in charge for the voltage range of interest
CKC
[ ]mlow
mhigh
m
eq
jeqeq
VVmVV
K
CKC
−− −−−−
=
=
10
10
0
0
)()()1)((
φφφ
lowhigh mVV −− )1)((
• Linearize over the interval {5V, 2.5V} for the high-to-low transition and {0, 2.5V} for the low-to-highlow transition and {0, 2.5V} for the low to high transition
• Correspond to {Vhigh=-5V, Vlow=-2.5V} and {Vhigh=0, V 2 5V} f NMOSVlow=-2.5V} for NMOS
![Page 95: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/95.jpg)
Delay in function of VDD
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Sizing of Inverter Loaded by an Identical GateS g o e te oaded by a de t ca Gate
Load cap. of first gate:p gCL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + CW
where Cdp1, Cdn1 → diffusion capacitance of first gatepCgp2, Cgn2 → gate capacitance of second gate
Cw → wiring capacitance
If PMOS d i ti l th th NMOSIf PMOS devices are α times larger than the NMOS ones,
pLW
LW)/(
)/(=α
all transistor capacitances will scale in approximately the same way nLW )/(
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Sizing of Inverter
gngp
dndp
CC
CC
≈
≈
22
11
α
α
fr ttt
+= )( pnL AAC
+=
wgndnL CCCC +++=∴ ))(1( 21α
2pt =
)(2
)(2
ββ
β
ββ
npn
L
pnDD
AA
VC
V
+=
+=
))/()/(.(
2
)(.2
μμ
β
ββ
nnpn
L
pn
nDD
LWLWA
AV
C
V
+=
)(.2
)/(.2
αμμ
β
μβ
p
npn
nDD
L
ppnDD
AA
VC
LWV
+=μβ pnDD
![Page 98: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/98.jpg)
Sizing of Inverter
)(.2 αμ
μβ p
npn
nDD
Lp
AA
VCt +=
∂
).
(.2
))(1( 21
αμμ
βα
p
npn
nDD
Wgndn AA
VCCC
++++
=
αα
optimalget to0Let =∂
∂ pt
CAμ )1(21 gndn
W
n
p
p
nopt CC
CAA
++=
μμα
If CW << Cdn1 + Cgn2, Ap = An
731nμC t t t 3 hi h i ll d73.1≈≈
p
nopt μ
μα Contrast to 3 which is normally usedin the non-cascaded case
![Page 99: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/99.jpg)
Impact of Rise Time on Delay
22 )2/()()( rpHLPHL tsteptactualt +=
Minimum-size inverter with fanout of a single gate
![Page 100: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/100.jpg)
Velocity Saturation
• Under long channel model, saturation current ∝ VDD2
• In small-geometry devices, this no longer holds: Iav ∝ VDD
SATL WCvkCt )11( κ=+≈
av DD
• Therefore, for VDD >> VT we have,
pnoxSATpnnp
p WCvkkk
t ,, )(2
κ+
• Running velocity saturated devices fat high VDD is not beneficial
• Lowering VDD below 2VT sharply increases delay
![Page 101: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/101.jpg)
Source/Drain Resistance
• In small-geometry devices, source and drain resistance affects switching currents
Source of the transistor is no longer grounded body effect– Source of the transistor is no longer grounded, body effect increases threshold voltage
– Vgs is also reduced– Current is reduced
![Page 102: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/102.jpg)
Power Consumption
• Static Power– Leakage current
Sub threshold conductance– Sub-threshold conductance
• Dynamic Power– Capacitive Power due to charging/discharging of capacitive p g g g g p
load– Short-circuit power due to direct path currents when there is
a temporary connection between power and groundp y p g
![Page 103: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/103.jpg)
Static Power Consumption
VVDD
V = V
VDD
Vout = VDD
Diode leakage
)1( / kTVqiISub-threshold current
/)( kTVV
)1( / −= kTVqsO eiI
)1( //)( kTqVnkTqVVD
dstgs eeKI −⋅= −
Pstatic = Ileakage. VDD
![Page 104: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/104.jpg)
Static Consumptionp• Leakage current through the reverse biased diode
junctions• For typical devices it is between 0.1nA - 0.5nA at
room temperatureFor a die with 1 million devices operated at 5 V this• For a die with 1 million devices operated at 5 V, this results in 0.5mW power consumption → not much
• Junction leakage current is caused by thermally g y ygenerated carriers -> therefore is a strong function of temperature M i t t i b th h ld l k h• More important is sub-threshold leakage when threshold voltage is close to 0
![Page 105: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/105.jpg)
Dynamic Consumption due to CL
VDD
Vout
l hi h i i- low-to-high transition- Assume 0 rise and fall times
![Page 106: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/106.jpg)
Dynamic Power due to CL
Vout
t
VDD
iVDD
t
CL
in
tdischargedischarge
charge
Define:E t k f l d i t itiEVDD : energy taken from supply during a transitionEC: energy stored on capacitor at the end of transition
![Page 107: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/107.jpg)
Energy Consumed and Stored
dtdt
dVCVdtVtiE outLDDDDVDDVDD
.)(0 0∫ ∫∞ ∞
==V
∫)(2
0
DDDDL
V
outDDL
QVVC
dVVC DD
==
= ∫
dtVdt
dVCdtVtiE outout
LoutVDDC ∫ ∫∞ ∞
==0 0
)(V
. 20
DDL
out
V
outDDL
VC
dVVVC DD
=
= ∫
2=
Half the energy is stored in Capacitor ! Other half is dissipated in the PMOS transistor !!the PMOS transistor !! For each switching cycle ( L → H & H → L), amount of energy dissipated in CL. VDD
2
![Page 108: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/108.jpg)
Pdynamic = CL.VDD2.f
• Example– 1.2μ CMOS chip– 100 MHz clock rate100 MHz clock rate– Average load capacitance of 30 fF/gate– 5V power supply
• Power consumption/gate = 75 μWPower consumption/gate 75 μW• Design with 200,000 gates: 15W !• Pessimistic evaluation: not all gates switch at the full rate
H t id th ti it f t Eff ti it hi• Have to consider the activity factor α: Effective switching capacitance = αCL
• Reducing VDD has a quadratic effect on Pdynamic
![Page 109: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/109.jpg)
Direct Path Current
• inputs have finite rise and fall times• Direct current path from VDD to GND while PMOS and
NMOS are ON simultaneously for a short periodPsc = Imean.VDD
tftrVDD + Vtp
T
Vtn
Imax
Imean
t1 t2 t3
![Page 110: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/110.jpg)
Symmetrical Inverter Without Load
⎥⎦⎤
⎢⎣⎡ += ∫∫
3
2
2
1
)(1)(12t
t
t
tmean dttIT
dttIT
I⎦⎣
2 β
If Vtn = -Vtp=VT and βn = βp = β and that the behavior around t2 is symmetrical
dtVtVT
I tin
t
tmean2))((
222 2
1
−×= ∫β
with DD tVtV =)(with
rt
rin
tVVt
tt
tV
=
=
.
)(
1
r
DD
tt
V
=22
rffr ttt ==
![Page 111: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/111.jpg)
Symmetrical Inverter Without Load
2/
/
2)(2 t
VVt trf
DDmean dtVt
tV
TI rf
DDTrf
−⋅= ∫β
2/
/
3)(3
2t
VV
trf
DD
DD
rf Vtt
VVt
T
rf
⎥⎥⎦
⎤
⎢⎢⎣
⎡−⋅=
β
3
/
)2
(32
tDD
DD
rf
VVtrfDD
VVVT
tDDTrf
−⋅=
⎥⎦⎢⎣
β
3)2(12
23
tDDDD
rf
DD
VVVT
tVT
−⋅=β
DD
tVVP rf3)2( −=
βT
VVP tDDsc )2(12
=
![Page 112: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/112.jpg)
Short Circuit Current with LoadsShort Circuit Current with Loads
![Page 113: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/113.jpg)
Output Transitions under Different Loads
![Page 114: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/114.jpg)
CL Power vs. SC Power under Different Loads
![Page 115: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/115.jpg)
CL Power vs. SC Power under Different Inputs
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Impact of Load Capacitance on SC Currentp p
• Large capacitance– Fast input transition, slow output transition– Input moves through the transient region before output
begins to changeg g– Short-circuit current close to zero
• Small capacitance– Relatively slower input transition, fast output transition– Both devices in saturation during most of the transition– Maximum short-circuit current
• [Veendrick84]: rise/fall times of all signals should be kept constant within a range to keep SC power minimal 10%~20% of total dynamic powerminimal, 10%~20% of total dynamic power
![Page 117: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/117.jpg)
Technology Evolution
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Technology Scaling (1)
Minimum Feature Size
![Page 119: The InverterThe Inverter - Purdue Engineeringvlsi/ECE559_Fall09/Notes/Inverter.pdf · The InverterThe Inverter References: Adapted from: Digital Integrated Circuits: A Design Perspective,](https://reader030.fdocuments.us/reader030/viewer/2022032614/5b8c551009d3f240638cc2a1/html5/thumbnails/119.jpg)
Technology Scaling
108p
mosfet
bipolar105
106
107
onen
ts/C
hip bipolar
transistor
mesfet104
105
Com
po
bipolarTransistor
enhancementmosfet
101
102
103
IC
11950 1960 19801970 1990
YEAR
101 IC
YEAR
Number of components per chip
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Propagation Delay Scalingp g y g
1n
500p
1n
e)
F/O = 1R.T. Operation
100p
200p
Dd(
sec/
stag
e
Ref.[4]3.5V
Ref.[5]3.5V
50p
100p
te D
elay
: τD Present Results
Reported Results
3.5V
3.3V2.5VRef.[7]
2.5V
20p
0 5 1 0 5 0 10 0
Gat VDD
ScalingVDD=5V
10p0.5 1.0 5.0 10.0
Channel Length : Left (μm)
0.1
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Technology Scaling Models
• Full Scaling (Constant Electrical Field)• Full Scaling (Constant Electrical Field)ideal model — dimensions and voltage scaletogether by the same factor S
• Fixed Voltage Scalingmost common model until recently —only dimensions scale, voltages remain constant
• General Scalingmost realistic for todays situation —voltages and dimensions scale with different factors
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Scaling Relationships for Long channel DevicesScaling Relationships for Long channel Devices
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Scaling of Short Channel Devices
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Homework Problem (due next Thursday)
• Design a static CMOS inverter with 0.4pF load capacitance. Make sure that you have equal rise and fall times. Layout the inverter using the Mentor tools, extract parasitics, and simulate the extracted circuit on HSPICE t k th t d i f t th ifi tiHSPICE to make sure that your design conforms to the specification.
• Do the same analysis for a three input NAND gate.