The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU...
Transcript of The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU...
![Page 1: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/1.jpg)
The Evolution of Microprocessors
Per Stenström
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Processor(Core)
Memory
Processor(Core)
Processor(Core)
L2 Cache
L1 Cache L1 Cache L1 Cache
MicroprocessorChip
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Time1970 20201980 1990 2000 2010
Multicycle Pipelined Superscalar Multicore …and beyond
Evolution of Microprocessors
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Multicycle Computers
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Fetc
h ne
xt in
stru
ctio
n
Dec
ode/
Fetc
h da
ta
Exec
ute
Stor
e re
sult
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Opcode Assembly code Meaning CommentsADD,SUB, ADD R1,R2,R3 R1=(R2) + (R3) Integer
operationsADDI, SUBI ADDI R1,R2,#3 R1=(R2)+3 ImmediateAND, OR, XOR AND R1,R2,R3 R1=(R2).AND.(R3) bit-wise
logical AND,OR, XOR
SLT SLT R1,R2,R3 If (R2)<(R3) then R1=1 else R1=0
Test R2, R3 outcome in R1
ADD.D, SUB.D, MUL.D, DIV.D
ADD.D F1,F2,F3 F1=(F2)+(F3) Floating-pointoperations
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Opcode Assembly code Meaning CommentsLB,LH,LW,LD LW R1,#20(R2) R1=MEM[20+(R2)] For bytes,
half-words, words anddouble words
SB,SH,SW,SD SW R1,#20(R2) MEM[20+(R2)]=R1L.S, L.D L.S F0,#20(R2) F0=MEM[20+(R2)] Single/double
float load
S.S, S.D S.S F0,#20(R2) MEM[20+(R2)]=F0 Single/double float store
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Opcode Assembly code Meaning CommentsBEQZ, BNEZ BEQZ R1,Label If (R1)=0 then
PC=LabelConditionalbranch-equal 0/not equal 0
BEQ, BNE BEQ R1,R2,Label If (R1)=(R2) PC=Label
Conditional branch-equal/not equal
J J Target PC=Target Target is an immediate field
JR JR R1 PC=(R1) Target is in register
JAL JAL Target R31 = PC + 4;PC = Target
Jump to target and save return address in R31
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
[15..0]
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
[15..0]
MU
XALU
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
[15..0]
MU
XALU
MU
X
MU
X
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt dataM
UX
ALU
SignEx-tend
[15..0]
Effective addresssDisplacement + (Rs)
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt dataM
UX
ALU
SignEx-tend
[15..0]
Data memory
Rd addrWr addr
Write data
Rd data
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
[15..11]
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt dataM
UX
ALU
SignEx-tend
[15..0]
Data memory
Rd addrWr addr
Write data
Rd data
MU
XALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ALU
ADD
+4
MU
XFetching the next instruction
ALU
Control
Memory transfer
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
ALU
Control
Memory transfer
BEQ R1,R2,offset ZERO
![Page 18: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/18.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
RegDst
RegWrite
ALUSrcALUOp
PCSrc
MemToReg
MemWrite
MemRead
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Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
DECODE /OPERAND FETCH
EXECUTE MEMORYACCESSINSTRUCTION
FETCHWRITEBACK
![Page 21: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/21.jpg)
Pipelined ”Single-Cycle” Computer
![Page 22: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/22.jpg)
The Conveyor Belt
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![Page 24: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/24.jpg)
![Page 25: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/25.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
LD R3,0(R11) LD R2,0(R10)ADD R1,R2,R3SD 0(R12),R1SUBI R4,R4,#1
LABEL: LD R2, 0(R10)
LD R3, 0(R11)
ADD R1,R2,R3
SD 0(R12), R1
SUBI R4,R4,#1
ADDI R10,R10,#4
ADDI R11,R11,#4
ADDI R12,R12,#4
BNEZ R4, LABEL
![Page 26: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/26.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
LD R3,0(R11) LD R2,0(R10)ADD R1,R2,R3SD 0(R12),R1SUBI R4,R4,#1
Structural hazardsData hazards
Control hazards
![Page 27: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/27.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
LD R3,0(R11)ADD R1,R2,R3SD 0(R12),R1SUBI R4,R4,#1 UNUSED
Structural hazardsData hazards
Control hazards
![Page 28: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/28.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
ADD R1,R2,R3SD 0(R12),R1SUBI R4,R4,#1 UNUSED UNUSED
Structural hazardsData hazards
Control hazards
![Page 29: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/29.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
BEQ R1,offsetUNUSED
Structural hazardsData hazards
Control hazards
![Page 30: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/30.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
UNUSED UNUSED BEQ R1,offset
Structural hazardsData hazards
Control hazards
![Page 31: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/31.jpg)
Instructionmemory
ReadAddress
Instruction[31..0]
PC
MU
X
[25..21]
[20..16]
Data memory
Rd addrWr addr
Write data
Rd data
[15..11] MU
X
Registers
Rs addrRt addr
Rd addr
Write data
Rs data
Rt data
MU
X
SignEx-tend
[15..0]
ShiftLeft2 ADD
ALU
ADD
+4
MU
X
UNUSED UNUSED BEQ R1,offsetNEXT INST.
Structural hazardsData hazards
Control hazards
![Page 32: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/32.jpg)
Superscalar Microprocessors
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IF IS EXID WB
InstructionFetch
InstructionDecode/Dispatch
InstructionIssue/ReadOperands
Execute WriteBack
![Page 34: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/34.jpg)
IF ID WB
EX 1
EX 2
EX N
IQ 1
IQ 2
IQ N
Fetch Decode/Dispatch
ReadOperands Execute Write
Back
![Page 35: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/35.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R1)
Cycle: 1
![Page 36: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/36.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R1)L.S F1,0(R2)
Cycle: 2
![Page 37: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/37.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R1)
L.S F1,0(R2)ADD.S F2,F1,F0
Cycle: 3
![Page 38: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/38.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R1)L.S F1,0(R2)
ADD.S F2,F1,F0S.S F2,0(R1)
Cycle: 4
![Page 39: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/39.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R1)
L.S F1,0(R2)
ADD.S F2,F1,F0
ADDI R1,R1,#4 S.S F2,0(R1)
Cycle: 5
![Page 40: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/40.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F1,0(R2)
ADD.S F2,F1,F0
ADDI R1,R1,#4ADDI R2,R2,#4
S.S F2,0(R1)
Cycle: 6
![Page 41: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/41.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
ADD.S F2,F1,F0
ADDI R2,R2,#4 SUBI R3,R3,#1
S.S F2,0(R1)
ADDI R1,R1,#4Cycle: 7
![Page 42: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/42.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
ADD.S F2,F1,F0
SUBI R3,R3,#1 BNEZ R3,Loop
S.S F2,0(R1)
ADDI R1,R1,#4ADDI R2,R2,#4 Cycle: 8
The ADDI R1,R1,#4 is being executed Out-of-program-orderwith respect to the S.S F2,0(R1)!
![Page 43: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/43.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F0,0(R2)
ADD.S F2,F1,F0
SUBI R3,R3,#1
BNEZ R3,Loop
S.S F2,0(R1)
ADDI R1,R1,#4
ADDI R2,R2,#4 Cycle: 9
![Page 44: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/44.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F1,0(R1) L.S F0,0(R2)
ADD.S F2,F1,F0
SUBI R3,R3,#1 BNEZ R3,Loop
S.S F2,0(R1)
ADDI R2,R2,#4
Cycle: 10
![Page 45: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/45.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F1,0(R1) L.S F0,0(R2)
ADD.S F2,F1,F0
SUBI R3,R3,#1
BNEZ R3,Loop
S.S F2,0(R1)
Cycle: 11
![Page 46: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/46.jpg)
IF ID WB
INT
FP
MEM
I-Q
FP-Q
M-Q
Loop L.S F0,0(R1) L.S F1,0(R2) ADD.S F2,F1,F0 S.S F2,0(R1) ADDI R1,R1,#4 ADDI R2,R2,#4 SUBI R3,R3,#1 BNEZ R3,Loop
L.S F1,0(R1)
L.S F0,0(R2)
ADD.S F2,F1,F0ADD,S F2,F1,F0
BNEZ R3,Loop
S.S F2,0(R1)
Cycle: 12
![Page 47: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/47.jpg)
Multicore Computers
![Page 48: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/48.jpg)
Processor(Core)
Memory
Processor(Core)
Processor(Core)
L2 Cache
L1 Cache L1 Cache L1 Cache
MicroprocessorChip
![Page 49: The Evolution of Microprocessors Per Stenström...Rtdata X Sign Ex-tend [15..0] Shift Left 2 ADD ALU ADD +4 X SUBI R4,R4,#1 SD 0(R12),R1 UNUSED ADD R1,R2,R3LD R3,0(R11) Structural](https://reader035.fdocuments.us/reader035/viewer/2022071409/6101b6f8ebbdb244e5539af1/html5/thumbnails/49.jpg)
Lectures on youtube9 interactive sessions, flipped class-room style5 problem solution sessions1 design exploration projectTextbook: Parallel Computer Organization and DesignDubois, Annavaram, Stenström
Blended Learning