The Design of a Relay Computer - Computer Action Teamweb.cecs.pdx.edu/~harry/Relay/RelayTalk.pdf124...
124
1 The Design of a Relay Computer Harry Porter, Ph.D. Portland State University April 24, 2006
Transcript of The Design of a Relay Computer - Computer Action Teamweb.cecs.pdx.edu/~harry/Relay/RelayTalk.pdf124...
1
The Design of aRelay Computer
Harry Porter, Ph.D.Portland State University
April 24, 2006
2
3
+V
4
Double Throw Relay
5
+V
Double Throw Relay
6
Four Pole, Double Throw Relay
7
+V
Four Pole, Double Throw Relay
8
9
Schematic Diagrams
10
Schematic Diagrams
Assume other terminalis connected to ground
11
Schematic Diagrams
Assume other terminalis connected to ground
+V
12
The “NOT” Circuit
in out
in out 0 1 1 0
in
out+V
13
The “NOT” Circuit
in out
in
out+V
in out 0 1 1 0
0
1
Convention: “1” = +12V “0” = not connected
14
The “NOT” Circuit
in out
in
out+V
in out 0 1 1 0
1
0
Convention: “1” = +12V “0” = not connected
15
c
The “OR” Circuit
b b or c
+V
+V
b c OUT0 0 0 0 1 11 0 11 1 1
bc b or c
16
An Optimization?
c
b
b or cb or cbc
17
c
An Optimization?
b b or c
b
b or cc
c or dd
d
c or d
18
c
An Optimization?
b b or c
b
b or cc
c or dd
d
c or d
Whoops!
19
c
An Optimization?
b b or c
b
b or cc
c or dd
d
c or d
Whoops!
20
An Optimization?
b or c
c
b
+V
d
c or d
b b or c
c
c or dd
21
1-Bit Logic Circuit
b
c
NOT
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
AND
OR
XOR
22
1-Bit Logic Circuit
b
VNOT
AND
OR
XOR
c
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
23
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
24
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
25
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
26
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
27
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
28
1-Bit Logic Circuit
b
V
c
NOT
AND
OR
XOR
b c NOT AND OR XOR0 0 1 0 0 00 1 1 0 1 11 0 0 0 1 11 1 0 1 1 0
29
AND7
OR7
Eight 1-bit circuits can be combinedto build an...
8-Bit Logic Circuit
LogicCircuit
NOT7
B7 C7
• • •
XOR7
AND1
OR1
LogicCircuit
NOT1
B1 C1
XOR1
AND0
OR0
LogicCircuit
NOT0
B0 C0
XOR0
30
The “Full Adder” Circuit
CarryinCarryout FullAdder
Sum
B CCyin B C Cyout Sum
0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
31
CarryinCarryout FullAdder
Sum
B C
8 full-adders can be combined to build an...
8-Bit Adder
32
8 full-adders can be combined to build an...
8-Bit Adder
CarryFullAdder
FullAdder
B0 C0
Sum0Sum1
B1 C1
FullAdder
Sum7
B7 C7
• • • 0Carry Carry
33
8 full-adders can be combined to build an...
8-Bit Adder
CarryFullAdder
FullAdder
B0 C0
Sum0Sum1
B1 C1
Carry FullAdder
Sum7
B7 C7
• • •
+B 8
8
8CSumCarry
Carry0
34
The Zero-Detect Circuit
ResultBus
ZeroV+
35
The Zero-Detect Circuit
ResultBus
ZeroV+
Sign
36
Enable Circuit
Enable
37
Enable Circuit
Enable
Bus
38
Enable Circuit x7 x6 x5 x4 x3 x2 x1 x0
ResultBus
B XOR C
Enable
39
Enable
Shift Left Circular (SHL)b7 b6 b5 b4 b3 b2 b1 b0
ResultBus
B
40
3-to-8 Decoderf0 f1 f2 OUTPUT
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
41
3-to-8 Decoder
f1
Vf0
f2
f0 f1 f2 OUTPUT
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
42
3-to-8 Decoder
f1
Vf0
f2
INCANDORXORNOTSHL<unused>
ADD
f0 f1 f2 OUTPUT
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
21:46
43CarrySign
Arithmetic Logic Unit (ALU)B 8
8
8C
Data Bus
3
Zero
8-bitLogic
8-bitAdder
Enable En En En En EnEn
AN
D
OR
XO
R
NO
T
SHL
INC
AD
D
Function
3-to-8Decoder
Zero-Detect
44
CarrySign
An 8-Bit ALU
ALU
B 8
8
8C
Result
Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 <nop>
3
Zero
45
Register Storage
+VA
46
Register Storage
+V
• • •
A7 A0A6
47
Register Storage
+V
Bus
• • •
Enable
A7 A0A6
Select
48
Register Storage
A7
Select
Load A0
• • •
Enable
A6
Bus
49
Register Storage
A7
Select
Load A0
• • •
Enable
A6
Bus
508-Bit “Data” Bus
LoadSelect
“X” Register
8-Bit Registers
518-Bit “Data” Bus
LoadSelect
LoadSelect
“X” Register “Y” Register
8-Bit Registers
52
16-Bit “Address” Bus
8-Bit “Data” Bus
“X” Register “Y” Register
LoadSelect
LoadSelect
LoadSelect
53
SystemArchitecture
M1
M2
X
Y
8-bi
t D
ata
Bus
A B C D
54
SystemArchitecture
M1
M2
X
Y
8-bitALU
8-bi
t D
ata
Bus
Z Cy S
A B C D
55
SystemArchitecture
A B C D M1
M2 M
X
Y XY
8-bitALU
8-bi
t D
ata
Bus
Z Cy S
16-b
it A
ddre
ss B
us
56
SystemArchitecture
A B C D M1
M2 M
X
Y XY
8-bitALU
8-bi
t D
ata
Bus
Z Cy S
Inst
PC
16-b
it A
ddre
ss B
us
57
SystemArchitecture
M1
M2 M
X
Y XY
8-bitALU
8-bi
t D
ata
Bus
Z Cy S
Inst
PC
Memory
AddrData
A B C D
16-b
it A
ddre
ss B
us
58
SystemArchitecture
M1
M2 M
X
Y XY
8-bitALU
8-bi
t D
ata
Bus
Z Cy S
Inst
PC
Memory
AddrData
16-bitIncrement
Inc
A B C D
16-b
it A
ddre
ss B
us
59
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
SystemArchitecture
8-bi
t D
ata
Bus
A B C D
16-b
it A
ddre
ss B
us
60
32K Byte Static RAM Chip
LEDs
8 FET Power Transistors(to drive relays during
a memory-read operation)
61
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
16-b
it A
ddre
ss B
us Example:The ALU
Instruction
62
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
16-b
it A
ddre
ss B
us
63
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
SELECT 16-b
it A
ddre
ss B
us
64
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
SELECT 16-b
it A
ddre
ss B
us
65
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
MEM-READ
PC
SELECT 16-b
it A
ddre
ss B
us
66
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
MEM-READ
PC
SELECT 16-b
it A
ddre
ss B
us
67
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 1:Fetch Instruction
MEM-READ
PC
SELECT
LOAD16
-bit
Add
ress
Bus
68
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
Step 1:Fetch Instruction
8-bi
t D
ata
Bus
A B C D
MEM-READSELECT
LOAD16
-bit
Add
ress
Bus
69
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 2:Increment PC
16-b
it A
ddre
ss B
us
70
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 2:Increment PC
SELECT 16-b
it A
ddre
ss B
us
71
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 2:Increment PC
SELECT 16-b
it A
ddre
ss B
us
72
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 2:Increment PC
SELECT
LOAD
16-b
it A
ddre
ss B
us
73
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 2:Increment PC
SELECT
LOAD 16-bitIncrement
16-b
it A
ddre
ss B
us
74
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
Step 3:Update PC
16-b
it A
ddre
ss B
us
75
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
SELECT
Step 3:Update PC
16-b
it A
ddre
ss B
us
76
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
SELECT
Step 3:Update PC
16-b
it A
ddre
ss B
us
77
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
LOAD
SELECT
Step 3:Update PC
16-b
it A
ddre
ss B
us
78
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
8-bitALU
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A B C D
LOAD
SELECT
Step 3:Update PC
16-b
it A
ddre
ss B
us
79
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
B C
8-bitALU
16-b
it A
ddre
ss B
us
80
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
FUNCTION
B C
8-bitALU
16-b
it A
ddre
ss B
us
81
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
FUNCTION
B C
8-bitALU
16-b
it A
ddre
ss B
us
82
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
FUNCTION
B C
8-bitALU
16-b
it A
ddre
ss B
us
83
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
FUNCTION
LOAD
LOAD
B C
8-bitALU
16-b
it A
ddre
ss B
us
84
16-bitIncrement
Inst
M1
M2 M
X
Y XY
J1 J2
J
PC
Inc
Memory
AddrData
Z Cy S
8-bi
t D
ata
Bus
A
D
Step 4:Execute Instruction
FUNCTION
LOAD
LOAD
B C
8-bitALU
16-b
it A
ddre
ss B
us
21:46
85
Clock
Switch
+V Output
+V
86
Clock
Switch
+V Output
+V
Charging
87
Clock
Switch
+V Output
+V
Discharging
88
Clock
Switch
+V Output
+V
89
+V +V
Clock
+V +V
A B C D
90
+V +V
Clock
Charging
+V +VOnOn
Discharging
A B C D
91
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
92
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
93
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
94
+V +V
Clock
Charging
+V +VOn
Discharging
On
A B C D
95
Clock Timing Diagram
A
B
C
D
96
Clock Timing Diagram
A
B
C
D
Clock
97
Clock Timing Diagram
A
B
C
D
Clock
Clock = (A and B) or (C and D)
98
Finite State Machine
1 2 3 4 5 6 7 8
clock
99
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
100
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
101
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
102
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
103
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
104
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
105
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
106
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
107
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
108
t7t5t4t3t2t1
Finite State Machine
1 2 3 4 5 6 7 8
t6 t8
Outputs
clock
109
Output from FSA2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
t1
t2
t3
t4
t5
t6
t7
t8
110
Instruction Timing - ALU Instruction
Select PCMemory Read
Load InstrLoad Inc
Select Inc Load PC
ALU FunctionLoad A
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
111
Instruction Timing - ALU Instruction
Select PCMemory Read
Load InstrLoad Inc
Select Inc Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Fetch
Load A
112
Instruction Timing - ALU Instruction
Select PCMemory Read
Load InstrLoad Inc
Select Inc Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Increment
Load A
113
Instruction Timing - ALU Instruction
Select PCMemory Read
Load InstrLoad Inc
Select Inc Load PC
ALU Function
Load Cond.Code Reg.
2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 31
Load A
Execute
114
Instruction Decoding
Instruction RegisterFinite State Machine
Control Signals(Load, Select, Mem-Read, etc.)
1 2 3 4 5 6 • • • 7 6 5 4 3 2 1 0
115
Instruction Decoding
Instruction RegisterFinite State Machine
Control Signals(Load, Select, Mem-Read, etc.)
CombinationalLogic
1 2 3 4 5 6 • • • 7 6 5 4 3 2 1 0
116
1 2 3 4 5 6 7 8 9 10
Instruction Timing - 16-bit Move
Select PCMemory Read
Load InstrLoad Inc
Select Inc Load PC
Select Source-Register
2 3 4 5 6 7 8 11
Load Dest-Register
(Same asbefore)
117
Finite State Machine
1 2 3 4 5 6 7
9 11 13 15 16
17 18 19 20 21 22 23
10 12 14
24
8
118
Finite State Machine
1 2 3 4 5 6 7
9 11 13 15 16
17 18 19 20 21 22 23
10 12 14
24
8
119
Instruction Decoding and Control
Clock
InstructionRegister
Finite StateMachine
Control Lines
Instruction Decoding
Dat
a Bu
s
120
The Instruction Set (1)
0 0 d d d s s s
1 0 0 0 r f f f
0 1 r d d d d d
1 0 1 1 0 0 0 0
Move
ALU
Load Immediate
16-bit Increment
ddd = destination registersss = source register (A, B, C, D, M1 ,M2 ,X or Y)
r = destination register (A or D)fff = function code (add, inc, and, or, xor, not, shl)
r = destination register (A or B)ddddd = value (-16..15)
XY ← XY + 1
121
The Instruction Set (2)
1 0 0 1 0 0 r r
1 0 0 1 1 0 r r
1 1 0 0 0 0 0 0
1 0 1 0 1 1 1 0
Load
Store
Load 16-bit Immediate
Halt
rr = destination register (A, B, C, D)reg ← [M]
rr = source register (A, B, C, D)[M] ← reg
Load the immediate value into M (i.e., M1 and M2)
v v v v v v v v v v v v v v v v
122
The Instruction Set (3)
1 1 1 0 0 1 1 0
1 0 1 0 d s s 0
1 0 1 0 1 0 1 0
Goto
Call
16-Bit Move
Return / Branch Indirect
a a a a a a a a a a a a a a a a
Branch to the given address
1 1 1 0 0 1 1 1 a a a a a a a a a a a a a a a a
Branch to the given addressSave return location in XY register
PC ← XY
d = destination register (PC or XY)ss = source register (M, XY or J)
123
The Instruction Set (4)
1 1 1 1 0 0 0 0
Branch If Negative
Branch If Carry
Branch If Zero
Branch If Not Zero
a a a a a a a a a a a a a a a a
Branch to the given address if S = 1
1 1 1 0 1 0 0 0 a a a a a a a a a a a a a a a a
Branch to the given address if Cy = 1
Branch to the given address if Z = 1
Branch to the given address if Z = 0
1 1 1 0 0 1 0 0 a a a a a a a a a a a a a a a a
1 1 1 0 0 0 1 0 a a a a a a a a a a a a a a a a
124
An Example Program address instr assembly comment 0000 0000 0011 1001 Y=B Y ← B 0000 0001 0011 0110 X=0 X ← 0 0000 0010 1000 0101 A=¬B If sign(Y)==1 0000 0011 1111 0000 BNEG Else . 0000 0100 0000 0000 . . 0000 0101 0000 0111 . . 0000 0110 0011 0010 X=C X ← C Else: . 0000 0111 0101 1001 A=-7 D ← -7 0000 1000 0001 1000 D=A . Loop: Loop: 0000 1001 0000 1110 B=X Shift X left (circular) 0000 1010 1000 0110 A=B<<1 . 0000 1011 0011 0000 X=A . 0000 1100 0000 1111 B=Y Shift Y left (circular) 0000 1101 1000 0110 A=B<<1 . 0000 1110 0011 1000 Y=A . 0000 1111 0000 1111 B=Y If sign(Y)==1 0001 0000 1000 0101 A=¬B . 0001 0001 1111 0000 BNEG Else2 . 0001 0010 0000 0000 . . 0001 0011 0001 0111 . . 0001 0100 0000 1110 B=X X ← X + C 0001 0101 1000 0000 A=B+C . 0001 0110 0011 0000 X=A . Else2: . 0001 0111 0000 1011 B=D D ← D + 1 0001 1000 1000 1001 D=B+1 . 0001 1001 1110 0010 BNZ Loop If D != 0 goto Loop 0001 1010 0000 0000 . . 0001 1011 0000 1001 . . 0001 1100 1010 1110 HALT HALT
