(the current status and the future vision)

Koichi ShinozakiElectronic Devices and Materials Group

ARD, JAXA

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Objectives To contribute to reduction of size and weight of

systems or subsystems, a smaller and lighter package for the space-use LSI needs to be developed.

Technical trends or requirements for the space-use LSI package; The package needs more connecting pins for the I/Os of

the multi-function.

The package requires to be hermetic and ceramic for space-use and high reliability.

An accustomed reflow soldering method is rather used for mounting technology.

A hermetic ceramic BGA package2

Package overview (the current sample)

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Fig-2: Top-side view w/o seal-cap

Fig-3: bottom-side view w/BGA

Fig-1: Top view of a 304pin-QFP(LEFT)vs. a 572pin-BGA Pkg(RIGTH)

47mm

26mm

Feature for element evaluationTarget feature Remark

TYPE Ceramic BGA Al2O3 with hermetic seal

Mounting area 26x26mm Pkg size(ref.) 26x26x4.1t (mm)(reduce 80% from the mounting area of 304pin-QFP [47x47x3.25t(mm) without contact pins])

Pin count 572 24x24 (but no 4-corner-pin)

Pin pitch 1.0 mm

Pin material Solder 63Sn/37Pb or 10Sn/90Pbwith a vacuum reflow process

Die bonding Al wire-bonding conventional process

Mounting tech. Reflow of BGA with/without underfill material

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BGA packaging & Mounting tech.Technical issue Status

Die bonding Good with conventional wire-bonding method

Pin attach Good with a vacuum reflow oven

Pkg Mounting Thermal shock test (min 500 cycles @ -30 to +100 degree C)

(without underfill) 631 cycles

(with underfill) 816 cycles for ALL pins, or 1,046cycles for effective I/O pins

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To improve heat-stress tolerance of the mounting area or structure, more analyses and examinations should be performed.

Die bonding A four-deck cavity structure to

keep compatibility with a wire bonding method and to reduce the package size.

This package passed wire-pull tests after a wire-bonding process, 6-time reflow stress tests, 2,000-cycle thermal shock test (-30 to +100℃) and a constant acceleration test (5,000g).

1st deck2nd deck

3rd deck4th deck

Fig-4: top-side view w/o seal-cap

Fig-5: Bonds to die pads (left) Fig-6: Al wire-arches (right)

[after 2000 cycle thermal shocks]

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Pin (ball) attach By using a vacuum reflow oven, a ball-attach process

in which no void occur in solder balls has been developed.

はんだボール

空洞（ボイド）

Fig-7: An x-ray CT image of solder balls attached by using a

N2-gas reflow oven

Fig-8: A micro x-ray image of solder balls, have no void, attached by using

a vacuum reflow oven

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Package mounting Vibration and mechanical-shock tolerability

Thermal-shock tolerability (Relief of the heat stress which occurs due to the CTE mis-match)

Fig-9: a mounting sample of a package on a PCB

(Technical issues)

Fig-10: a sketch of mounting portion and the heat stress

Ceramic Pkg. CTE: 7 x 10-6/Ｋ

PCB CTE: 15 x 10-6/Ｋ

stress in the balls

expansion or shrink

expansion or shrink

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Vibration and mechanical-shock tolerability

The package passed the tests with good results as follows;

Visual: There is no crack or anomaly in the solder-balls and the underfill in DPAs.

Electrical conductivity: There is no significant variation (0.43 to 1.0%) before and after the tests

Package mounting

Vibration test condition: (MIL-STD-202 Method 214)

random-wave, acceleration 34.02 Grms, 3 minutes , 3 axes

Mechanical-shock test condition: (MIL-STD-202 method 213)

1500G, 0.5m sec., tearing direction, 3 times

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Package mounting

ID Pad structure

Ball material(Solder)

Stand-off Number of cycle to failure

w/o underfill w/ underfill

1-a Planer Eutectic 0.33mm 166 338

1-b Planer Eutectic & High-temp. 0.48mm 290 497

2-b Dimple Eutectic & High-temp. 0.68mm 631 816

The thermal shock test (-30 to +100 deg. C) was performed until the solder ball fail.This failure means 10% or more change of daisy chain resistance.

The goal of the number of cycles: 500 (Min.) to 1,000 (Challenge)

Dimple

Planer

Package (ID 1) Package (ID 2)

Die

Bonding wire

Fig-11: cross-section views of the packages

Thermal-shock tolerability

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NOTE: Eutectic solder: Sn63-Pb37, High-temperature solder: Sn10-Pb90

Package mountingThe higher stand-off reduces heat stress and strain in the solder-balls

Stand-off1.0 mm

Ceramic Pkg.

Stand-off0.5 mm

Ceramic Pkg.

Thermal-shock tolerability

0.2mm

0.33mm0.48mm

0.15mm 0.68mm

Fig-12: an example of strain chart of a solder ball.

Peak strain is reduced by 30% when the stand-off is reduced by half, according to the stress analysis. (Fig-12)

Fig-13: The cross-section of solder balls and pad structures

1-a 1-b 2-b

The stand-off of “2-b” to the left, that is a dimple pad structure with eutectic or high-temp. solder balls, is twice as high as that of “1-a”, that is a planer pad structure with eutectic ball only. (Fig-13)

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Package mounting Underfill suitable for mounting structure reduces heat

stress of solder balls at low temperature.

Mpa Fig-13: Stress chart at -45 deg C of solder balls,without underfill (left) or with underfill (right)

MAX 91MPaMAX 187MPa

Package

Solder

underfill

Crack

Tear-off

Package

Fig-14: A cross-section of b-2.

Thermal-shock tolerability

The underfill reduces the peak stress by almost half at -45 deg Caccording to stress analyses.

The underfill is torn from the package and this may be the reason causing the solder ball to crack.It’s possible that the material properties of the underfill are not suitable for mounting structure.

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In results of thermal shock test, the number of cycle to failure of the mount with underfill is an average of 1.7 times more than that without underfill.

But ...

Package mounting Examples of failure mode after thermal-shock test

Thermal-shock tolerability

Fig-15: A planar structure, eutectic solder,without underfill

Fig-16: A dimple structure, high-temp. solder,without underfill

Fig-17: A planar structure, eutectic solder,with underfill

NOTE: These three images are shown at the different magnifications.

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NEXT STEP On thermal-shock tolerability, minimum goal (500

cycles) has been achieved. Now, more DPAs and stress simulations will be performed to find a way to reach 1000 cycles or more.

Failure analysis of the torn underfill will be performed to find a proper material property of underfill.

Developing of BGA package for a SOI-ASIC die (e.g. HR5000S MPU).

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A vision for the future~ FY2014 FY2015 FY2016 FY2017 FY2018 FY2019 FY2020

BGA

Stack-chip

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FPGA w/EEPROMSRAM

MCM SoC ?

Flip-chip Mixed Signal ?

The virtual plan of a package miniaturization

NOTE: To turn “Virtual” to “Real”, the voices of the users who would like to use those small package devices are very important!

Thank you!

MPU

LGA and new connecting structure ?