The Computer Engineering Research Grouppc/courses/432/2015... · Web viewVideo Input to DDR Memory,...
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Video Input to DDR Memory, DDR Memory to Custom VGA Output by ECE532-2015-Group01 This describes how to take video input from the OV7670 Camera and write a frame buffer to memory through an AXI Master Interface. The following instructions describe how to create a system on the Nexys4DDR which takes video input, writes it to memory, and sets up a custom VGA controller to display through the VGA port. 1. Follow the ECE532 DDR Tutorial to create a system with MicroBlaze and the MIG. The Camera will write to DDR Memory through the MIG. 2. Copy the OV7670 and VGA folders included with this tutorial into a local directory. Include this IP by clicking on Project Settings under Project Manager in Vivado. Select IP and click Add Repository. Point to OV7670 and VGA. Click Select and OK to exit Project Settings. 3. In the block diagram created in step 1, add the OV7670 IP. This takes the raw Camera signals and converts them to AXI-Stream signals compatible with the VDMA Block. 4. Next add the Axi Video Direct Memory Access (VDMA) IP. This block converts the AXI-Stream into full AXI transactions to DDR Memory. 5. Double Click on the VDMA and re-customize as follows:
Transcript of The Computer Engineering Research Grouppc/courses/432/2015... · Web viewVideo Input to DDR Memory,...
Video Input to DDR Memory, DDR Memory to Custom VGA Outputby ECE532-2015-Group01
This describes how to take video input from the OV7670 Camera and write a frame buffer to memory through an AXI Master Interface. The following instructions describe how to create a system on the Nexys4DDR which takes video input, writes it to memory, and sets up a custom VGA controller to display through the VGA port.
1. Follow the ECE532 DDR Tutorial to create a system with MicroBlaze and the MIG. The Camera will write to DDR Memory through the MIG.
2. Copy the OV7670 and VGA folders included with this tutorial into a local directory. Include this IP by clicking on Project Settings under Project Manager in Vivado. Select IP and click Add Repository. Point to OV7670 and VGA. Click Select and OK to exit Project Settings.
3. In the block diagram created in step 1, add the OV7670 IP. This takes the raw Camera signals and converts them to AXI-Stream signals compatible with the VDMA Block.
4. Next add the Axi Video Direct Memory Access (VDMA) IP. This block converts the AXI-Stream into full AXI transactions to DDR Memory.
5. Double Click on the VDMA and re-customize as follows:
6. The Camera requires a 25.175MHz clock to produce 30 frames per second. Add a clock by double-clicking on the Clocking Wizard block and setting clk_out3 to 25.175MHz.
7. This clock also requires a separate reset module. Add a Processor System Reset block. The added blocks should look like this:
8. Connect the blocks as shown below:
9. Next, connect clk_out3 (25.175MHz) to:a. OV7670/clk25b. axi_vdma_0/s_axis_s2mm_aclkc. proc_sys_reset_0/slowest_sync_clk.
10. Next Run Connection Automation as follows:a. Connect /axi_vdma_0/M_AXI_S2MM to /mig_7series_0/S_AXIb. Connect /axi_vdma_0/S_AXI_LITE to /microblaze_0c. Connect /proc_sys_reset_0/ext_reset_in to reset (external pin)
11. Next, make the 10 unconnected OV7670 ports external ports. These blocks should now look like this:
12. Next, we will create the video output subsystem. We could use the Axi TFT Controller, but it consumes more memory bandwidth than necessary, and underflows easily when there is a lot of traffic going into and out of memory. Instead, we use a VDMA in read mode, a FIFO for clock domain crossing and a custom VGA module which was adapted from an online source1. Add vga640x480, AXI4-Stream Data FIFO, and another VDMA. Double-click and re-customize the FIFO and VDMA as follows:
1 http://www.element14.com/community/thread/23394/l/draw-vga-color-bars-with-fpga-in-verilog?displayFullThread=true
13. Run connection automation as follows:a. Connect /axi_vdma_1/M_AXI_MM2S to /mig_7series_0/S_AXIb. Connect /axi_vdma_1/S_AXI_LITE to micrblaze_0
14. Make the following ports external on the vga640x320: blue, green, red, vsync, hsync
15. Connect the remaining ports as shown below. The VDMA as well as the slave side of the FIFO must be connected to the 100MHz clock (clk_out1) and related aresetn signal. The VGA controller and master side of the FIFO must be connected to the 25.175MHz clock (clk3_out) as well as the related aresetn signal. This is similar to the Camera subsystem setup.
16. The file pin_constraints.xdc in this package contains the pin constraints for the external ports for the camera and the VGA. Add these to the constraints file. Ensure the ports in this file match the ports in your external design.
17. Generate the block design.
18. Run synthesis, implementation, bitstream generation, and export to SDK.
19. In the address editor, check the base address of TFT, VDMA(Camera), VDMA(VGA), and MIG. Suppose they are as follows:
a. TFT: 0x44A0000b. VDMA(Camera): 0x44A10000c. VDMA(VGA): 0x44A20000d. MIG: 0x80000000
20. Use the following code to display to screen:
// Horizontal and Vertical Resolution of the Camera#define DISPLAY_COLUMNS 640#define DISPLAY_ROWS 480
// TFTvolatile unsigned int * TFT = (unsigned int *)0x44A00000;
// VDMA (CAMERA)volatile unsigned int * VDMA_CAM = (unsigned int *)0x44A10000;volatile unsigned int * VDMA_CAM_CR = (unsigned int *)0x44A10030;volatile unsigned int * VDMA_CAM_AD = (unsigned int *)0x44A100AC;volatile unsigned int * VDMA_CAM_ST = (unsigned int *)0x44A100A8;volatile unsigned int * VDMA_CAM_HS = (unsigned int *)0x44A100A4;volatile unsigned int * VDMA_CAM_VS = (unsigned int *)0x44A100A0;
// VDMA (VGA)volatile unsigned int * VDMA_VGA = (unsigned int *)0x44A20000;volatile unsigned int * VDMA_VGA_CR = (unsigned int *)0x44A20000;volatile unsigned int * VDMA_VGA_AD = (unsigned int *)0x44A2005C;volatile unsigned int * VDMA_VGA_ST = (unsigned int *)0x44A20058;volatile unsigned int * VDMA_VGA_HS = (unsigned int *)0x44A20054;volatile unsigned int * VDMA_VGA_VS = (unsigned int *)0x44A20050;
int main(){
*(VDMA_VGA_CR) = 0x1; // Enable VDMA*(VDMA_VGA_AD) = 0x80000000; // The base address of the frame
buffer*(VDMA_VGA_ST) = 4096; // Line size (stride value)*(VDMA_VGA_HS) = 4*DISPLAY_COLUMNS; // Horizontal Pixel Count *
4B/pixel*(VDMA_VGA_VS) = DISPLAY_ROWS; // Vertical Line Count
*(VDMA_CAM_CR) = 0x1; // Enable VDMA*(VDMA_CAM_AD) = 0x80000000; // The base address of the frame
buffer*(VDMA_CAM_ST) = 4096; // Line size (stride value)*(VDMA_CAM_HS) = 4*DISPLAY_COLUMNS; // Horizontal Pixel Count *
4B/pixel*(VDMA_CAM_VS) = DISPLAY_ROWS; // Vertical Line Countreturn 0;
}
After setting the vertical line count, the VDMA turns on and starts reading/writing at 30 frames per second to the specified address. TFT reads from this address and displays to screen.
NotesThe VDMA writes data in the same format that the TFT controller uses, so a TFT controller could be used instead. However, only 16 bits are necessary for each pixel, so a more efficient encoding could be used to reduce memory bandwidth requirements by modifying the OV7670, vga640x480, and VDMAs. This should be fairly simple to do and we leave it up to users of the tutorial.
At the moment, each frame buffer occupies 2MB (1024x512 screen size, 4 bytes per pixel). However, only the top left corner contains valid data (top left 640 x 480 pixels). Each pixel contains RGB565 data, and the TFT reads it assuming it is RGB666, which we truncate above to RGB444.
VDMA writes: 0bXXXX XXXX RRRR R000 GGGG GG00 BBBB B000 (RGB565)TFT reads: 0bXXXX XXXX RRRR RRXX GGGG GGXX BBBB BBXX (RGB666)Screen Display: 0bXXXX XXXX RRRR XXXX GGGG XXXX BBBB XXXX (RGB444)
In the OV7670 and VGA folders, there are projects which can be used to modify the IP block internals. Just make sure to re-package the IP and upgrade in any project in which it is used. Look at the VDMA and Camera OV7670 datasheets to see how the various input and output signals should be set and timed.
