The CMOS Fabrication Process & Design Rules
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Transcript of The CMOS Fabrication Process & Design Rules
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7/30/2019 The CMOS Fabrication Process & Design Rules
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.1 Brockman, ND, 2004
CSE/EE 462: VLSI DesignFall 2004
The CMOS Fabrication Processand Design Rules
Jay Brockman
[Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State
adaptation of Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.2 Brockman, ND, 2004
Growing the Silicon Ingot
From Smithsonian, 2000
Silicon Wafer
Single die
Wafer
From http://www.amd.com
ND Multi-Project Reticle: Rocket Chip
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.5 Brockman, ND, 2004
CMOS Process
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.6 Brockman, ND, 2004
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
One full photolithographysequence per layer(mask)
Built (roughly) from thebottom up
5 metal 2
4 metal 1
2 polysilicon
3 source and drain diffusions
1 tubs (aka wells, active areas)
exception!
oxidationoptical
mask
process
step
photoresist coatingphotoresist
removal
(ashing)
spin, rinse,
dryacid etch
photoresist
development
stepper
exposure
Photolithographic Process CMOS Inverter
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.9 Brockman, ND, 2004
P-Type Substrate and N-Well
P-type substrate
NMOS devices
go here
N-well
PMOS devices
go here
N-well mask
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.10 Brockman, ND, 2004
Active Area
deposited
nitride layer
active mask defines
p-type and n-typemosfet locations
(drain-gate-source)
Field Oxide Growth
field oxide
gate oxide
Thick field oxideelectrically isolates
transistors
Nitride prevents fieldoxide growth
Thin gate oxide grownafter nitride removed
o2
o2o2
o2
o2
o2o2
o2o2
o2
SiO2 formation consumes Si
Si-SiO2 interface below
original Si surface
Polysilicon Gate
poly mask
added to layout
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.13 Brockman, ND, 2004
P-Select Mask and N-Type Source/Drain Implant
n-type
implant p-select covers p-type
source/drain regions
select mask mustoverlap active areas
n-type ion implantcreates n-typesource/drain regions
high temperatureanneal repairs silicon
lattice and causesdiffusion of implantedions
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.14 Brockman, ND, 2004
N-Select Mask and P-Type Source/Drain Implant
finished mosfetsp-type implant both select masks added
Contact Cuts Metal 1
non-planar surface
Vi 1 d M l 2 Ad d M lli i
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.17 Brockman, ND, 2004
Via 1 and Metal 2
Multilevel interconnectfabrication processes planarize
between layers (expensive)
MOSIS SCMOS does not allowstacked vias
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.18 Brockman, ND, 2004
Advanced Metallization
Advanced Metallization A Modern CMOS Process
p-
p-epi
p well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
Dual-Well Trench-Isolated CMOS
field oxide
D i R l Wh H D i R l ?
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.21 Brockman, ND, 2004
Design Rules
Interface between the circuit designer and processengineer
Guidelines for constructing process masks
Unit dimension: minimum line width
z scalable design rules: lambda parameter
z absolute dimensions: micron rules
Rules constructed to ensure that design works evenwhen small fab errors (within some tolerance) occur
A complete set includes
z set of layers
z intra-layer: relations between objects in the same layer
z inter-layer: relations between objects on different layers
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.22 Brockman, ND, 2004
Why Have Design Rules?
To be able to tolerate some level of fabrication errorssuch as
1. Mask misalignment
2. Dust
3. Process parameters(e.g., lateral diffusion)
4. Rough surfaces
Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on eachlayer to maintain that object after fab
z minimum line width is set by the resolution of the patterningprocess (photolithography)
Minimum spaces between objects (that are notrelated)on the same layer to ensure they will not short after fab
0.15
0.150.3 micron
0.3 micron
Intra-Layer Design Rules
Metal24
3
10
9
0Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
I t L D i R l O i i t t
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.25 Brockman, ND, 2004
Inter-Layer Design Rule Origins
1. Transistor rules transistor formed by overlap of activeand poly layers
Transistors
Catastrophic
error
Unrelated Poly & Diffusion
Thinner diffusion,but still working
CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.26 Brockman, ND, 2004
rans stor ayout
1
2
5
3
Transistor
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
Inter-Layer Design Rule Origins, Continued
2. Contact and via rules
M1 contact to p-diffusion
M1 contact to poly
Mx contact to My
Contact Mask
Via Masks
0.3
0.14
both materialsmask misaligned
M1 contact to n-diffusion
Contact: 0.44 x 0.44
Vi d C t t
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CSE/EE 462 L05 CMOS Fabrication Process and Design Rules.29 Brockman, ND, 2004
Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2