The Challenges in Making NIL Master Templates · eBeam Initiative Luncheon at SPIE 2014 © 2011 Dai...
Transcript of The Challenges in Making NIL Master Templates · eBeam Initiative Luncheon at SPIE 2014 © 2011 Dai...
© 2011 Dai Nippon Printing Co.,Ltd. All Rights Reserved.
The Challenges in Making NIL
Master Templates
Naoya Hayashi
Dai Nippon Printing Co., Ltd.
A Member of the eBeam Initiative
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OUTLINE
Recent Progress in Nanoimprint for CMOS
Challenges in NIL master templates
Patterning challenges
Summary
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NIL template strategy
EB writing
Imprint
Wafer imprint
High quality
master template
Multiple replica
templates
Multiple replica templates will be duplicated from high
quality EB written master template.
Replica templates
used as stamps for
wafer lithographyMaster
Replica
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Template fabrication process
EB writing
Imprint
Master
Develop Etching Repair
Replica
Etching
Resolution
IP control
CDU
Uniformity Inspection
Fine repair
Defect
IP control
CDU
Uniformity
Defect
Inspection
Zero defect
master
Replica
Master Wafer imprint
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Comparison between Optical masks
and NIL templates
NIL template Optical/EUV mask
Lithography Near field lithography Far field lithography
Magnification X1 X4
Field size 26mmx33mm 112mmx132mm
Substrate 6025 Quartz 6025 Quartz
Mask fabrication Master: EB / Replica: NIL EB lithography
EB process High resolution / low sensitivity
/ Non-CAR
High sensitivity / CAR
Difficulties in NIL template fabrication Master template resolution and throughput are the most critical
issues for X1 lithography Defect control becomes difficult due to near field (contact)
lithography Duplication from master to replica template degrades master
template performance
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General performance status at
hp3x nm generation
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CD map of the current template
Replica Template CD uniformity
CDU(3σ) = 1.5nm
○ : -● : +
Error sources:
Master uniformity,
RLT uniformity,
Etching uniformity,
need to be optimized.
RLT
(Residual film
thickness)
Master
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IP : Master & Replica
10nm 10nmMaster Replica
Replica residual
x=2.00nm, y=2.48nm
Image placement has been reached to less than 2.5nm.
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Master residual
x=1.13nm, y=1.82nm
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1
10
100
1000
10000
100000
1000000
Q3 Q4 Q1 Q2 Q3 Q4 H1 H2
2011 2012 2013
DD:0.6pcs/cm2
Non-fills
Process defects
History of replica template defect improvement
2014
Master damages
Plugs
Defect density (DD) has been reduced to 0.6 pcs./cm2 by defect
source analysis and process optimization.
Defe
ct
density (
pic
s/s
q.c
m)
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Defect density of replica
Defect density of replica template is now less than 5 pieces/cm2
0
1
2
3
4
5
6
7
8
9
10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Defe
ct
densi
ty (
pics/
sq.c
m)
Number of replica
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NIL Template Readiness
Templates are ready for use!
Target Status
Defectivity (pcs/cm2) 1.0 0.6
CD Uniformity (3σ, nm) 2.2 1.5
Image Placement (3σ, nm) 2.5 2.5
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* Status of hp2x and 1x nm generation were updated at the morning
sessions of today.
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Patterning Challenges
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1x nm template
HP22nm HP20nm HP19nm HP18nm HP17nm
Master
Replica
1x nm replica fabrication is confirmed down to 18nm LS.
Master resolution is a key to extend NIL.
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HP22nm HP20nm HP19nm HP18nm HP17nm
Master
Replica
Multi-beam Mask Writer:10nm beam resolution
EB with Non-CAR
MBMW with Non-CAR
15nm L&S
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Resist images
hp14nmhp16nm hp15nm hp13nm
Resolution with 100kV EB Writer
100KeV EB
with Non-CAR
MBMW with Non-CAR
15nm L&S
Multi-beam Mask Writer:10nm beam resolution
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Summary
マスター
NIL template progresses in CMOS application CD uniformity of 1.5nm has been obtained. Image placement of within 2.5nm residual distortion has
been obtained. Defect density on templates has been improved to zero
defect on master template, and <1 defect/cm2 on
replicated template at hp3x nm generation. We have
been working on further improvement on hp2x/1x nm.
Patterning challenges in master templates Resolution down to 1x nm and beyond Throughput
Promising solution Multi e-beam mask writer will provide the solution!
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