The Blixer, A Wideband Balun-LNA-IQ-Mixer Topology

2706 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 12, DECEMBER 2008

The BLIXER, a Wideband Balun-LNA-I/Q-MixerTopology

Stephan C. Blaakmeer, Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE,Domine M. W. Leenaerts, Fellow, IEEE, and Bram Nauta, Fellow, IEEE

Abstract—This paper proposes to merge an I/Q current-com-mutating mixer with a noise-canceling balun-LNA. To realize ahigh bandwidth, the real part of the impedance of all RF nodesis kept low, and the voltage gain is not created at RF but inbaseband where capacitive loading is no problem. Thus a highRF bandwidth is achieved without using inductors for bandwidthextension. By using an I/Q mixer with 25% duty-cycle LO wave-form the output IF currents have also 25% duty-cycle, causing2 times smaller DC-voltage drop after IF filtering. This allowsfor a 2 times increase in the impedance level of the IF filter,rendering more voltage gain for the same supply headroom. Theimplemented balun-LNA-I/Q-mixer topology achieves 18 dBconversion gain, a flat noise figure 5.5 dB from 500 MHz to7 GHz, IIP2 � �20 dBm and IIP3 � 3 dBm. The core circuitconsumes only 16 mW from a 1.2 V supply voltage and occupiesless than 0.01 mm� in 65 nm CMOS.

Index Terms—CMOS integrated circuits, direct conversion,high-linearity mixer, linearity, low noise, low-noise amplifiers,low-power electronics, merged LNA and mixer, microwave in-tegrated circuits, microwave receivers, multi-standard, noisecanceling, noise cancellation, radio receivers, RF transceiver,software defined radio, software radio, UHF integrated circuits,wideband LNA, wideband matching, wideband receiver, widebandRF front-end, zero IF.

I. INTRODUCTION

W IDEBAND radio receivers have recently drawn signif-icant research interest, e.g., for emerging software-de-

fined radio (SDR) architectures and ultra-wideband (UWB)communication standards [1]–[3]. Such applications call forradio receivers covering the frequency range from a few hun-dred MHz up to about 6 GHz (SDR) or even 10 GHz (UWB).Co-operability with other communication devices (e.g., cel-lular, WLAN) operating in the same spectrum is mandatory,setting especially stringent demands on the wideband linearityof such a receiver. A single-ended RF input avoids the useof an external broadband balun and its accompanying losses.Compared to a differential input it also requires less switches

Manuscript received April 11, 2008; revised June 21, 2008. Current versionpublished December 10, 2008.

S. C. Blaakmeer is with the University of Twente, CTIT Institute, IC Designgroup, 7500 AE Enschede, The Netherlands, and also with Axiom IC Twente,Enschede, The Netherlands (e-mail: [email protected]; [email protected]).

E. A. M. Klumperink and B. Nauta are with the University of Twente, CTITInstitute, IC Design group, 7500 AE Enschede, The Netherlands.

D. M. W. Leenaerts is with NXP Semiconductors, Research, Eindhoven, TheNetherlands.

Digital Object Identifier 10.1109/JSSC.2008.2004866

to connect the RF input to different RF filters and/or antennanetworks [2].

Recently, some wideband balun-LNAs with high linearityhave been proposed offering a wideband input match, gainand single-ended to differential conversion [4], [5]. Activemixers have a capacitive input impedance, i.e., the gate of atransistor. When a passive mixer is used, a voltage buffer ortransconductance stage is often required between the LNAoutput and the input of the mixer(s). Also this intermediatestage between LNA and mixer loads the LNA capacitively. Dueto this capacitance load, it is challenging to realize high LNAgain over a large bandwidth. Inductive peaking has been usedto still achieve 6 GHz bandwidth [3], [6], however we wouldlike to avoid the use of area consuming on-chip inductors inexpensive nanometer scale CMOS processes. Moreover, therequirements on linearity in the input stage of a mixer will behigher than for the LNA, because of the voltage gain of theLNA. As the input signal of the mixer is still at a high frequencyit is challenging to obtain high linearity there. For instance,negative feedback techniques are not very effective becauseloop gain is limited at GHz frequencies.

This paper proposes a solution to the above described prob-lems via a so-called “BLIXER” topology. The topology actuallycomprises an active balun, LNA and mixer in a single circuit.Without bandwidth extension inductors, it still easily achievesmore than 7 GHz bandwidth in 65 nm CMOS by merging a cur-rent commutating I/Q-mixer with a noise-canceling balun-LNA[7]. In this paper we explain the operation of the topology in de-tail and analyze its gain and noise behavior. Also we compareit to alternative topologies to illustrate its competitive perfor-mance.

The paper is structured as follows. Section II quickly reviewsrecently proposed balun-LNAs to show why it is challenging tosimultaneously achieve high gain and high bandwidth. Then weintroduce the BLIXER topology in Section III and show how itcan simultaneously achieve high gain and high RF bandwidth.In Section IV, we analyze the gain and noise figure of theBLIXER in terms of component design parameters. Section Vdiscusses the circuit implementation and measurement results,while Section VI draws conclusions.

II. BALUN-LNA GAIN AND BANDWIDTH LIMITATION

A. Balun-LNA Topology

Fig. 1 shows a balun-LNA consisting of a parallel operatingcommon gate (CG) and common source (CS) stage. Both stagesare cascoded to allow for realizing a high voltage gain via re-sistor and . The CG stage realizes wideband input

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BLAAKMEER et al.: THE BLIXER, A WIDEBAND BALUN-LNA-I/Q-MIXER TOPOLOGY 2707

Fig. 1. Balun-LNA of [5] with cascodes added. Signal � is amplified and con-verted to a balanced RF output signal, while the noise � of the impedance-matching CG transistor is canceled.

impedance matching and gain, while the CS stage realizes ananti-phase output signal. The circuit can simultaneously achievenoise canceling, distortion canceling and output balancing asdiscussed in detail in [5]. In a CG stage only, the noise of theCG transistor would be dominant when the input impedanceis matched to . However, using a prop-erly designed CS stage this noise ( in Fig. 1) can be can-celed. The noise current generates a noise voltage on thesource resistor and a larger voltage in anti-phase across

. The input noise voltage is amplified bythe CS stage to , which is in-phase and fully correlatedwith . For equal CG and CS stage gain, the noise due to theCG transistor is fully canceled at the differential output, whilethe signal contributions to the output signal add up to create abalanced output. This noise-canceling technique was proposedin [8], [9], while different circuit topologies were generated andcompared in [10]. The parallel CS-CG topology (or balun-LNA)was found to be one of the best performing topologies (topology“e”) in Figs. 4.22 and 4.23 of [10]). It cancels the noise of theCG transistor in order to obtain a noise figure (NF) close to orlower than 3 dB [3]–[6], [9], [11]–[13]. To achieve this low NF,the impedance of the CS stage needs to be scaled down timeswith respect to the CG stage, where is typically in the orderof 4 (see Fig. 2).

The CG stage is biased using an external inductorto obtain low-noise operation and save valuable voltage head-room. Depending on the application this inductor can either bevery large (RF-choke) for wideband operation, or smaller andwell-defined to tune to a dedicated band and realize RF pre-fil-tering. Especially for software defined radio transceivers this is arealistic approach, as some RF pre-filtering is commonly neededto make the linearity requirements of a CMOS transceiver fea-sible [14]. Using an external inductor at the input of a CMOSchip allows for realizing external re-configurability and gener-ally the quality factor of the off-chip inductors is higher thanon-chip realizations.

B. Achievable Gain and Bandwidth

The voltage gain of transistors in modern CMOS processesis low. Cascoding is an effective method to increase the voltagegain. The output resistance of the transconductor (input tran-sistor plus cascode) is increased, so that increasing and

Fig. 2. Practical balun-LNA design for � � � illustrating typical componentdimensioning and biasing in a 65 nm CMOS technology.

in Fig. 1 still improves the voltage gain. Next to this, thecascodes lower the effective input capacitance, as the Miller ef-fect is reduced (most important for the CS transistor, as it is

-times wider than the CG transistor). This helps to improvethe bandwidth over which good input impedance matching isachieved.

Let us now consider the gain and bandwidth of thebalun-LNA, neglecting the effect of body effect for sim-plicity. In Fig. 2 a typical design in a 65 nm CMOS technologyis shown. The transconductance of the CG transistor is 20 mSto realize impedance matching to a 50 source. This re-quires about 1.5 mA of biasing current for a transistor with

m m at a moderate overdrive voltage of. We design the voltage drop across the load

resistor to be 0.6 V, half of the 1.2 V supply voltage. This leaves0.6 V for the sum of ’s of the input and cascode transistor,which is sufficient to keep each MOS transistor in saturation

. With 1.5 mA bias current in the CG stage and0.6 V headroom, the CG load resistor becomes 400 .If we use the same components and biasing in the CS stage, andneglect the body effect, then DC-bias and modulus of the gainof the stages are equal. Since the CG noise is cancelled, theCS noise dominates in the LNA. To achieve acceptable noise,the impedance level in the CS stage is assumed to be scaleddown by 4 times (80 mS and 100 ). This does not affectthe DC-voltages and voltage gain. With mS and

, the voltage gain of the CG stage is

(1)

As the gain of the CS stage is equal but with opposite sign, thetotal voltage gain of the CG-CS LNA from single-ended inputto differential output is 2 times higher:

dB (2)

A high voltage gain can thus be obtained by using this parallelconnection of a CG and a CS stage. However, the bandwidthassociated with this high gain is limited due to the dominantpole at the output of the CG stage. For a 3 dB bandwidth of


10 GHz, the loading capacitance is most critical at the CGside and should be smaller than

(3)

The load capacitance is the sum of the input capacitance ofthe next stage (input stage of the mixer) and the capacitance ofthe cascode transistor. For a cascode transistor with

(same size as the CG transistor), the capacitance ofthe only the cascode is already close to the maximal allowedcapacitance:

(4)

where the two dominant capacitances seen at the drain of thecascode are the gate-drain overlap capacitance and thedrain-bulk junction capacitance . This means that no(capacitive) load can be driven when a 3 dB bandwidth in theorder of 10 GHz is required. This clearly shows that there is abandwidth problem at the load of the CG side for high enoughvoltage gain. As one of the goals in this design was to avoid theuse of on-chip inductors, no inductive peaking techniques [3],[6] will be used to broaden the bandwidth. The BLIXER topologywe propose in the next section achieves high bandwidth withoutrequiring on-chip inductors.

III. THE BLIXER TOPOLOGY

A. The Basic BLIXER Topology

In Fig. 3, the principle of the BLIXER topology is shown. Com-pared to the balun-LNA of Fig. 1, the same CG and CS tran-sistors are used while the cascode transistors are now part of acurrent commutating mixer. Instead of one, both the CG and theCS side have now two cascode (or mixer) transistors, which areperiodically switched on and off, with frequency . The cur-rent from the CG and CS transistor can always flow towards theloads (discussed in Section III-B), as at any moment in time oneof its mixer (cascode) transistors is active, i.e., the LO signalhas 50% duty-cycle. At the drains of the mixer the signal of in-terest is down converted to an intermediate frequency (IF) whichis much lower than the RF frequency. In the BLIXER topology,the capacitance at the loads sets the IF bandwidth, instead of theRF bandwidth in case of the balun-LNA. As the IF bandwidth ismuch lower than the RF bandwidth, the capacitance at the loadscan be much higher. Furthermore, the capacitive load of the nextstage can be absorbed into the capacitance of the IF filter. Thebandwidth problem at the load of the CG stage, described in theprevious section, is thus solved without requiring inductors forbandwidth extension.

There are only three RF signal nodes in the BLIXER topology:the input node and the two drain nodes of the CG and CS tran-sistor. This means that in the complete down-converter there areonly three nodes that can limit the RF bandwidth. For impedancematching, the real part of the input impedance of the circuitequals . When the real part of the impedances at thetwo drains nodes is low (indicated in Fig. 3), the bandwidth atthese nodes can be high. For switch transistors equal to the cas-code transistors in Fig. 2, the real parts at the drains of the CGand CS transistors are 50 and 12.5 , respectively, (

Fig. 3. Basic BLIXER topology consisting of the balun-LNA core of Fig. 1 withdoubled cascode transistors driven by an LO implementing down-conversionmixing to IF.

of mixer transistors). Thus, all RF node impedances are in theorder of 50 or lower, allowing for high bandwidth.

The CG and CS transistors can be considered as a transcon-ductor converting to currents and (seeFig. 3). These currents are largely conveyed to the IF outputvia the switched cascode transistors, provided the real inputimpedance of these transistor is lower than the parasitic capac-itance to ground. Only modeling gate-source capacitances, theRF bandwidth limitation due to the switched cascode transistorswill be close to , which is typicallyan order of magnitude higher than for the balun-LNA with avoltage gain in the order of 20 dB.

B. Noise Canceling at IF Instead of at RF

Consider now the real part of the load impedance, which con-sists of four resistors instead of two in the balun-LNA. A bitmore complex load is used in order to maintain the noise-can-celing conditions in both LO switch positions. In Fig. 4, the ac-tive part of the circuit is shown when LO+ is high. As in Fig. 1,the CG side has as load, while the load in the times scaledCS side is . The IF output voltage is sensed at the combinedCG and CS load, where the lower capacitance of the current-lessbranch effectively works as level shifter. As the impedance ofthe CS side is times lower than for the CG side, it has a lownoise contribution and still the gain of the CG and the CS sides isequal. As the gain of both sides is equal, the noise of the CG tran-sistor is canceled in the same way as in the balun-LNA of Fig. 1Note that in the BLIXER topology the noise canceling takes placeafter the frequency (down) conversion i.e., at IF. The noise-can-celing down-converter in [15] also has this property. However,it is much less power efficient as cascaded stages instead ofcascoding (i.e., stacking of transistors with current re-use) wasused, while also high overdrive voltages were used to push thebandwidth.

C. The I/Q-BLIXER Topology

Quadrature outputs are required in order to implement a low-or zero-IF receiver. It is possible to create quadrature outputsstarting with signal currents and from a differential pair, byconnecting two switching pairs to each current, and using a sine


Fig. 4. Equivalent circuit of the BLIXER when �� side is active. As in Fig. 1,the current of the CG stage flows into its load impedance � �� , andthe CS current flows into � �� , which impedance is � times smaller.

and cosine wave to drive the two pairs [16], [17]. In principlethis is also possible with the asymmetrical balun-LNA currents

and , provided that the switch transistors and load networkare scaled as shown in Fig. 5. We will refer to this circuit as theI/Q-BLIXER. Simulations show that it is possible to use sine andcosine LO signals in I/Q-BLIXER, however this seems mainlyattractive for narrowband receivers like in [16] and [17]. Fornarrowband receivers, the required sine and cosines can be gen-erated via a quadrature VCO with relatively small tuning range.For multi-standard receivers or software defined radio we wantmuch wider tuning range. Digital frequency synthesis methodsexploiting Moore’s law are then preferred [18]. However, usingtwo square waves with 50% duty cycle with a relative delay of1/4 period gives 25% overlap between LO I and LO Q pulses.Using a 25% duty-cycle, this overlap can be avoided and it ispossible to “isolate” the I- and Q- current-path in time. Hence,the full of the input devices is available to either the I- orQ-output of the circuit which is beneficial for the conversiongain. Furthermore, we will show in the next section that, withoutcompromising the voltage headroom, it is possible to double thevalue of the IF load resistors to increase the gain.

D. Conversion Gain and Voltage Drop Load Resistors

The voltage conversion gain from single-ended input to dif-ferential output of the BLIXER topology (Fig. 3) can be calcu-lated as

(5)

Fig. 5. I/Q-BLIXER driven by LO waveforms with 25% duty cycle, which al-lows for sharing currents � and � � � by an I- and Q- mixer.

where, after the first equal sign, the factor equals the fun-damental Fourier component of a 50% duty-cycle (LO)-signaltoggling between 0 and 1. The term between brackets is thecombined voltage gain of the CG and CS side. The factor 2 isbecause a differential LO signal is used, and the final factor isbecause only the down converted half of the signal is used, asshown in (6) at the bottom of the page.

Similarly, the voltage gain of the I/Q-BLIXER (Fig. 5) with25% duty-cycle LO equals

(7)

where the factor equals the fundamental Fourier compo-nent of a 25% duty-cycle LO signal.

Compared to the BLIXER, the conversion gain of the I/Q-BLIXER is lower due to the lower duty-cycle, assuming the same

’s and load resistors are used. However, in the I/Q-BLIXER

larger load resistors can be used, as shown below.The average (or DC) voltage drop across the load resistors in

the BLIXER is

(8)

This is because with 50% duty-cycle LO, half of the periodthe CG transistor bias current flows through and inthe other half the CS bias current a current flows through

.In the I/Q-BLIXER, the DC-voltage drop across the load equals

(9)

(6)


Fig. 6. Q-side of the I/Q-BLIXER showing the branch currents and node volt-ages.

as with 25% duty-cycle the CG and CS bias current flow onlyfor 1/4 of the period through one of the loads (the waveformsare shown in Fig. 6). The capacitors in the load average thesepulses of current and filter out the high-frequency components.

Comparing (8) with (9) we see that, assuming equal transcon-ductor bias currents ( and ) and equal voltage dropacross the load, we can double the load resistors ( and

) in the I/Q-BLIXER. This doubling of the load resistors6 dB compensates the gain reduction caused by the lower

duty-cycle 3 dB and results in 3 dB more conversion gainfor the I/Q-BLIXER compared to a 50% duty cycle BLIXER.

A numerical example clarifies this further. Using exactly thesame components and biasing as the balun-LNA of Fig. 2 forthe BLIXER results in the same average voltage drop across theload resistors (0.6 V). Using (5) the conversion gain equals:

dB, which is about 4 dB lower than thegain of the balun-LNA. In the I/Q-BLIXER we can double theload resistors, i.e., and , for equalload voltage drop. This results in an I/Q-BLIXER with a gainof dB, which is only 1 dB lower than thebalun-LNA, and 3 dB higher than the BLIXER.

E. Similar Topologies in Literature

In [19], a MICROMIXER cell with single-ended input and dif-ferential output was proposed. It uses a bipolar equivalent of theCG-CS input stage. However the possibility of noise cancelingwas not recognized nor exploited. Two of these mixer-cells andan additional LNA would be needed for I/Q operation with ac-ceptable NF.

A merged LNA and I/Q-mixer was published in [16]. How-ever, this design is narrowband, uses 3 on-chip inductors and re-quires a differential RF input signal. In contrast, the I/Q-BLIXER

topology does not require on-chip inductors, achieves widebandsingle-to-differential operation and I/Q-mixing in one circuitcell.

In [20], a “merged CMOS LNA and Mixer exploiting noisecancellation” is proposed, which seems related at first sight(“merged” and “noise cancellation”). However, a closer lookshows this combination actually uses a folded mixer withseparate bias currents for the LNA and mixer core (no cur-rent re-use). Also the used noise canceling is of another typerendering partial canceling. This circuit has no I/Q outputs,

requires a differential input (and external balun) and uses fouron-chip inductors. Still, the circuit also uses down-conversionvia current commutation directly on the output current of a CGinput stage, and is in that sense related. We will compare itsperformance at the end of the paper (see Table I).

F. Attractive Properties of BLIXER Topologies

Apart from the bandwidth advantages, the BLIXER topologyhas some other advantageous properties with respect to linearity,balancing of the output and power consumption, as discussedbelow.

Similar as the noise, the distortion generated by the CGtransistor is canceled [4], [5], [11] and the load resistors arelinear. If the switch transistors are well switched, the mixertransistors convey the output current of the CG-CS stage tothe output without much distortion (assuming is signif-icantly lower than the somewhat nonlinear output impedanceof the CG/CS transistors). This means that the only remainingsource of nonlinearity in the BLIXER is the V-to-I conversionof the CS transistor. In a traditional cascade of voltage-gainLNA and active mixer, the mixer input transistors experiencealmost an order of magnitude more voltage swing that the RFinput, and hence often limit the overall linearity. As the CStransistor of the BLIXER directly senses the RF input voltagewithout pre-amplification, relatively high linearity can easilybe obtained.

Compared to the balun-LNA of Fig. 1, the BLIXER also im-proves on the quality of the balance of the output signal. This isbecause the output load network is completely symmetrical inthe BLIXER, instead of the and in the balun-LNA. More-over, both the CG and the CS stage contribute to both outputsignals (each half of the time). Even if the ratio of and

is not exactly equal to the ratio of the CS- and CG-loadimpedances (1: ), still the gain balancing at the IF output is un-affected. Such a mismatch does make the noise canceling lessperfect, but as shown in [8], [10] noise canceling is robust forsuch errors as 20% mismatch still only gives 0.1 times thenoise of the CG transistor (without canceling).

The power efficiency of the BLIXER is also attractive as thebias-current of the balun-LNA is re-used to realize the mixerfunctionality. Especially when the I/Q configuration is used,a complete I/Q receiver with high conversion gain is obtainedre-using the power of balun-LNA. Of course, the LO drivers dorequire additional power, but this power will scale down in fu-ture technologies with Moore’s law.

IV. IMPLEMENTATION AND SIMULATIONS

In the following sections we will discuss the actual chip im-plementation of the BLIXER in CMOS 65 nm technology and wewill evaluate its performance via simulations, comparing to thebalun-LNA and basic BLIXER.

A. Input Transconductor Implementation

The implementation of the input transconductor is shown inFig. 7. As discussed in Section III-F the CS stage determinesthe linearity of the circuit. In order to obtain high (third-order)linearity the CS transistor should be biased with a high .However, at a high , the of a transistor is low, which


Fig. 7. Implementation of the input stage. The CS transistor is split is a PMOSand an NMOS transistor.

means that a large bias current is required to reach a certain .This reduces the voltage headroom as this bias current has toflow through the loads. Therefore, the CS stage is implementedusing a PMOS and a NMOS transistor. Both the NMOS andPMOS can be biased at a high for high third-order linearity,whereas also the second-order distortion can be low in this in-verter-type of circuit. The effective of this inverter based CSstage is designed to be about 4 times higher than the effectiveof the CG transistor. Also the DC-output current the CS stageinverter is designed to be approxi-mately 4 times higher than the bias current of the CG transistor.Besides the high linearity, another advantage of the inverter-typeCS is that the PMOS transistor can be DC-coupled to the input,which reduces the AC-coupling related signal-loss to the inputof the CS stage.

The CG transistor is biased using an inductor which puts thesource of the CG transistor at DC-ground, as indicated in Fig. 7.Because the biasing of the CG transistor does not require anyDC-voltage drop, the voltage headroom of the CG and CS sideis equal. A large bias inductor nH can be used as itis placed off-chip. This large inductor allows for good matchingin the lower frequency range. In the higher frequency range,the parasitic capacitance of the inductor dominates. To-gether with the total bondwire inductance and input capacitance( and ) a broadband-matching -network is formed,which results in impedance matching up to high frequencies.

B. Switches and Load Implementation

The width of the switches switching the CG current waschosen at 40% of the width of the CG transistor. The reasonfor choosing a small(er) width is to reduce the input capaci-tance of the switches. The area of a transistor determines its1/f-noise. In order to lower the 1/f-noise contribution of theswitch transistors, their area was increased by setting the lengthto 100 nm, instead of using minimum length (65 nm) devices.As overlap and junction capacitances dominate the capacitanceof transistors with small length, increasing the length increasesthe input capacitance of the switches only slightly. The CSswitches are 4 times wider than the CG switches.

The impedance ratio of the CG and CS part of the load wasdesigned equal to the ratio of effective CS and CG transconduc-tance, which is nominally slightly lower than 4. The bandwidthof both parts of the loads was designed in the order of 300 MHz,enough to handle UWB signals in a zero-IF architecture.

Fig. 8. Gain of the balun-LNA, basic BLIXER (50% LO duty-cycle) and I/Q-BLIXER (25% LO duty-cycle). Note that the BLIXERs have much higher band-width (9.5 GHz ).

C. Conversion Gain and Noise Figure Simulations

In this section we will evaluate the gain and noise figure ofthe BLIXER and the I/Q-BLIXER and compare it to the stand-alone balun-LNA. The aim of this comparison is to show thatthe BLIXERs can have more bandwidth, at practical values forthe gain and noise figure. In order to make a fair comparison, allthree circuits use the input stage described in Section IV-A, andthe dimensions of the (switched or biased) cascode transistorsare equal. Choosing this, the bias current of the three circuitscores is equal. However, the BLIXER and I/Q-BLIXER have morefunctionality than the balun-LNA, as these circuits also perform(I/Q) down-conversion.

As discussed in Section III-D, the load impedance of theBLIXER and the balun-LNA needs to be half the load impedanceof the I/Q-BLIXER, in order to keep the average voltage dropacross the loads equal in all three cases. The loads in thebalun-LNA and BLIXER are halved by placing two I/Q-BLIXER

loads in parallel. The switches of the BLIXER and I/Q- BLIXER

are driven with ideal 50% and 25% duty-cycle LO signalsrespectively (rise and fall time 1% of the LO period).

Fig. 8 shows the voltage conversion gain of the BLIXERs asa function of the input signal frequency for an IF of 50 MHz.Also the voltage gain versus signal frequency of the balun-LNA,loaded with 100 fF on both outputs, is shown. Clearly, the band-width of the BLIXERs is much higher 9.5 GHz than thebandwidth of the balun-LNA 3.5 GHz . As expected, the(low frequency) conversion gain of the I/Q-BLIXER is about 1dBlower than the gain of the balun-LNA.

Fig. 9 shows the Noise Figures of the three topologies. Thesingle side band (SSB) noise figure of the BLIXER is 4 dBhigher than the NF of the balun-LNA. This can be expectedbased on the conversion-loss of the mixing action (2 or

4 dB). In contrast to the BLIXER, the I/Q-BLIXER has I- andQ-outputs which can be combined to reject the noise of theimage band. Therefore, the relevant measure of NF for theI/Q-BLIXER is the double side band (DSB) NF. Fig. 9 showsthat compared to the standalone balun-LNA, the NF of theI/Q-BLIXER increases with only 1–2 dB.

D. Effects of Non-Ideal LO Signals

For higher LO frequencies, it becomes increasingly chal-lenging to generate a 25% duty-cycle LO signal with sufficiently


Fig. 9. Comparison of the noise figure of the balun-LNA, basic BLIXER andI/Q- BLIXER. NF is used for the I/Q-BLIXER as it has quadrature outputs.

Fig. 10. Effect of LO pulse with finite rise and fall time in the I/Q-BLIXER onthe NF versus the LO frequency for different IF frequencies.

low rise and fall times. Simulations on the I/Q-BLIXER are per-formed to investigate the effects of finite rise and fall times. Anideal voltage source generating a 25% duty-cycle LO signalwith 10% rise and fall time is supplied to a cascade of twoinverters, for each of the four LO phases. The inverters usedfor this simulation are equal to the inverters used in the finalstage of the LO driver in the complete I/Q-BLIXER realization.The size of second inverter is twice the size of the first inverter,and is designed to drive the LO switches. The inverters limitthe rise and fall time to about 25–30 ps, which causes narrowerpulses and lowers pulse-amplitude for higher LO frequencies.

Fig. 10 shows that for higher LO frequencies, mainly the NFat low IF frequencies (2 MHz) is affected. The increase in NF atlow IF frequencies is due to an increased sensitivity to 1/f-noiseof the LO switches and the LO driver (inverter) transistors. Thereduction of conversion gain compared to the case with idealLO drive is smaller than 1 dB (not shown as this is only a minoreffect).

V. IC IMPLEMENTATION AND MEASUREMENTS

Fig. 11 shows an overview of the I/Q-BLIXER test chip.The RF input is single-ended while the IF I- and Q-outputsare differential. The single-ended external oscillator signal isconverted into a differential signal on-chip and subsequentlydivided by 2 to generate in-phase (I) and quadrature (Q) LOsignals. The output of the divide-by-2 is amplified to rail-to-rail

Fig. 11. Overview of the test chip. The LO is derived from an external clock viaa single-to-different converter and divide-by-2 to generate quadrature phases.

Fig. 12. Chip micrograph and PCB detail showing packaged sample.

swing to obtain a 50% duty-cycle LO signal. The required 25%duty-cycle is generated using an AND operation on the I- andQ-signals. The I/Q-BLIXER core is implemented as described inSections IV-A and Sections IV-B. The differential IF outputs ofthe I/Q-BLIXER are buffered to 50 for measurement purposesusing four source-followers.

The circuit was fabricated in a baseline 65 nm LP CMOStechnology and a standard 1.2 V supply was used. The die photoand a detail of the PCB are shown in Fig. 12. The I/Q-BLIXER

core measures less than 0.01 mm . The measurements were per-formed on packaged, PCB-mounted samples.

The measured voltage conversion gain is 19 dB with and theIF bandwidth is 400 MHz, as shown in Fig. 13. The DSB NFof the I/Q-BLIXER at a 3 GHz LO frequency is around 4.5 dBand flat over the IF bandwidth. The wideband RF performanceis shown in Fig. 14. The gain remains flat within 1dB up to7 GHz. From 1 to 6 GHz, the NF is below 5 dB, using a fixed IFof 50 MHz. Note that this NF includes the PCB losses. Above7 GHz, the circuit generating the 25% duty-cycle LO signalsfails and the gain and NF could not be determined. The isbelow 10 dB up to 7 GHz.

The wideband linearity was measured using a two tone test.To assess IIP2 and IIP3 without filtering effects, the input tonesand the intermodulation products should fall within the flat partof the conversion gain versus frequency curve (Fig. 14). In awideband system a high spacing between the two test tones can


Fig. 13. Conversion gain �� and NF for � � 3 GHz.

Fig. 14. Conversion Gain �� , NF and � versus RF input-frequency�� 50 MHz�.

be used. Two tones at 5.2 GHz and 5.7 GHz, which representstwo IEEE 802.11a interferers, gives a 3rd order intermodula-tion product at 4.7 GHz . Using an LO frequency of 4.6 GHzthe measured IIP3 3 dBm. The IIP2 equals 20 dBm, using2.4 GHz (802.11 b/g) and 5.7 GHz (802.11 a) input tones and anLO of 3.2 GHz. The intermodulation for tones that leak throughthe mixer was determined using a 5.7 GHz and a 5.8 GHz signal(two 802.11a interferers). The intermodulation product at 100MHz showed an IIP2 40 dBm, regardless of the LO fre-quency. The LO leakage to the RF input is below 60 dBm forLO frequencies up to 4 GHz and below 5 dBm up to 7 GHz.

Fig. 15 shows a breakdown of the power consumption of thedifferent parts of the implemented circuit. The I/Q-BLIXER coreconsumes 16 mW and the biasing and IF buffering combinedconsumes 13 mW. Note that the IF buffers are added for mea-surements purposes and can often be omitted. At an LO fre-quency of 500 MHz, the 25% duty-cycle generation and LObuffering consume only 4 mW. At an LO frequency of 7 GHzthis part consumes 28 mW, which is almost half of the totalpower consumption. The LO buffering is based on inverters,which explains the increase in (dynamic) power consumptionat higher LO frequencies.

In Table I the measured performance is summarized and com-pared to other state-of-the-art wideband down-converters. TheI/Q-BLIXER achieves the widest signal bandwidth. Note that we

Fig. 15. I/Q-BLIXER power consumption breakdown for 500 MHz and 7 GHz.

specify the 1 dB bandwidth, where others often specify the3 dB bandwidth. The obtained linearity is the highest among

the reference designs. The main reason for the high linearity isthat the (RF) linearity is determined by only one transistor (com-bination), the CS inverter.

The noise figure is comparable to the other designs; further-more, the NF is almost flat across the entire band. Note that thisNF includes the PCB losses and that no external balun is needed.

Due to the absence of on-chip inductors, the area is verysmall. The combined area of the I/QBLIXER core and the I/Q-LObuffers is more than 4.5 times smaller than the smallest refer-ence design.

For low LO frequencies, the power consumption of the LObuffering is much lower than the other designs, and for high LOfrequencies, it is in the same order. The design of [20] has alower core (LNA plus mixer) power consumption. However, incontrast to our design, this design has no quadrature outputs.Compared to the designs with quadrature outputs [1]–[3], thepower consumption of our design is about 2 times lower.

VI. CONCLUSION

This paper proposes the BLIXER topology, which stacks acurrent-commutating mixer on top of a noise-canceling balun-LNA. The proposed topology has several attractive properties. Itachieves a high and flat gain over a wide bandwidth without in-ductors for bandwidth extension. This is because the BLIXER di-rectly converts the currents of the balun-LNA core to IF via cur-rent-commutating mixers, of which the (real part of) the inputimpedance is low. Creating voltage gain is shifted from RF tobaseband where capacitive loading is not a problem. By usingan I/Q mixer with 25% duty-cycle LO waveform, the outputIF currents have also have a reduced duty-cycle, resulting insmaller DC-voltage drops after IF filtering. This allows for a2 times increase of the impedance level of the IF load, ren-dering 2 times more voltage gain for the same supply head-room. The I/Q-BLIXER theoretically has only 1 dB less gainthan a balun-LNA biased at the same current. Also, its doublesided noise figure is only 1–2 dB higher than for the balun-LNAalone. The I/Q-BLIXER topology implements balun, LNA, andI/Q down-conversion functionality, all in one circuit core. A65 nm implementation achieves 18 dB conversion gain, a flatNF 5.5 dB from 500 MHz to 7 GHz, IIP2 20 dBmand IIP3 3 dBm. The core circuit consumes 16 mW which


TABLE ICOMPARISON OF STATE-OF-THE-ART WIDEBAND DOWN-CONVERTERS

is about 2 times lower than comparable wideband down-con-verters with I/Q-outputs. The area of the I/Q-BLIXER core occu-pies less than 0.01 mm in 65 nm CMOS, which makes it thesmallest wideband down-converter design published.

REFERENCES

[1] S. Lee, J. Bergervoet, K. S. Harish, D. Leenaerts, R. Roovers, R. vande Beek, and G. van der Weide, “A broadband receive chain in 65 nmCMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 418–612.

[2] J. Craninckx, M. Liu, D. Hauspie, V. Giannini, T. Kim, J. Lee, M.Libois, D. Debaillie, C. Soens, M. lngels, A. Baschirotto, J. VanDriessche, L. P. Van der Perre, and P. Vanbekbergen, “A fully recon-figurable software-defined radio transceiver in 0.13 �m CMOS,” inIEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 346–607.

[3] R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M.Mikhemar, W. Tang, and A. A. Abidi, “An 800- MHz-6-GHz soft-ware-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-StateCircuits, vol. 41, pp. 2860–2876, Dec. 2006.

[4] S. C. Blaakmeer, E. A. M. Klumperink, B. Nauta, and D. M. W.Leenaerts, “An inductorless wideband balun-LNA in 65 nm CMOSwith balanced output,” in Proc. 33rd Eur. Solid-State Circuits Conf.(ESSCIRC), Sep. 2007, pp. 364–367.

[5] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B.Nauta, “Wideband balun-LNA with simultaneous output balancing,noise-canceling and distortion-canceling,” IEEE J. Solid-State Cir-cuits, vol. 43, pp. 1341–1350, Jun. 2008.

[6] S. Chehrazi, A. Mirzaei, R. Bagheri, and A. A. Abidi, “A 6.5 GHz wide-band CMOS low noise amplifier for multi-band use,” in Proc. IEEECustom Integrated Circuits Conf. (CICC’05), Sep. 2005, pp. 801–804.

[7] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B.Nauta, “A wideband balun LNA I/Q-mixer combination in 65 nmCMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 326–327.

[8] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Noise cancellingin wideband CMOS LNAs,” in IEEE ISSCC Dig. Tech. Papers, Feb.2002, pp. 406–407.

[9] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wide-band CMOSlow-noise amplifier exploiting thermal noise canceling,” IEEE J. Solid-State Circuits, vol. 39, pp. 275–282, Feb. 2004.

[10] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, Wideband LowNoise Amplifiers Exploiting Thermal Noise Cancellation. : Kluwer/Springer, 2005.

[11] J. Jussila and P. Sivonen, “A 1.2-V highly linear balanced noise-can-celling LNA in 0.13-�m CMOS,” IEEE J. Solid-State Circuits, vol. 43,pp. 579–587, Mar. 2008.

[12] C. F. Liao and S. I. Liu, “A broadband noise-canceling CMOS LNAfor 3.1–10.6-GHz UWB receivers,” IEEE J. Solid-State Circuits, vol.42, pp. 329–339, Feb. 2007.

[13] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B.Nauta, “A wideband noise-canceling CMOS LNA exploiting a trans-former,” in Digest of Papers—IEEE Radio Frequency Integrated Cir-cuits Symposium, 2006, pp. 137–140.

[14] V. J. Arkesteijn, “Analog Front-Ends for Software-Defined Radio Re-ceivers,” Ph.D., University of Twente, Enschede, 2007.

[15] V. J. Arkesteijn, E. A. M. Klumperink, and B. Nauta, “A widebandhigh-linearity RF receiver front-end in CMOS,” in Proc. 30th Eur.Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 71–74.

[16] H. Sjoland, A. Karimi-Sanjaani, and A. A. Abidi, “A merged CMOSLNA and mixer for a WCDMA receiver,” IEEE J. Solid-State Circuits,vol. 38, pp. 1045–1050, Jun. 2003.

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[18] E. A. M. Klumperink, R. Shresta, E. Mensink, V. J. Arkesteijn, andB. Nauta, “Cognitive radios for dynamic spectrum access—polyphasemultipath radio circuits for dynamic spectrum access,” IEEE Commu-nications Magazine, vol. 45, pp. 104–112, May 2007.

[19] B. Gilbert, “The MICROMIXER: A highly linear variant of the gilbertmixer using a bisymmetric class-AB input stage,” IEEE J. Solid-StateCircuits, vol. 32, pp. 1412–1423, Sep. 1997.

[20] A. Amer, E. Hegazi, and H. F. Ragaie, “A 90-nm wideband mergedCMOS LNA and mixer exploiting noise cancellation,” IEEE Journalof Solid-State Circuits, vol. 42, pp. 323–328, Feb. 2007.

[21] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: PrenticeHall, 1988.


Stephan C. Blaakmeer (S’00–M’08) was born inStiens, The Netherlands, in 1976. He received theM.Sc. degree in electrical engineering from theUniversity of Twente, Enschede, The Netherlands,on the subject of RF CMOS ring oscillators, in2001. He joined Ericsson Eurolab, Emmen, TheNetherlands, in 2001, where he worked on CMOSradios for Bluetooth. In 2003, he returned to the ICDesign group of the University of Twente to worktoward the Ph.D. degree on the subject of widebandreceiver techniques in CMOS.

He recently joined Axiom IC, Enschede, The Netherlands, where he isworking on RF transceivers. His interests are RF and analog circuits in generaland more specific in circuits for wireless transceivers.

Eric A. M. Klumperink (M’98–SM’06) was bornon April 4, 1960, in Lichtenvoorde, The Nether-lands. He received the B.Sc. degree from HTS,Enschede, The Netherlands, in 1982. After a shortperiod in industry, he joined the Faculty of ElectricalEngineering of the University of Twente (UT) inEnschede in 1984, participating in analog CMOScircuit design and research. This resulted in severalpublications and a Ph.D. thesis, in 1997 (“Transcon-ductance based CMOS circuits”).

After receiveing his Ph.D., he started working onRF CMOS circuits. He is currently an Associate Professor at the IC-Design Lab-oratory which participates in the CTIT Research Institute (UT). He holds severalpatents and has authored or coauthored more than 80 journal and conference pa-pers.

In 2006 and 2007, Dr. Klumperink served as an Associate Editor for IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS II, and since 2008 for IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS I. He was a corecipient of theISSCC 2002 Van Vessem Outstanding Paper Award.

Domine M. W. Leenaerts (M’94–SM’96–F’2005)received the Ph.D. degree in electrical engineeringfrom Eindhoven University of Technology, Eind-hoven, The Netherlands, in 1992.

From 1992 to 1999, he was with EindhovenUniversity of Technology as an Associate Professorwith the Micro-electronic Circuit Design group. In1995, he was a Visiting Scholar with the Departmentof Electrical Engineering and Computer Science,University of California, Berkeley. In 1997, he wasan Invited Professor with the Technical University of

Lausanne (EPFL), Lausanne, Switzerland. From 1999 until 2006, he was withPhilips Research Laboratories. Since 2007, he has been with NXP Semicon-ductors, Research, Eindhoven, The Netherlands, as a Senior Principal Scientist,involved in (CMOS) RF integrated transceiver design. He has published over150 papers in scientific and technical journals and conference proceedings andholds over 20 U.S. patents. He has coauthored several books, including CircuitDesign for RF Transceivers (Kluwer, 2001).

Dr. Leenaerts served as IEEE Distinguished Lecturer in 2001–2003 andserved as an associate editor of the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS PART I (2002–2004). Since 2005, he has been the IEEE Circuitsand Systems Society Member representative in the IEEE Solid-State CircuitsSociety Administrative Committee. Since 2007, he has served as an AssociateEditor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is a member of thetechnical program committees of the ISSCC, ESSCIRC, and RFIC Conference.

Bram Nauta (M’91–SM’03–F’08) was born inHengelo, The Netherlands, in 1964. In 1987, hereceived the M.Sc. degree (cum laude) in electricalengineering from the University of Twente, En-schede, The Netherlands. In 1991, he received thePh.D. degree from the same university on the subjectof analog CMOS filters for very high frequencies.

In 1991, he joined the Mixed-Signal Circuitsand Systems Department of Philips Research,Eindhoven, The Netherlands, where he worked onhigh-speed A/D converters and analog key modules.

In 1998, he returned to the University of Twente as a full Professor headingthe IC Design group, which is part of the CTIT Research Institute. His currentresearch interest is high-speed analog CMOS circuits. He is also a part-timeconsultant in industry. In 2001, he cofounded Chip Design Works. His Ph.D.thesis was published as a book: Analog CMOS Filters for Very High Frequen-cies (Springer, 1993) and he received the Shell Study Tour Award for his Ph.D.work.

From 1997 until 1999, he served as an associate editor of IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS PART II–ANALOG AND DIGITAL

SIGNAL PROCESSINg. After this, he served as a Guest Editor, an AssociateEditor (2001–2006), and from 2007 as Editor-in-Chief for the IEEE JOURNAL

OF SOLID-STATE CIRCUITS. He is also a member of the technical programcommittees of the IEEE International Solid State Circuits Conference (ISSCC),the European Solid State Circuit Conference (ESSCIRC), and the Symposiumon VLSI Circuits. He was a corecipient of the ISSCC 2002 Van VessemOutstanding Paper Award. He is a distinguished lecturer of the IEEE andelected member of IEEE SSCS AdCom.

The Blixer, A Wideband Balun-LNA-IQ-Mixer Topology

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