Y. R. Chien, H. W. Tsao and W. L. Mao: The Application of New Far-End Crosstalk Cancellation in 10GBASE-T 375

Short paper

THE APPLICATION OF NEW FAR-END CROSSTALK

CANCELLATION IN 10GBASE-T*

Ying-Ren Chien and Hen-Wai Tsao

Graduate Institute of Communication Engineering and Department of Electrical Engineering, National Taiwan University

Wei-Lung Mao

Department of Electronic Engineering, National Formosa University

ABSTRACT

In 10GBASE-T system, far-end crosstalk (FEXT) interference results in a consider-able loss in decision point signal-to-noise ratio (DP-SNR). Thus IEEE 802.3an work group suggests that FEXT interference must be suppressed by at least 20 dB to achieve the DP-SNR requirement. This paper proposes a novel transmitter-side-based multi-ple-input-single-output (MISO) FEXT cancellation architecture. The coefficients of the MISO FEXT canceller and equalizer are obtained by using the least-mean-square adap-tive method jointly. Simulation results show that the proposed method is able to suppress the FEXT interferences by 20.99 dB and the resulting DP-SNR is 7.36 dB higher than that of the traditional equalization method.

Key words: Far-end Crosstalk (FEXT), 10GBASE-T, Interference Cancellation.

Manuscript received Feb. 1, 2007; revised June 28, 2007, and accepted Sep. 29, 2007. This work was supported by the NSC under Grant NSC94-2220- E-002-021.

I. INTRODUCTION

To meet the demands of economical high-speed data transmission over short transmission distances, the IEEE 802.3an work group specifies requirements for the next generation 10Gbps Ethernet network over copper line which is named the 10GBASE-T. The full duplex transmission over 4-pair copper suffers from many im-pairments, such as inter-symbol-interference (ISI), inser-tion loss (IL), echo, near-end crosstalk (NEXT), far-end crosstalk (FEXT), and alien crosstalk. These impair-ments will seriously degrade the achievable data rate [1] and need to be alleviated.

The IEEE 802.3an work group has proposed a ten-tative architecture for 10GBASE-T system [1]-[4]. A summary of tentative specifications for 10GBASE-T system is listed in TABLE 1. Under these specifications, the decision point signal to noise ratio (DP-SNR) at the receiver needs to be at least 23.4 dB to achieve the ex-tremely low bit error rate (BER) of 10-12 . In [5], the au-thors used a tentative decision as the input of FEXT canceller and adapt its equalizer coefficients for sin-

gle-carrier-based twisted-pair transmission systems. However, the correctness of tentative decisions is not good enough in the 10GBASE-T system. Thus, the ten-tative-decision-based FEXT cancellation method does not fit for the 10GBASE-T system. In [6]-[7], the au-thors proposed a multi-dimensional equalizer to equalize both ISI and FEXT interferences. However, because 10GBASE-T system utilizes the transmitter equalization scheme, i.e. Tomlinson-Harashima Precoding (TH pre-coding) [8], those existing receiver-side-based FEXT cancellation techniques do not work. To overcome these

Table 1 The Tentative Specification of 10GBASE-T System.

Items Tentative Specification

Baud Rate 800MHz

Modulation Code Baseband 128-DSQ (PAM-16)

Forwarding Error Control

LDPC(2048,1723) systematic

Framing 64B/65B

Transmitter Equalization

Tomlinson-Harashima Precoding

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376 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING, VOL.14, NO.5 (2007)

problems, a new FEXT cancellation approach for a sys-tem with TH precoding scheme is presented in this pa-per.

The organization of this paper is as follows. In Sec-tion II, the channel model and system architecture are introduced. In Section III, we formulate the FEXT can-cellation problem and also devise a training architecture to fulfill the design in Section III. In Section IV, the simulation results demonstrate the proposed method can cancel the FEXT interference more effectively compared to a conventional equalizer, which only compensates the ISI and treats FEXT just as noise. Finally, in Section V, we summarize the entire paper.

II. SYSTEM MODELS

Based on the system architecture proposed by the IEEE 802.3an work group, a transmitter-side-based FEXT cancellation architecture is proposed to generate the pre-compensation signal at the transmitter side and to cancel the FEXT interference at the receiver side. A simplified system model is shown in Fig. 1. There are two different operation modes, one is training mode and the other is data mode [1]. When the system starts up, the switches will alternate to the lower branch, and the system will operate in the training mode.

During phase one of the training mode, the slave side is silent and receives the far-end training signal from the master side, which is corrupted by both additive white Gaussian noise (AWGN) and the FEXT interfer-ence. Then the slave uses the pre-defined training se-quences to train the coefficients of the feedforward equalizer (FFE), feedback equalizer (FBE) and multiple- input-single-output (MISO) FEXT canceller until the mean square error convergences to an acceptable value, e.g. -30 dB. When phase one is finished, the system en-ters into phase two of the training mode. The slave side starts to send local training sequences to the master side. In phase two, the slave side will train the ECHO cancel-ler and NEXT canceller while the master side will train its FFE, FBE and MISO FEXT at the same time.

After the training period is finished, the slave side will relay the well-trained coefficients of FBE, i.e. B(1)[z] , to the master side as the feedback coefficients of the TH precoder, and the coefficients of the MISO filters to the master side as the MISO FEXT canceller at the transmitter side as well. Then the switches will change to the upper branch, and the system will enter into the data mode.

Because the disturbing source of NEXT and echo are known to the victims, those two kinds of interference signals can be cancelled more easily than the FEXT in-terference. For simplicity, this paper focuses on the

Fig. 1 The proposed system architecture for the 10GBASE-T system.

Y. R. Chien, H. W. Tsao and W. L. Mao: The Application of New Far-End Crosstalk Cancellation in 10GBASE-T 377

FEXT cancellation problem only. The detailed equiva-lent transmitter, channel and receiver block diagrams are described as follows.

A. The Proposed Transmitted Signal Models

Fig. 2 shows the equivalent transmitter block dia-gram in data mode. There is an MISO FEXT canceller at the transmitter side, which comprises three SISO FEXT cancellers, i.e. l(i, j)[k], with input of v(i)[k] for i≠ j , and we denote the FEXT pre-compensation signal for the ith pair as s(i)[k]. First, the information bits are fed into a 128 double square (128-DSQ) modulator. We denote the output data symbol of the 128-DSQ modulator as x( j)[k], which comprises two 16-level pulse-amplitude-modula-tion (PAM) symbols. One of the most important proper-ties of the 128-DSQ modulated symbol is that the two PAM symbols are not independent, such that the mini-mal distance among 128-DSQ modulated symbols is

22 and hence improves the immunity against noise over that of a 16-PAM2 modulation scheme ( two inde-pendent 16-PAM constellation ) [3].

The transmitted signal u(i)[k] is given by:

( ) ( ) ( ) ( ) ( ) ( , )[ ] [ ] [ ] [ ] [ ] [ ]i i i i j i j

i j

u k v k s k v k v k l k≠

= − = − ∗∑ (1)

with ( ) ( ) ( ) ( ) ( )[ ] [ ] [ ] [ ] [ ]i i i i iv k x k d k v k b k= + − ∗ where ( )[ ]iu k and ( )[ ]iv k are the transmitted channel symbols and the TH-precoded symbol of wire pair i, respectively. The symbol * denotes the convolution.

As shown in Fig. 3, the effect of the modulo device is equivalent to choosing the unique integer sequence

( )[ ] 2id k M∈ Ζ , so that the precoded symbol ( )[ ]iv k falls into the interval [ , )M M− with M=16 [8]. The coefficients of the TH precoder are denoted as ( )[ ]ib k .

B. The Multiple-Input-Multiple-Output (MIMO) Channel Model

In Fig. 4, the equivalent channel can be modeled as an equivalent N × N channel matrix H(z) with N=4. The matrix H ( z ) i s excited by far-end signal vector

(1) (2) (3) (4)[ ]T

k u u u u⎡ ⎤= ⎣ ⎦u . The diagonal elements of H(z) represent the IL channel and its off-diagonal elements represent the FEXT interference crosstalk channel. To simplify the notations, the effect of root-raised cosine pulse shaping filter at the transmitter side and the effect of receiver matched filter, which is matched to the pulse shaping filter, will be merged into the equivalent channel. The equivalent noise ( )[ ]in k% is the noise at the output of the receiver-matched filter with additive white Gaus-sian noise (AWGN) as its input.

C. The Received Signal Models

The received signal model in data mode is shown in Fig. 1. We denote the received data at ith pair at time k as y(i)[k], which comprises the interested received signal

Fig. 2 The equivalent transmitter block diagram.

Fig. 3 The linearized model of Tomlinson-Harashima pre-coder in Fig. 2.

Fig. 4 The equivalent MIMO channel model for 10GBASE-T system.

r(i , j)[k], FEXT crosstalk ( , )[ ]i j

i j

r k≠∑ , and equivalent

noise ( )[ ]in k% . Therefore, ( )[ ]iy k can be expressed as follows

4 1( ) ( , ) ( ) ( )

1 0

[ ] [ ] [ ] [ ]v

i i j j i

j n

y k h k n u n n k−

= =

= − +∑∑ % (2)

where ν is the length of the channel memory. Then ( )[ ]iy k will pass through the FFE W(i)(z).

The output of FFE of the ith pair, i.e. ( )[ ]iy k% , will apply to a modulo device and then feed into a slicer. Ideally, if the IL channel is equalized perfectly and the FEXT interference is cancelled completely, then

( ) ( ) ( ) ( )[ ] [ ] [ ] [ ]i i i iy k x k d k n k= + +% % (3)

After the modulo operation, it becomes

{ }( ) ( ) ( ) ( )[ ] [ ] [ ] [ ]i i i ix k Mod y k x k n k= = +% % % , (4)

378 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING, VOL.14, NO.5 (2007)

where Mod{‧} denotes the modulo operation. Then the DSQ slicer will make decisions ( )ˆ [ ]ix k and ( )ˆ [ 1]ix k − based on ( )[ ]ix k% and ( )[ 1]ix k −% , respectively.

III. FEXT CANCELLATION PROBLEM FORMULATION

For simplicity, it is assumed that pair one is the vic-tim channel and the other three channels are the disturb-ing channels. The interference that coupled to pair one is given by

4 4(1, ) ( ) (1, )

2 2

[ ] [ ]* [ ]j j j

j j

r k c k h k= =

=∑ ∑ (5)

The object of FEXT cancellation is to suppress FEXT interference by at least 20 dB to meet the DP-SNR requirements [1].

A. The proposed transmitter-side-based FEXT canceller design

For the 1st pair, although it is hard, and even impos-sible, to estimate the random integer d(1)[k] at the re-ceiver side, however, d(1)[k] is known information at the transmitter side. The object is to devise an MISO FEXT filter to generate the FEXT pre-compensation signal s(1)[k] at the transmitter side such that the coupled FEXT interference could be canceled properly based on this fact. It is expected that the pre-compensation signal will cancel the coupled FEXT interference from the other three pairs at the output of FFE.

As shown in Fig. 2 and Fig. 4, we denote the output of FFE (1)[ ]W z excited by (1)[ ]s k as (1)[ ]q k% , whose Z-domain representation can be expressed as

4(1) ( ) ( ) ( ) ( , )

2

[ ] ( ( ) ( )) / ( ) ( )j j j i j

j

Q z X z D z B z L z H=

⎡ ⎤= + ⋅⎢ ⎥⎣ ⎦∑%

(1,1) (1)) ( ) ( )H z W z (6)

If we ignore s(1)[k], the interference signal coupled into the output of FFE of pair 1 from the other three pairs can be expressed as:

4 4(1) ( ) (1, ) (1) ( ) (1, ) (1)

2 2

( ) ( ) ( ) ( ) ( ) ( ) ( )j j j j

j j

Q z U z H z W z V z H z W z= =

= ≈ =∑ ∑

4( ) ( ) ( ) (1, ) (1)

2

( ) ( ( ) ( )) / ( ) ( ) ( )j j j j

j

z X z D z B z H z W z=

⎡ ⎤= +⎣ ⎦∑ (7)

Let (6) be equal to (7), then we have

(1, )(1, )

(1,1)

( )( ) , 2,3, 4

( )

jj H z

L z jH z

= = (8)

The approximation in (7) is due to (1)[ ]v k being generally much greater than (1)[ ]s k . In fact, it is ob-served that the pre-compensation filter acts just like an equal level FEXT (EL-FEXT) emulator. The penalty of the approximation is slight, however, the approximation reduces hardware cost and makes the design easier.

The average FEXT suppression ratio is used to evaluate the performance of a FEXT canceller, which is defined as

( )( )

2( )4

10 2( ) ( )1

110 log

4

j

j jj

E q

E q qξ

=

⎛ ⎞⎡ ⎤⎜ ⎟⎢ ⎥⎣ ⎦= ⎜ ⎟

⎡ ⎤−⎜ ⎟⎢ ⎥⎣ ⎦⎝ ⎠

∑%

(9)

where E(．) denotes the expectation. In this paper, we use lower case letters to represent

time domain variables, and use the corresponding upper case letter to represent its Z-domain variable without explicit explanations.

B. Joint equalizer and MISO FEXT canceller training architecture

Fig. 5 shows the block diagram of the proposed joint equalizer and MISO FEXT canceller architecture. The difference between the proposed architecture and traditional “equalizer and interference canceller design” is that the output of the MISO FEXT canceller is not only linked to the FFE but also feeds into the input of feedback equalizer (FBE) during the training period. Hence, we have the following relation at the end of training period:

( , ) ( ) ( ) 1i i i iH W B ≈ , (10)

( , ) ( ) ( , ) ( ) , for i j i i j iL B H W i j≈ ≠ (11)

From (10) and (11), we have

( , ) ( ) ( , )( , )

( ) ( , ), for

i j i i ji j

i i i

H W HL i j

B H≈ = ≠ (12)

Fig. 5 The Joint equalizer and MISO FEXT canceller training architecture for the wire pair one.

Y. R. Chien, H. W. Tsao and W. L. Mao: The Application of New Far-End Crosstalk Cancellation in 10GBASE-T 379

This is why the filter coefficients as designed in (8) can be obtained by the proposed joint training architec-ture.

The training algorithm is based on LMS algorithm and ( )[ ]ix n is the training sequence of pair i. For pair one, (1)[ ]x n is used to train the FFE and FBE, while

(2)[ ]x n , (3)[ ]x n and (4)[ ]x n are used to train the MISO FEXT canceller.

During the training period, the coefficients of FFE, FBE and MISO FEXT canceller are updated as the fol-lowing recursive equations, respectively:

( ) ( ) ( ) ( )1[ 1] [ ] [ ] [ ], 1, 2,3, 4i i i i

FFEn n n e n iμ+ = + =w w c (13)

( ) ( ) ( ) ( )2[ 1] [ ] [ ] [ ], 1, 2,3, 4i i i i

FBEn n n e n iμ+ = − =b b c (14)

( , ) ( , ) ( , ) ( )3[ 1] [ ] [ ] [ ],i j i j i j i

FXEn n n e n iμ+ = −l l c

{ }], 1, 2,3, 4i j≠ ∈ (15)

where ( )[ ]i nw , ( )[ ]i nb and ( , )[ ]i j nl are filter coeffi-cients, FFEμ , FBEμ and FXEμ are the step-size scalars for coefficient updating. The size of filter contents

( )1

ic , ( )2 [ ]i nc and ( , )

3 [ ]i j nc for FFE, FBE and MISO FEXT are fN 1× , bN 1× and xN 1× , respectively. The scalar ( )[ ]ie n is the error signal between the desired signal and the slicer input signal (1)[ ]x k% . The size of column vectors ( )[ ]i nw , ( )[ ]i nb and ( , )[ ]i j nl are de-noted as fN 1× , bN 1× and xN 1× , respectively.

At the end of the training mode, the well-trained coefficients of FBE, (1)[ ]nb , and MISO filter, { (1,2)[ ]nl ,

(1,3)[ ]nl and (1,4)[ ]nl }, would be relayed to the trans-mitter side as the coefficients of the TH precoder and MISO FEXT canceller of pair one, respectively, and

(1)[ ]nw would be the coefficients of FFE at the receiver. The same methodology can be applied on the other

three wire pairs to obtain the corresponding coefficients of the TH precoder, MISO FEXT canceller and FFE simultaneously

C. The proposed transmitter-side-based FEXT cancellation mechanism in data mode

As shown in Fig. 1, the switch will change to the upper branch in data mode. The received signal for wire pair i can be expressed as

( ) ( )( )

( ) ( ) ( ) ( , ) ( ) ( ) ( , ) ( )

( ) ( ) ( , ) ( ) ( , ) ( )

( ) ( , ) ( ) ( , ) ( , ) ( ) ( , ) ( )

( ) ( , ) ( ) ( , ) ( ) ( , ) ( )

i i i i i j j i j i

i j

i i i i j i j i

i j

i i i j i j i i j i j i

i j i j

i i i j i j j i j i

i j i j

Y V S H V S H N

V S H V H N

V H V L H V H N

V H V H V H N

≠

≠

≠ ≠

≠ ≠

= − + − +

≈ − + +

= − + +

= − + +

∑

∑

∑ ∑

∑ ∑

%

%

%

%

( ) ( , ) ( )i i i iV H N= + % (16)

where ( , )

( , )( , )

( )( )

( )

i ji j

i i

H zL z

H z= , and the precoded data sym-

bol and the FEXT pre-compensation signal for wire pair j is ( ) ( )jV z and ( ) ( )jS z , respectively. Because the amount of ( ) ( , )j i jS H for i j≠ is relatively small and can be ignored in (16). Consequently, the FEXT crosstalk can be cancelled at the receiver side by adding the pre-compensation signal at the transmitter side.

Note that ( ) ( )jV z depends on the transmitted data ( ) ( )jX z and the corresponding TH precoder coeffi-

cients ( ) ( )jB z only, and the FEXT pre-compensation signal ( ) ( )jS z depends on ( ) ( )iV z for i j≠ . Hence, there is no interaction between ( ) ( )jV z and ( ) ( )jS z . Therefore, the transmitter-side-based MISO FEXT can-cellation architecture can be applied on the four wire pairs simultaneously.

IV. SIMULATION RESULTS

In this section, we adopt the channel model pro-vided by the IEEE 802.3an work group, and the IL and FEXT impulse responses are shown in Fig. 6. Compar-ing the proposed MISO FEXT canceller to a traditional receiver, which just treats FEXT as noise. The simula-tion parameters are listed in TABLE 2 and the resulting DP-SNR comparison are listed in TABLE 4.

As shown in TABLE 2, the AWGN SNR is set to 32 dB at the receiver input ( preceding the receiver matched filter ), which include alien crosstalk and ther-mal noise. In order to have a fair comparison, we set the total number of taps as the same for these two different architectures. The training sequence is an m-sequence with period 16384 [3], and the choice of FEXT taps is based on the time span of FEXT interference. Training sequence is used to get the FFE, FBE and MISO FEXT canceller coefficients. The training method is the least mean square (LMS) algorithm [9]. In the end of the training mode, all three architectures can achieve an op-timal value for SNR (about 30 dB).

Fig. 6 The impulse response of IL and FEXT channel of Class-E cable of length 55 meters.

380 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING, VOL.14, NO.5 (2007)

A. Simulation results of a traditional equalizer

As shown in TABLE 3, the achieved DP-SNR per-formance at the end of the training mode is almost the same between a traditional equalizer and the proposed MISO FEXT canceller. However, as shown in TABLE 4, the proposed architecture outperforms the traditional architecture in terms of DP-SNR in data mode.

The scatter diagram of slicer inputs for the tradi-tional receiver is shown in Fig. 8. If we adopt a tradi-tional equalizer, the average DP-SNR would be only 22.48 dB in data mode. Since it is degraded by DP-SNR 7.36 dB on average, a method is needed to suppress the FEXT interference.

As shown in TABLE 4, without a sophisticated FEXT canceller, even if the tap numbers are much larger than that of a MISO FEXT canceller, the DP-SNR can not meet the 23.4 dB requirement.

B. Simulation results of MISO FEXT canceller

The learning curve of the proposed training archi-tecture and the scatter diagram of the slicer input are shown in Fig. 9 and Fig. 10, respectively. The learning curve is obtained by averaging over 200 independent trials of the simulation with each trial running over 2×105 PAM symbols with amplitude +1 and -1. The re-sults show that the average mean square error is 30 dB, which is much higher than 23.4 dB.

As shown in Fig. 11, the FEXT interference and the estimated FEXT interference are similar. By the FEXT suppression ratio definition in (9) we could evaluate the performance of a FEXT canceller. The resulting average FEXT suppression ratio is 20.99 dB which meets the FEXT suppression ratio requirement.

In the proposed method, we may doubt if the pre-compensation signal will cause the transmitted power spectrum to violate the specification. As shown in Fig. 7, we can observe that the transmitted power spec-trum before and after adding the pre-compensation sig-nals are almost the same.

V. CONCLUSIONS

The DP-SNR in a 10GBASE-T system will be de-graded by 5 dB to 8 dB without FEXT cancellation. This paper proposes a practical joint equalizer and MISO FEXT canceller architecture to train the coefficients of a MISO FEXT canceller and equalizer in the start-up pe-riod. The proposed transmitter-side MISO FEXT can-celler can achieve a FEXT suppression ratio of 20.99 dB over 55 meters of Class-E cable which meets the FEXT suppression ratio requirement.

ACKNOWLEDGEMENT

The author would like to thank Mr. Jan-Hwa Lee who gave many suggestions in this work. This research was supported by the NSC project NSC94-2220- E-002-021.

Table 2 The simulation parameters.

Items Traditional equalizer

MISO FEXT canceller

FFE taps ( Nf ) 45 45

FBE taps (Nb ) 335 35

FEXT canceller taps (Nx ) NA 100

Total Taps 45+335 45+35+100*3

AWGN SNR 32 dB 32 dB

Table 3 The performance comparison in training mode.

Pair number Traditional equalizer

DP-SNR (dB) MISO FEXT canceller

DP-SNR (dB)

Pair 1 30.29 30.36

Pair 2 30.43 30.44

Pair 3 29.01 29.03

Pair 4 30.02 30.06

Average DP-SNR

29.94 29.97

Table 4 The performance comparison in data mode.

Pair number Traditional equalizer

DP-SNR (dB) Traditional equalizer symbol

error rate(SER) MISO FEXT canceller

DP-SNR (dB) MISO FEXT canceller symbol error rate(SER)

Pair 1 21.76 1.9×10-1 30.08 6.0×10-5

Pair 2 22.84 8.5×10-2 30.28 1.0×10-5

Pair 3 23.45 6.2×10-2 29.12 2.2×10-4

Pair 4 21.86 1.8×10-1 29.89 8.0×10-5

Average Performance

22.48 1.29×10-1 29.84 9.25×10-5

Y. R. Chien, H. W. Tsao and W. L. Mao: The Application of New Far-End Crosstalk Cancellation in 10GBASE-T 381

Fig. 7 The comparison of the transmitted power spectrum.

Fig. 8 The scatter diagram of slicer inputs of the traditional receiver architecture in data mode.

Fig. 9 The learning curve of the joint equalizer and MISO FEXT canceller training architecture.

Fig. 10 The scatter diagram of the slicer inputs of the pro-posed architecture in the data mode.

Fig. 11 The comparison between the real FEXT and the es-timated FEXT interference.

REFERENCES

[1] W. Jones, “10GBASE-T Tutorial Overview,” [Online]. Available: http://www.ieee802.org/3/ 10GBT/public/jan03/jones_2_0103.pdf

[2] S. Power, H. Takatori, X. Chen, K. Seki, J. Tellado, and K. Kota, “10GBASE-T PAM Scheme ：

Proposed Overall Architecture,” [Online]. Available: http://www.ieee802.org/3/an/public/jul04/powell_1_0704.pdf

[3] S. Powell, B. Shen, and G. Ungerboeck, “10GBASE-T Modulation & Coding, Set of Fixed Precoders, and Start-up,” [Online]. Available: http://grouper.ieee.org/groups/802/3/an/public/nov04/ungerboeck_1_1104.pdf

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[4] S. Powell and B Shen, “ Specification and Perofr-mance of Proposed LDPC (2048,1723) Code,” [Online]. Available: http://grouper.ieee.org/groups/ 802/3/an/public/jan05/powell_1_0105.pdf

[5] G. H. Im, K.-M. Kang, and C. J. Park, “FEXT can-cellation for twisted-pair transmission,” IEEE J. Sel. Areas Commun., volume 20, issue 5, pp.959-973, June 2002.

[6] Koyama, T.; Peng, J.; Cohen, P. ,“A multi-dimensional equalizer for Gigabit Ethernet,” in Proc. Int. Conf. on Communications, 2001, vol-ume 2, pp. 509-512, June 2001.

[7] Lange, C.; Ahrens, A., “Far-End crosstalk equaliza-tion in multi-pair symmetric copper cable transmis-sion,” in Proc. Int. Conf. on Advances in the Inter-net, Processing, Systems and Interdisciplinary Re-search, pp. 643-648, June 2005

[8] Robert F. H. Fischer, Precoding and Signal Shaping for Digital Transmission, Wiley-IEEE Press, 2002.

[9] S. Haykin, Adaptive Filter Theory, 4th ed. Pren-tice-Hall, 2001

Ying-Ren Chien was born in Tai-wan, Republic of China, in 1977. He received his B.S. degree in Electronic Engineering from National Yunlin University of Science and Technol-ogy (NYUST), Taiwan, R.O.C., in 1999, and a M.S. degree in Electrical Engineering from National Taiwan

University (NTU), Taiwan, R.O.C., in 2001. He is currently working towards a Ph.D. with the Graduate Institute of Communication Engineer-ing, NTU. His research interests include signal processing on communication systems, high-speed network transmissions, timing recovery and multiuser detections.

Hen-Wai Tsao received B.S., M.S., and Ph.D. in Electrical Engineering from National Taiwan University, Taipei, Taiwan, Republic of China, in 1975, 1978, and 1990, respectively. He joined the faculty of the Depart-ment of Electrical Engineering, Na-

tional Taiwan University in 1978 and became an Associate Professor in 1983. His main research interests include Communication Systems, Communication Electronics, Measurement and Instrumentation systems and Integrated Circuits. In the past few years, he has published several papers on optical CDMA transmission techniques, and presently, he is investigating the realization of highly linear multi-carrier RF transmitters and key circuit blocks in 10-Gigabit Ethernet systems. Also, he has studied precision timing circuit techniques applied to automatic test equipments (ATEs). He has been involved in the projects of designing and implementing high speed vari-able-length Ethernet packet switches and ASIC’s for Ethernet Passive Optical Networks (EPONs).

Wei-Lung Mao was born in Taiwan, R.O.C. in 1972. He received his B.S. degree in Electrical Engineering from National Taiwan University of Science and Technology in 1994, and M.S. both degree and Ph.D. in Electrical Engineering from National Taiwan

University in 1996 and 2004, respectively. He is now an assistant professor in the Department of Electronic Engineering, National Formosa Uni-versity. His research interests are satellite naviga-tion systems, adaptive signal processing, neural networks and communication electronics.