The ALICE TPC Team

ALICE TPC, Schleching 2003 1

The ALICE TPC Team

Project leader: Peter Braun-Munzinger, GSI DarmstadtDeputy project leader: Johanna Stachel, HeidelbergTechnical coordinator: Peter Glässel, Heidelberg

Bergen D. Röhrich Data acquisitionBratislava B. Sitar 1/2 IROC series productionCERN T. Meyer Field cageCERN L. Musa ElectronicsCopenhagen B.S. Nielsen Laser systemKrakow M. Kowalski SimulationsDarmstadt GSI H.R. Schmidt ROC engineering, prototyping,

series production, simulationsDarmstadt TU H. Oeschler Electronics testingFrankfurt R. Renfordt Electronics testing, installationHeidelberg KIP V. Lindenstruth Data acquisition, HLTHeidelberg PI J. Stachel Electronics, engineering,

IROC production, OROC productionLund H.A. Gustafsson Electronics


Outline

OverviewField CageReadout chambersLaser systemCooling systemGas systemReadout electronics PerformancesOutlook


The ALICE Detector at LHC


General Conditions at LHC for Heavy Ion Collisions

5.5 TeV CM-energy (NN) Pb + Pb (and probably lighter ions)

rapidity density worst case dN/dy = 8000

8 kHz inelastic collision rate rapidity interval 17 units 25 ns bunch spacing


Central event

Central event Pb-Pb

dN/dy = 8000only a 2 deg slice!


Summary of TPC Specs

|| < 0.9 (full length tracks)

845 < r < 2466 mm drift length 2 x 2.5 m, 100 kV, 88 s drift Ne/CO2 (90/10)

18 x 2 sectors with 2 ROC’s 557 568 channels, 512 10 bit time samples (5.7 MHz) event size 60 MB occupancy 40 to 15% @ dN/dy = 8000 position resolution 800 to 1250 m in r and z material budget 3.5 to 5% X0


TPC Field Cage Overview

Inner and outer Isolation vesselsAluminum End Plates housing ROC’sField defining system: strips supported by rods


Field Cage parts

5560

5000

Drift volume

Isolation volume

Isolation volume

End wheel


Inner Field Cage Production

Nomex®

Tedlar®

Fiber Pre-Pregs

Aluminum

Honeycomb Core

Cylinders are fabricated from segments glued

together (lashing).


Inner Field Cage Vessel: Assembly


Inner Field Cage Vessel: Guard Rings

Potential guard rings glued to inner and outer surface of Inner Field Cage Vessel

100 mm


Field Cage Assembly


Checking the End Wheel


Leak test of inner vessel


Flange of Outer Isolation Volume

Forged and machined rings from André Constructions Mécaniques - Grenoble


Field Cage: Central Electrode

Single mylar foil 3 sheets glued Carbon fiber frame proven technique (NA48)


Central Electrode: Prototype

25 µm aluminized Mylar on Al frame of 10 cm width, Ø approximately 3 m.


Service Support Wheel

Carries front end electronics and services


Service Support Wheel Model

3 sectors SSW1 sector end plateTrain all operations


Readout Chambers

18 sectors each side, 2 chambers/sector MWPC’s, 557568 cathode pads gas gain 2x104

gated pad sizes 4x7.5, 6x10, 6x15 mm2

pad occupancy 15 … 40% (dN/dy = 8000) 5.7 MHz 10 bit ADC sampling, 512 samples position resolution 800 … 1250 m (r, z)


Readout Chamber Wire Geometry

gate wirescathodes

anodespads


Pad Plane

optimized pad sizes

4 x 7.5 mm 6 x 10 mm 6 x 15 mm

segmented: IROC and OROC

total 557 568 pads


IROC Module Tests

1150 1200 1250 1300 13501000

10000

100000

Module 0319.02.02

Gai

n

Anode voltage (V)

HV 1260 … 1310 V @ gas gain 20,000


IROC Gain Homogeneity

(Drop at ends due to 55Fe source geometry)


Leak Test


Adjusting Wires vs Pads


IROC Detail Photos

FEE side with one cable Pad side before addinganode wire plane


IROC Connected to Front End Card

FEC in Cu sandwich

6 cables per FEC


OROC Wiring


IROC Laser Tracks

Pad response function = 2 mm as expected

Double track resolution:Separated maxima down to

two pad distanceTwo-gauss fit down to 1 pad


Laser System: Objectives

Electronics testing Sector alignment Drift velocity monitoring

Pressure, temperature Temperature gradients (stratification, i.e. up-down) ExB, space charge effects

Two possible approaches: Relative measurements, rely only on time stability of laser ray position Absolute measurements, requires knowledge of absolute position of laser ray. More ambitious


Laser Rod Principle

4 micro mirrors along z, alignment check with CCD at other TPC end


Laser Rod with Mirrors


Rays perpendicular to beam axis

Effective ray ~1mm2 x 4 z-planesStrategic

boundary crossingsAdditional signal from

central electrode (and pad plane)

Laser Ray Pattern


Laser Spatial Accuracy Goals

Assembly: angular accuracy ~1 deg.Relative angles of micro-mirror rays measured to 50 radFinal position of laser rays:

Stable to better than TPC resolution Known to better than TPC resolution via internal calibration with respect to central electrode and ROC (signal from pad plane)

Gives absolute measurement if E-field is near-perfect


Cooling: Temperature Stabilization and Homogeneity

Clearly a challenging item: we aim at T 0.1 KDouble defense line strategy:

Outer thermal screens toward TRD and ITSROC al bodies and pad planes: water-cooledDirect water cooling of FEE boards (Cu sheet sandwich)

Simulations and tests look promisingAn important concern: resistor rods (4 x 8 W)


TPC Cooling Scheme


Resistor Rod Cooling

gas cooled

water cooledHigh-resistivity water

10G10 Separator

Resistor

Cu-heat bridges

Ceramic pipe Resistor

insulation volume (gas)

gnd 100 kV


TPC Gas System

Mixer

Purifier

COremoval

2

Krypton

8bar

CO2

Ne/CO 2

Purging

~1 mbar

S

S

Gas Monitor TPC7 bar

S

S

Controller

In the cavern On the detectorIn the cavern On the detectorSurface Gas Building On the

Plug

pressureprotection

~2 mbar

to Exhaust

switch direct ventor re-circulation

~4 mbar

The buffer could be in SG Build.

~13 mbar

Pneumatic-switch

Gas purge

Buffer500 ltr.

3

4

5

6

98

12

1310

11

6

7

2 12

14

15

16

19

17

20

22

24

25

26

27

28

30

21

17

134

2

1

3

1

11

16

18

29

36

13

13

CirculatorModule

21

Ne/CO2 (90/10), high purity: < 5 ppm O2

expensive gas -> recirculation, low purge, ‘breathing’ system


anode wire

pad plane

drift region88s

L1: 5s 200 Hz

PASA ADC DigitalCircuit

RAM

8 CHIPS x

16 CH / CHIP

8 CHIPSx

16 CH / CHIP

CUSTOM IC(CMOS 0.35m) CUSTOM IC (CMOS 0.25m )

DETECTOR FEC (Front End Card) - 128 CHANNELS(CLOSE TO THE READOUT PLANE)

FEC (Front End Card) - 128 CHANNELS(CLOSE TO THE READOUT PLANE)

570132PADS

1 MIP = 4.8 fC

S/N = 30 : 1

DYNAMIC = 30 MIP

CSA SEMI-GAUSS. SHAPER

GAIN = 12 mV / fCFWHM = 190 ns

10 BIT

< 10 MHz

• BASELINE CORR.

• TAIL CANCELL.

• ZERO SUPPR.

MULTI-EVENT

MEMORY

L2: < 100 s 200 Hz

DDL(4096 CH / DDL)

Powerconsumption:

< 40 mW / channel

Powerconsumption:

< 40 mW / channel

gat

ing

gri

dFEE Architecture


36 sectorsFRONT VIEW

IROC

OROC

FEC

C1 : 18 FECs

C6 : 20 FECs

C4 : 20 FECs

C3 : 18 FECs

C2 : 25 FECs

C5 : 20 FECs

SIDE VIEW

128 channels Front End Card (FEC)

FEE POWER:

CHANNEL: 40 mW BOARD: 6.9 W

SECTOR: 832 W TOTAL: 30.2 kW

Capton Cable

140mm

190m

m

Mounting FEE


Loc

al

Con

trol

ler

DD

L - IN

TSlow

-Control

Interface

TTC-RX

BOARDCTRL

RCU

Slow – Control(1 Mbit – serial link)

Detector Link(100 MB / s)

(#216)

COUNTING ROOM

1

2

25

Each TPC Sector is served by 6 Readout Subsystems

Front-end bus(160 MB / sec)

LocalSlow- Control

Serial link

ON DETECTOR

Overall TPC: 4356 Front End Cards 216 Readout Control Units

FEC128 ch

DataCompr.

FEC128 ch

FEC128 ch

PASA – ADC – DIG.

Global Architecture


Differential PASA Circuit


Differential Output Signal


Noise performance of PASA


Differential PASA Test Results


010011010001011101010011010001011110010011010001011010

01001101000110111010110011000111001010011010 010011010001101110010 010011010001101110010 010011010001101110010

BaselineCorrection

I

+

–

TailCancellation

BaselineCorrection

II

ZeroSuppression

010011010001101110010010011010001101110010010011010001101110010

DataFormat

Memory+

Multi-EventBuffer

010011010001011101010011010001011110010011010001011010

01001101000110111010110011000111001010011010 010011010001101110010 010011010001101110010 010011010001101110010

BaselineCorrection

I

+

–

TailCancellation

BaselineCorrection

II

ZeroSuppression

010011010001101110010010011010001101110010010011010001101110010

DataFormat

Memory+

Multi-EventBuffer

SAMPLING CLOCK 20 MHz

READOUT CLOCK 40 MHz

10- bit20 MSPS

11- bit CA2arithmetic

18- bit CA2arithmetic

11- bitarithmetic

40-bitformat

40-bitformat

10-bitarithmetic

ALICE TPC READOUT CHIP – Principle


4cards16 ch

13

5 m

m

1998channels per chip: 1

ADC: 1 externalDigital Filter: no


ADC: 4 externalDigital Filter: no


ADC: 16 internalDigital Filter: yes

Integrated ADCs

ALTRO 16

External ADCs (fallback solution)

20

mm

4 PQFP 100

8 SSOP 28

24 mm

ALTRO – Summary of Prototyping


7.7 mm

8.3 mm

Data Memory1K x 40

Pedestal Memory1K x 10

ADCChannel 0

ADCChannel 7

ProcessingLogic

3.8 mm

12 mm

14.1 mm

TQFP 176

24mm

ALTRO Layout and Package

2.5 m (ST)


0 100 200 300 400 500 600 700-50

0

50

100

150

200filter inputthreshold

0 100 200 300 400 500 600 700-50

0

50

100

150

200Filtered data and fixed threshold

filter outputthreshold

AD

C c

ou

nts

AD

C c

ou

nts

Time samples (170 ns)

Time samples (170 ns)

ALTRO Digital Tail Cancellation Performance


ALTRO OUTPUTFILTER DISABLED

ALTRO OUTPUTFILTER ENABLED

ZERO SUPPRESSION THRESHOLD: 5 ADC COUNTS

Digital Tail Cancellation Performance

ALTROtest result


The layout of the chip has been

optimised to minimise the

influence of the digital circuitry

on the integrated ADCs.

Supply (VCC / GND) for the digital core

Supply (VCC / GND) for the ADC

The supply voltages for the

PASA are distributed on a

different plane

PCB Design near ALTRO chip


Kaptoncables to TPC

coolingpipe

readout busconnectors

control busconnector

power supply connector

voltageregulators

current monitoring& supervision

ALTROs

ShapingAmplifiers

GTLtransceivers(back side)

Final Front-end Card Prototype

4 chipsALTRO,PASA onother side

PCB’s delivered Feb 02

one type of FEC only!128 ch


PCI CARD (PLDA)

FEC- INTERFACE (PMC CARD)PCI CARD

PMC-PCIDDL-SIU CONNECTOR

Readout Control Unit (RCU) Prototype PCI Card + Mezzanine Card


Electronics Testing

Tasks defined and assigned to teamsFrankfurt, Lund, TU Darmstadt, Bergen, CERN, Heidelberg

A formidable task


LV and HV Grounding Scheme


Low Voltage: Connection to Power Supplies

~10 t Cu


Track efficiency and momentum resolution

> 95 % efficiency @ dN/dy = 8000


PID using dE/dx of TPC

dE/dx = 8.5%


ALICE Past and Future

ALICE TP 1995

TPC Technical Design Report 2000 2003: complete Field Cage and ROC series production 2004/5 Installation at CERN (above ground) Start of LHC 2007

The ALICE TPC Team

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