CERN – IT Department CH-1211 Genève 23 Switzerland t Open Access at CERN Tim Smith CERN/IT.
Thanushan Kugathasan, CERN Plans on ALPIDE development 02/12/2014, CERN.
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Transcript of Thanushan Kugathasan, CERN Plans on ALPIDE development 02/12/2014, CERN.
Pixel matrix in pALPIDEfs_V2
LOGO
Thanushan Kugathasan, CERN
Plans on ALPIDE development02/12/2014, CERN
In-pixel circuit
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 2
Strobe
Front-end analog output (pix_out)
• The front-end acts as an analogue delay line• 2 µs peaking time
• When Strobe is asserted, the front-end binary output is latched into the pixel state register
• Pixel state register readout by a zero suppression circuit (AERD)
Front-end / comparator
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
Analog Bias PurposeVRESET_P PMOS active reset diode biasIRESET PMOS active reset max currentVRESET_D Diode active reset diode biasIBIAS Front-End bias current (40 nA)ITHR Front-End threshold current (0.5 nA)IDB Inverter stage thresholdVCASP Front-End PMOS cascodeVCASN Front-End NMOS cascode, tuning of the DC outputVPULSE_LOW Pulsing Voltage Level (Low)VPULSE_HIGH Pulsing Voltage Level (High)
VRESET_P
PWELL
source
curfeed
VCASP
AVDD
AVSS
VCASN
M0b
D1
M1
M2
M3
M4
M5
IRESET
pix_in
pix_out
PIX_OUT_B
VPULSE_*
Cinj 160 aFVRESET_D
D0
Diode ResetPMOS Reset
AVSS
M0a
pix
_o
ut
cu
rfe
ed
Clipping
IBIAS
Cc
M0ITHR IDB
M6
M7
M8
Analog references generated by an on-chip 8-bit DAC
3
Pw ~ 40 nW/pixel=> 5 mW/cm2
pALPIDEfs_V2 - Sectors
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 4
Sector nwell diameter Spacing pwell
opening Reset Input PMOS W/L
0 2 µm 2 µm 6 µm PMOS 0.22
1* 2 µm 2 µm 6 µm PMOS 0.92
2 2 µm 4 µm 10 µm PMOS 0.22
3 2 µm 4 µm 10 µm Diode 0.22
PMOS reset Diode reset
Pulsing capacitor:0.16 fF
Input routing line
Input PMOS
pwell opening = nwell diameter + 2 . spacing
* Some pixels in sector 1 have antenna protection diode for the transistor connected to the bias lines.
In-pixel logic
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
2 Configuration bits:Pixel pulsingPixel masking
Sig
nals
buf
fere
d fr
om th
e pe
riphe
ry
Pixel State register
Test charge injection
Input from priority encoder
Output to priority encoder
5
Matrix Read-Out scheme
6Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
…
STATE
VA
LID
AD
DR
ES
SA
ER
D
PIX
EL
Fro
nt-e
nd
PIX
EL
Fro
nt-e
nd
Periphery Digital Readout
PIX
EL
Fro
nt-e
nd
PIX
EL
Fro
nt-e
nd
RESET
STATE
RESET
STATE
RESET
STATE
RESET
SY
NC 10
512 512
512 512
STATE
PIX
EL
Fro
nt-e
nd
PIX
EL
Fro
nt-e
nd
RESET
STATE
RESET
512 512
512 512
512 512
512 512
0 1 511
512
row
s
DACs
VA
LID
AD
DR
ES
S
SY
NC 10
VA
LID
AD
DR
ES
S
SY
NC 10
AE
RD
AE
RD
512 double columns
Address Encoder Reset Decoder (AERD)• Zero-suppression with priority encoder logic
Priority Encoder Logic
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 7
Unit block of the hierarchical tree element (repeated block)
RESET DECODER
ADDRESS ENCODER
STATE[0]STATE[1]STATE[2]STATE[3]
PRIORITY LOGIC
Fast ORVALID
ADDRESS[1]
ADDRESS[0]
SYNC[0]SYNC[1]SYNC[2]SYNC[3]
SYNC
HIERARCHY NHIERARCHY N-1 HIERARCHY N+1
Priority
• Hierarchical arbiter tree structure -> reduces loads, 5 levels to encode 1024 pixels • Fully combinatorial asynchronous circuit without clock propagating into the matrix
-> reduction of power & noise
▪ Provide active pixel address to periphery
▪ Propagate SYNC(RESET) from periphery to active pixel
▪ Process repeated until all hits are read out -in pixel memories reset one by one at each clock cycle
-readout duration depends on occupancy
Pixel layout
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
• 4 metal layers routing• Two power domains:
• Analog (Front-end)• Digital (Pixel logic and AERD)
8
Prio
rity
Enc
oder
(A
ER
D)
Pixel matrix detail
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 9P
ixel
Col
umn
(Lef
t)
Pix
el C
olum
n (R
ight
)
56 µm
Summary and outlook
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
• pALPIDEfs_V2 implements the same in-pixel circuit as in pALPIDEfs_V1 • 1024 x 512 pixels (28 µm x 28 µm)• New sectors• Minor layout changes
• pALPIDEfs_V1 pixel sensor is fully efficient in-pixel front-end with power consumption of 40 nW per pixel.
• reverse substrate bias offers more operation margin
• Goals for the next design:• Multiple in-pixel state registers.• Reduction of the threshold spread (~ 18 e- in pALPIDEfs_V1)• Reduction of the circuit input capacitance contribution.• Reduction of the front-end bias parameters.• Studies on pixel front-end outpt signal shaping time (pile-up, trigger latency).
10
Multiple in-pixel State Register
11Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
Multiple in-pixel State Register
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
3 Pixel state registers
12
Strobe<2:0> Memory to be written (front-end state latch)Mem_sel<2:0> Memory to be read and reset by the AERD readout
Pixel Logic I/O
Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 13
Signal DescriptionLogic level
0 1
INPUT
PULSE_TYPE Pulse type selection Enable DPULSE Enable APULSE
PULSE CMOS pulse see DPULSE and APULSE
PIXCNFG_DATA Configuration data D-LATCH data line
PIXCNFG_COLSEL Column selection Disable Enable
PIXCNFG_ROWSEL Row selection Disable Enable
PIXCNFG_REGSEL Register selection Pulse reg. Mask reg.
PIX_OUT_B Pixel front-end output Active low
STROBE_B<2:0> Strobe window (1 per state register bit) Active low
MEM_SEL_B<2:0> State register bit to be interfaced to the priority encoder Active low
PRST_B State register reset (global) Active low
PIX_RESET State register reset from priority encoder Effective on falling edgeOUT
STATEState register value to priority encoder (if MASK_EN = 0) Active high
State Register
14Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
3 x NAND SR Latches
State bit cell
15Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
Setlogic
Resetlogic
Set logic and reset have the same transistor level implementation
(x2)
State register output selection
16Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2
Transistor level