Mar 7, 2008 E0-286@SERC 1

VLSI Testing Random Access Scan Design

VLSI Testing Random Access Scan Design

Virendra SinghIndian Institute of Science (IISc)

Bangalorevirendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture – 18

Mar 7, 2008 E0-286@SERC 2

No Serial Scan (???) A solution to test power, test time and test

data volume

No Serial Scan (???) A solution to test power, test time and test

data volumeThree Problems with serial-scan

Test power Test application time Test data volume

Efforts and limitations ATPG for low test power consumption

Test power ↓ Test length ↑ Reducing scan clock frequency

Test power ↓ Test application time ↑ Scan-chain re-ordering (with additional logic insertion)

Test power/time ↓ Design time ↑ Test Compression

Test time/data size ↓ Has limited capability for Compacted test

Orthogonal attack Random access scan instead of Serial-scan Hardware overhead? Silicon cost << Testing cost

Mar 7, 2008 E0-286@SERC 3

Random Access ScanRandom Access Scan

Architecture

Each FF has unique address

Address shift register

X-Y Decoder

Select FF to write/read

A d d re ss R e g iste rS c a n - in

C U T

A d d re ss d e c o d e r(x)

F ilp - flo p s

Addre

ss d

ecoder(y

)

Saluja et al [ITC’04]

Mar 7, 2008 E0-286@SERC 4

Scan Operation ExampleScan Operation Example

Test vector

Test PPI(ii ) PPO(oi )

t1 00101 00110

t2 00100 00101

t3 11010 11010

t4 00111 01011

Scan operation for t2

CUT0

0

1

1

t1

0

0

0

1

01

1

0

1

1

i1 o1CUT

0

0

1

0

t2

0

0

0

1

10

1

0

1

1

i2 o2

Scan-inoperation

i1

o1

i2

o2

i3

o3

i4

o4

1

No. of scan

5 45

Complete test application Total number of scan operation = 15

Mar 7, 2008 E0-286@SERC 5

Test Vector OrderingTest Vector OrderingTest data volume and Test application time is proportional to the random access scan operationGoal: Reduce # scan operation

V3

Dummy

V2

V4

V15

5

5

5

01

13

3

5

4

2

4

5

1

4

Test PPI(ii ) PPO(oi )

t1 00101 00110

t2 00100 00101

t3 11010 11010

t4 00111 01011

# Scan operation = 8

Mar 7, 2008 E0-286@SERC 6

Hamming Distance ReductionHamming Distance ReductionDon’t care values in PPI do not need scan operation Use Don’t care identification method

Fully specified test vector Vectors w/ X values on targeted bit positionswithout loss of fault coverage

1. Before vector ordering: Identify don’t cares in PPI2. Vector ordering3. Simulate test vector in order / Fill X’s with previous vectors PPO4. Identify more X’s on targeted bit in PPI

- odd vector - even vector

5. Repeat 3,4 until no more X’s are identified

CUT

TF1

CUT

TF2

CUT

TF3

CUT

TF4

1X10X

0X1X0

X110X

1X001

1X110

1X011

11011

100X0

0X110

11011

11101

110X1

11001

Targeted

Change allowed

X 1 0

1

1

Mar 7, 2008 E0-286@SERC 7

Optimizing Address ScanOptimizing Address ScanThe cost of address shifting

# of scan operation x ASR width Example address set = { 1, 5, 6, 11 } for 4-bit ASR 4 X 4 = 16

Proper ordering of address can minimize shifting cost Apply 11(1011) after 5(0101) needs only 1 left-shift

Minimizing address shifting cost Construct Address Shifting Distance Graph (ASD-graph) Find min-cost Hamiltonian path using ATSP algorithm ( Result

: 5 shifts )

0001

0110

1011

2

0101

4 24

3

3

1

2

2

4

1

3

V = Aij = {1,5,6,11}

G = < V, E >

w(eij) =

0000

1

4

3

3

The number of minimum left-shift operation for the transition from v

i to v

j.

E = {eij | eij is an edge between vi and vj}

Last ASR contents of prev ious test vector

Mar 7, 2008 E0-286@SERC 8

Result (Test Time/Data)Result (Test Time/Data)

Test data volume

K100K200K300K400K500K600K700K800K900K

1000K

s13207s15850s35932s38417s38584

b17sb20sb22s

Benchmarks

Bits

Serial

RAS

Test Application time

K100K200K300K400K500K600K700K800K900K

1000K

s13207s15850s35932s38417s38584

b17sb20sb22s

Benchmarks

Clo

cks

Serial

RAS

Mar 7, 2008 E0-286@SERC 9

Result on Power ConsumptionResult on Power Consumption

Circuit

Peak Power consumption Avg. Power Consumption

Serial RAS Rate(%) Serial RAS Rate(%)

s5378 39.76 5 12.58 22.79 0.218 0.957

s9234 42.27 10.81 25.57 25.72 0.22 0.857

s13207 38.8 4.15 10.7 24.93 0.052 0.207

s15850 40.75 8.51 20.89 24.55 0.092 0.374

s35932 21.5 0.21 0.96 6.3 0.032 0.506

s38417 34.58 1.46 4.22 23.62 0.001 0.002

s38584 31.31 18.86 60.23 24.23 0.04 0.165

b17s 30.65 5.01 16.34 13.5 0.004 0.033

b20s 37.87 12.37 32.67 24.39 0.006 0.027

b22s 36.52 8.16 22.34 22.67 0.003 0.015

Peak power consumption is reduced 40% to 99%

Average power consumption is negligible!

• Switching activity is measured by simulation ( # of switching gate / total # of gate ) X 100 %

Mar 7, 2008 E0-286@SERC 10

Thank YouThank You