7/28/2019 Testability Consideration

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DESIGN FOR TESTABILITY

Design For Test is general term applied to design methods that lead tomore thorough and less costly testing

But Why?

Circuit densityDevice Speed

Surface Mount Technology

Complex Board Interconnect

Man YearsFor chip level and Board leveltesting

Man HoursFor testing the same

How to get away with it?

-Go-No go-Diagnostic Test

20Testing methodologies fordigital designs have gone20 years ahead comparedto analog designs

TESTING-Test vectors (n,2^n)

-Fault modeling

CONTROLLABILITY ANDOBSERVABILITY-Ease of producing desired values on internal signals-Ease of propagating internal signals to primary outputs

DIFFERENT TESTING METHODOLOG-Bed of Nail testing (Observability)

-In Circuit Testing(Controllability)

But Multi Layer PCBs, BGA, SMD etc

-Scan Methods

Scan Path method considers any digital circuit to be collection of flip flopsinter connected by combinational logic and is concerned with controllingand observing the state of the storage elements

TAG (IEEE 1149.1) TAG was developed as interface to support boundary scan testing.However the resulting interface has proved more generally useful as a wayto get data into and out of registers in hardware.

BOUNDARY SCANBoundary scan testing is a way of testing that the inputs and outputs of components on a board, or sub-systems on a chip, are connected correctly.

Boundary scan adds a simple logic cell (a scan cell) to each input andoutput, which can record the current state of that input or output.

Scan cell has no impact on the input or output, the cells may be directed tocapture or Update the current state of the input or output.

TAG CHIP ARCHITECTURE

The basic cycle of operat ion is a sequence of capture a register, shift in anew value from TDI, while simultaneously shifting out the old value on

TDO, then update the register with the valu e shifted in.

The TAP controller can shift values either through the instruction registeror through one of the other registers (collectively known as data registers).In the minimal configuration there are only two data registers: theboundary scan register and the bypass register. The bypass register is aconvenient mechanism when boundary scan testing is not being used.

The instruction register must be at least 2 bits long. IEEE 1149.1 requiresa minimum of 4 instructions:

BYPASSCapture, shift and update data through the bypass entry. This allows thechip to continue its normal operation. IEEE 1149.1 requires this instructionto consist of all 1's.

SAMPLE

Capture and shift data through the boundary scan register, thus taking asample of the data entering and leaving the chip via its inputs andoutputs. However the update phase does not drive data onto inputs oroutputs.

PRELOADShift data through the boundary scan register, thus setting up a value inthe scan cells for future use. For this instruction, the capture phase does

not get the previous value into the cell and the update phase does notdrive data onto inputs or outputs.

In early versions of the standard, this instruction was combined withSAMPLE.

EXTEST This is used to test connectivity between multiple chips. In extest mode thechip does not try to drive outputs or accept inputs. It is normal to usePRELOAD to set up the boundary scan register prior to EXTEST.

TAP STATE MACHINE The TCK and TMS signals drive a finite state machine in the TAP controller. TMS is sampled on the rising edge of TCK and used to advance the state

The actions taken in each state are as follows:

Test-Logic-ResetIn this state all test-modes (for example extest-mode) are reset, which willdisable their operation, allowing the chip to follow its normal operation.

At start-up the external logic will drive TMS high for at least 5 TCK cycles. This guarantees to reach the Test-Logic-Reset state and remain there.

Run-Test/Idle This is the resting state during normal operat ion.

Select-DR-Scan , Select-IR-Scan These are the starting states respectively for accessing one of the dataregisters (the boundary-scan or bypass register in the minimalconfiguration) or the instruction register.

Capture-DR , Capture-IR These capture the current value of one of the data registers or theinstruction register respectively into the scan cells.

This is a slight misnomer for the instruction register, since it is usual tocapture status information, rather than the actual instruction withCapture-IR.

Shift-DR , Shift-IRShift a bit in from TDI (on the rising edge of TCK) and out onto TDO (on thefalling edge of TCK) from the currently selected data or instruction registerrespectively.

Exit1-DR , Exit1-IR

These are the exit states for the corresponding shift state. From here thestate machine can either enter a pause state or enter the update state.

Pause-DR , Pause-IRPause in shifting data into the data or instruction register. This allows forexample test equipment supplying TDO to reload buffers etc.

Exit2-DR , Exit2-IR These are the exit states for the corresponding pause state. From here thestate machine can either resume shifting or enter the update state.

Update-DR , Update-IR The value shifted into the scan cells during the previous states is driveninto the chip (from inputs) or onto the interconnect (for outputs).

So we have a simple state machine, which allows either data registers orthe instruction register to go through its capture-shift-update cycle, withan option to pause during the shifting.

INSTRUCTIONSIEEE Std 1149.1 defines nine test instructions. Of the nineinstru ctions, three are required and six are optional.

BYPASS Instruction The required BYPASS instruction allows the IC to remain in afunctional mode and selects the bypass register to beconnected between TDI and TDO. The BYPASS instructionallows serial data to be transferred through the IC from TDIto TDO without affecting the operation of the IC. The bit codeof this instruction is defined as all ones by IEEE Std 1149.1.

SAMPLE/PRELOAD Instruction The required SAMPLE/PRELOAD instruction allows the IC toremain in its functional mode and selects the boundary-scanregister to be connected between TDI and TDO. During thisinstruction, the boundary-scan register can be accessed viaa data scan operation, to take a sample of the functional dataentering and leaving the IC. This instruction is also used topreload test data into the boundary-scan register beforeloading an EXTEST instruction. The bit code for this

instruction is defined by the vendor.

EXTEST Instruction The required EXTEST instruction places the IC into anexternal boundary-test mode and selects the boundary-scanregister to be connected between TDI and TDO. During thisinstruction, the boundary-scan register is accessed to drivetest data off-chip via the boundary outpu ts and receive test

data off-chip via the boundary inputs. The bit code of thisinstruction is defined as all zeroes by IEEE Std 1149.1.

Few optional instructions

INTEST Instruction The optional INTEST instruction places the IC in an internalboundary-test mode and selects the boundary-scan registerto be connected between TDI and TDO. During thisinstruction, the boundary-scan register is accessed to drivetest data on-chip via the boundary inputs and receive testdata on-chip via the boundary outputs. The bit code of thisinstruction is defined by the vendor.

RUNBIST Instruction The optional RUNBIST instruction places the IC in a self-testmode, enables a comprehensive self-test of the ICs core

logic, and selects a user-specified data register to beconnected between TDI and TDO. During this instruction, theboundary outpu ts are controlled so that they cannot interferewith neighboring ICs during the RUNBIST operation. Also,the boundary inputs are controlled so that external signalscannot interfere with the RUNBIST operation. The bit code of this instruction is defined by the vendor.

CLAMP Instruction The optional CLAMP instruction sets the outputs of an IC tologic levels determined by the contents of the boundary-scanregister and selects the bypass register to be connectedbetween TDI and TDO. Before loading this instruction, thecontents of the boundary-scan register can be preset withthe SAMPLE/PRELOAD instruction. During this instruction,data can be shifted through the bypass register from TDI to TDO without affecting the condition of the outputs. The bitcode of this instruction is defined by the vendor.

HIGHZ Instruction The optional HIGHZ instruction sets all outputs (inclu dingtwo-state as well as three-state types) of an IC to a disabled(high-impedance) state and selects the bypass register to beconnected between TDI and TDO. During this instruction,data can be shifted through the bypass register from TDI to

TDO without affecting the condition of the IC outputs. The bitcode of this instruction is defined by the vendor.

IDCODE Instruction The optional IDCODE inst ruction allows the IC to remain inits functional mode and selects the optional deviceidentification register to be connected between TDI and TDO. The device identificat ion register (see Figure 3-8) is a

32-bit shift register containing information regarding the ICmanufacturer, device type, and version code. Accessing thedevice identification register does not interfere with theoperation of the IC. Also, access to the device identificationregister should be immediately available, via a TAPdata-scan operat ion, after power-up of the IC or after the TAP has been reset using the optional TRST* pin or byotherwise moving to the Test-Logic-Reset state. The bit codeof this instruction is defined by the vendor.

USERCODE Instruction The optional USERCODE instruction allows the IC to remainin its functional mode and selects the device identificationregister to be connected between TDI and TDO. During theUSERCODE instuction, the optional 32-bit deviceidentification register captu res user-defined informationabout the IC. Accessing the device identification registerdoes not interfere with the operation of the IC. The bit codeof this instruction is defined by the vendor.