Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for: Design and realization in PSI T....
-
Upload
elmer-james -
Category
Documents
-
view
214 -
download
0
Transcript of Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for: Design and realization in PSI T....
TIAR
A Fi
nal M
eetin
g
Test of LLRF at SPARC
Marco BellavegliaINFN – LNF
Reporting for:• Design and realization in PSI
T. Schilcher, Andreas Hauff, Roger Kalt and LLRF section staff• Design, installation and tests in LNF
S. Gallo, M. Bellaveglia and RF group staff
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
TIAR
A Fi
nal M
eetin
g
Summary• Design and realization of the C band LLRF system at PSI• System description and specifications• Analogue sub-system description• Digital sub-system description• Measurements on the system at PSI
• Tests at INFN-LNF• Installation in the SPARC tunnel• Measurements on the system at LNF• Next future - System online for structure conditioning• Next year - Integration in the SPARC control system
• Conclusion 2
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
TIAR
A Fi
nal M
eetin
g
System description
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
3
• The system will interface a RF high power system• 1 klystron• 1 RF pulse compressor (SLED)• 2 accelerating structures
TIAR
A Fi
nal M
eetin
g
System specifications
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
4
• Analogue part• Number of RF signal receivers: 12 + 4 spares• RF Frequency 5.712 GHz• IF Frequency 39.666 MHz• Bandwidth (3dB) ±18 MHz• Phase resolution < 15 fs or 0.03 deg• Amplitude error ≈ 0.1 dB (10 dB range)
• Digital part• 16 ADC channels (to sample IF waveforms)• 4 DAC channels (for vector modulator control)• FPGA for signal processing• EPICS server implemented in the main CPU
TIAR
A Fi
nal M
eetin
g
Analogue sub-system
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
5
Main components:1. Vector modulator2. RF frontend
(receiver)3. LO, IF and sampling
clock frequencygenerator
TIAR
A Fi
nal M
eetin
g
Analogue sub-systemVector modulator• Differential I/Q inputs DC - 20 MHz bandwidth (3dB)• Integrated RF switches for interlock: 76 dB suppression
and 1us switching time Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
6
TIAR
A Fi
nal M
eetin
g
Analogue sub-systemVector modulator
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
7Integrate time jitter (from 10Hz to 10MHz) is 22 fs RMSNo significant jitter added to the reference oscillator
Output spectrum for a 1MHZ offset and19MHz offset frequency generated
TIAR
A Fi
nal M
eetin
g
Analogue sub-systemRF receiver board
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
8
down-converter channels (16)
Power supplyfilter
RF shielding
RF inputs (16)
TIAR
A Fi
nal M
eetin
g
Analogue sub-systemLO generator
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
9It generates the 5712+39.666MHZ LO frequency for the down-conversion of the RF signals to the IF
TIAR
A Fi
nal M
eetin
g
Analogue sub-systemFrequency divider
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
10• It generates all the frequencies needed by the system• IF, ADC clock, DAC clock
• Time jitter is about 100fs RMS
TIAR
A Fi
nal M
eetin
g
Digital sub-system
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
11
Main components:1. ADCs and DAC data
communication2. Digital signal
processing3. Control system
interface
TIAR
A Fi
nal M
eetin
g
Digital sub-system - Layout
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
12
MASTER SLAVE
TIAR
A Fi
nal M
eetin
g
Digital sub-systemADCs and DAC
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
13
ADC card• FMC516 from Curtiss-Wright• 4ch / 16bit / 250Msps / AC-
coupled• Read IF waveforms • 3 cards required for 12x ADC
channel + 1 spare
DAC card• FMC204 from 4DSP• 4-Channels / 16-bit / 1Gsps / AC
coupled• Convert 4ch AC coupled to 2ch
DC-coupled differential• Controls the vector modulator
TIAR
A Fi
nal M
eetin
g
Digital sub-systemFPGA and RT application
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
14
RT application• Data processing
• Read data from local memory• Computes averages, standard
deviations and jitters• Communication with EPICS
• Receive and handle inputs from epics
• Send raw and processed ADC channel data to epics
FPGA• RF signal processing• Interfaces ADCs and DAC• Write data on local memory
TIAR
A Fi
nal M
eetin
g
Digital sub-systemGUI software
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
15
• Provided by PSI• Programmed in QT
environment• It can read and write
most of the EPICS variables
• LLRF control is possible at SPARC at least in first operations
TIAR
A Fi
nal M
eetin
g
Measurements at PSI
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
16
• ADC IQ measured 3dB bandwidth (from IF): ±18MHz
• 180° phase jump performed in about 25ns (measured by 40Gs/s scope)
• Intra-pulse standard deviations:• LO Amplitude: 3.6 e-4 (relative)• LO Phase: 0.021°• VM Amplitde: 1.09 e-3 (relative)• VM phase: 0.13°
TIAR
A Fi
nal M
eetin
g
Tests at LNFInstallation in the SPARC tunnel
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
17
FRONT BACK
TIAR
A Fi
nal M
eetin
g
Tests at LNFVector modulator phase measurement
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
18
• Phase measured by two ADC channels just after system installation
• Vector modulator drift observed• System at regime in about 1h• In any case the drift can be
compensated with feedback
• Subtraction of the phase measured from the two channels
• Relative error on absolute phase in the two channel is• 0.015° RMS, considering the
thermal drift• 0.011° RMS at regime
TIAR
A Fi
nal M
eetin
g
Tests at LNFVector modulator amplitude and phase avg.
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
19
Variable StdevIntra-pulse relative ampli (1 / 3 us) 6e-4 / 7e-4Pulse-to-pulse relative ampli (100 avg, 1us) 2e-4Intra-pulse phase (1 / 3 us) 0.06° / 0.09°Pulse-to-pulse phase (100 avg, 1us) 0.01°
• Measured values meet the specifications• Vector modulator seems to perform better than in PSI• The DAC card has been substituted because it was not
functioning after the shipping at LNF. Maybe the card had worse performance because it was starting to malfunction in PSI
• We also are using a dedicated RF oscillator and not a frequency synthesizer
TIAR
A Fi
nal M
eetin
g
Tests at LNF - 180° phase jump
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
20
• Any shape of the vector modulator output waveform in amplitude and phase is possible
• 180° phase jump performed• System ready to feed pulse RF compressor
TIAR
A Fi
nal M
eetin
g
Next future – first power testsConditioning of the 2nd section
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
21
Acc. structure
Temporary LLRF
5712MHzRef signal
• The system will be used only to read the signals from cavity, maintaining the temporary LLRF system in use for a first test phase
TIAR
A Fi
nal M
eetin
g
Next future - Full capability testConditioning of the 2nd section
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
22Acc. structure
Temporary LLRF
5712MHzRef signal
• The system will be used in the conditioning both to drive the klystron and to read the signal from the power RF network
• System will be fully commissioned
TIAR
A Fi
nal M
eetin
g
Integration in the SPARC control system
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
23
• QT GUI provided by PSI and custom LabVIEW GUI running at the same time
• We can read/write every EPICS variable• System ready to be integrated in the SPARC control system
TIAR
A Fi
nal M
eetin
gD
ares
buty
– N
ovem
ber 2
5-27
201
3
24
Integration strategy
Other linac device
Other linac device
RF powersystem
PSILLRF
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
Ethernet
Ethernet
Ethernet
Serial, USB, firewire, …
Serial, USB, firewire, …
EPICSRF
cabling
TIAR
A Fi
nal M
eetin
gD
ares
buty
– N
ovem
ber 2
5-27
201
3
25
Integration strategy
Other linac device
Other linac device
RF powersystem
PSILLRF
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
Ethernet
Ethernet
Ethernet
Serial, USB, firewire, …
Serial, USB, firewire, …
EPICSRF
cabling
One layer addedto the CS architecture
TIAR
A Fi
nal M
eetin
gD
ares
buty
– N
ovem
ber 2
5-27
201
3
26
Integration strategy
Other linac device
Other linac device
RF powersystem
PSILLRF
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
FrontendCPU
w LabVIEW
Ethernet
Ethernet
Ethernet
Serial, USB, firewire, …
Serial, USB, firewire, …
EPICSRF
cabling
Standard RF frontendapplication is to be modified
to include the EPICS/LabVIEW interface
TIAR
A Fi
nal M
eetin
g
Conclusion
Dar
esbu
ty –
Nov
embe
r 25-
27 2
013
27
• Design and realization at PSI• Measurements on simulated signals at PSI show that
specifications are met• Shipping to LNF (substitution of the broken DAC card)• Measurements on simulated signal at LNF show that
specifications are met• EPICS/LabVIEW interface drivers provide full control of
LLRF• Test the system on real signals from RF power system• Conditioning of the second TW accelerating section using
LLRF from PSI• Full integration in the SPARC control system
• Done• December 2013• 2014