Temperature Sensor in CMOS Technology

Luís Miguel de Oliveira Costa

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Examination Committee

Chairperson: Prof. Doutor João Manuel Torres Caldinhas Simões Vaz

Supervisor: Prof. Doutor Jorge Manuel dos Santos Ribeiro Fernandes

Members of the Comitee: Prof. Doutor José António Beltran Gerald

November 2013

i

Acknowledgements

I would first like to express my gratitude to my dissertation supervisors Professor Doutor Jorge

Fernandes and Doutor Miguel Martins for sharing their knowledge, availability and advises

which have been very important for the development of this work. With them I have grown not

only in a technical way but also as a person.

Also, my colleagues and friends from the Analog and Mixed-Signal Circuits group David

Correia, Taimur Kuntz, Hugo Gonçalves, Diogo Brito, Rui Duarte and Professor António Couto

Pinto for all their companionship and precious help. To my dear friend Leonel Almeida who has

been a great friend throughout my academic and personal life.

To IST (Instituto Superior Técnico) and INESC-ID (Instituto Nacional de Sistemas e

Computadores – Investigação e Desenvolvimento) for contributing to my academic formation

and providing the necessary resources for this work. Also to FCT (Faculdade de Ciências e

Tecnologia) which supported this work through the Disruptive Project (EXCL/EEI-

ELC/0261/2012)

I would like to thank all of my friends I met in IST, Ricardo Martins, Tiago Carinhas, Pedro

Araújo, Carlos Fernandes, Dinis Bucho, Nuno Bernardo, Luís Afonso, Diogo Lucas, Magda

Santos, André Silva, Joana Fonseca, and Diana Freitas. They have been an active part of my

life since the moment I met them and we shared moments that I will never forget.

To my parents, António e Madalena, for their love and unconditional support. They have always

been there for me and without them this dream wouldn’t have been possible.

To everyone else who contributed more or less directly to the accomplishment of this work,

thank you!

ii

Abstract

This dissertation is focused on the implementation of an integrated smart temperature sensor in

CMOS technology.

An analysis of the state-of-the-art implementations is vital for a better understanding of the

several techniques used in temperature sensing in integrated circuits. A first approach for

implementing an existent topology of an analog temperature sensor is performed. The sensor is

dimensioned and its layout is designed using UMC 130nm technology. Design techniques were

used in order to present a compact and tolerant to manufacturing process errors. A low-power

circuit was achieved presenting, however a slight non-linearity at its output.

The most accurate existent temperature sensors consist of an analog frontend, used for

temperature sensing, followed by a ΣΔ analog-to-digital converter. The main objective of this

work is to propose an alternative technique of implementing the ΣΔ ADC. This technique avoids

the design of an operational amplifier (OpAmp), as well as the offset voltage compensation

circuit usually implemented to reduce measurement errors. This alternative technique presents

a comparator-based circuit, consisting of a dynamic comparator followed by a current source,

which replaces the operational amplifier. As this comparator-based circuit is only turned on

during short periods of time, it presents no static power consumption, thus lowering power

consumption when compared to an OpAmp-based topology.

The circuit is first studied at a high-level, in order to confirm the validity of this solution. The

transistor level circuit is designed as well as its respective layout. Simulation results still show a

non-linearity at the digital output of the smart temperature sensor, which result from undesired

charge injection at its input. Nevertheless, the proposed topology proves to be a good

alternative for these types of circuits when low power consumption is preferred to accuracy.

Keywords:

Smart Temperature Sensor

ΣΔ ADC

Comparator-based circuit

Low-Power

iii

Resumo

A presente dissertação tem como objectivo a implementação de um sensor de temperatura

integrado digital em tecnologia CMOS.

Para uma melhor compreensão das várias técnicas usadas na medição da temperatura com

circuitos integrados é necessária uma análise a diversas implementações que representam o

estado de arte deste tipo de circuitos. Assim, é feita uma primeira abordagem de

implementação de um sensor de temperatura analógico já existente, em que o sensor é

dimensionado e desenhado o respectivo layout em tecnologia UMC de 130nm. As técnicas de

desenho de layout foram utilizadas de modo a apresentar um circuito compacto e tolerante a

erros de processo de construção. Foi obtido um circuito de baixo consumo apresentando, no

entanto, uma ligeira não-linearidade na tensão de saída.

Os sensores de temperatura que apresentam maior exactidão consistem num sensor de

temperatura analógico seguido de um conversor analógico-digital ΣΔ. O principal objectivo

deste trabalho é o de propor uma técnica alternativa para implementar o conversor analógico-

digital. Esta técnica evita não só o projecto de um amplificador operacional (AmpOp), mas

também dos circuitos de redução de tensão de desvio normalmente a ele associados, para

reduzir erros de medição. Esta técnica alternativa apresenta um circuito baseado num

comparador que consiste num comparador dinâmico seguido de uma fonte de corrente, que

substitui o amplificador operacional. Como este novo circuito apenas é ligado durante curtos

intervalos de tempo, não apresenta consumo estático diminuindo, assim, o consumo quando

comparado com uma topologia baseada num AmpOp.

O circuito é primeiramente estudado num modelo de alto-nível, de modo a confirmar a validade

da solução. De seguida, é desenhado ao nível do transístor e finalmente desenhado o layout.

Os resultados obtidos por simulação demonstram ainda uma ligeira não-linearidade na saída

do sensor de temperatura digital, que resulta de injecção de cargas indesejadas na sua

entrada. Ainda assim, a topologia proposta prova ser uma boa alternativa para estes tipos de

circuitos, especialmente em aplicações que exijam baixo consumo.

Palavras-chave:

Sensor de temperatura digital

Conversor A/D ΣΔ

Circuito baseado em comparador

Baixo Consumo

iv

Table of Contents

Acknowledgements i

Abstract ii

Resumo iii

Table of Contents iv

List of Tables vi

List of Figures vii

List of Terms ix

1. Introduction 1

1.1. Context and Motivation 2

1.2. Objectives 3

1.3. Dissertation Outline 4

2. Temperature Sensing in Integrated Circuits 5

2.1. Bipolar Junction Transistor 6

2.2. Integrated Temperature Sensors 8

2.2.1. Analog Temperature Sensors 8

2.2.2. Smart Temperature Sensors 12

2.3. State-of-the-art 15

2.4. Conclusions 16

3. Temperature Sensor Design 18

3.1. Integrated Smart Temperature Sensor 19

3.1.1. Bipolar Junction Front-End 19

3.1.2. Sigma-Delta A/D Converter 20

a) OpAmp-Based Modulator 22

b) CBSC-Based Modulator 24

3.1.3. Digital Block Back-End 25

3.2. Model Implementation 28

3.2.1. High-Level circuit 28

3.2.2. Results 29

3.3. Conclusions 31

4. Implementation in UMC 130nm Technology 32

4.1. Bipolar Front-End 33

v

4.2. Comparator-based Circuit 36

4.2.1. Comparator 36

4.2.2. Current Source 39

4.3. Latch Comparator 42

4.4. D Flip-Flop 44

4.5. Switches 45

4.6. 1-bit D/A Converter 48

4.7. 12-bit Binary Counter 49

4.8. Multi-Phase Generator 50

4.9. Layout 51

5. Simulation Results 53

5.1. Introduction 54

5.2. Simulations of the complete sensor 54

5.3. Simulations of the ΣΔ-ADC 55

5.4. System Resolution 56

5.5. Power consumption simulations 56

5.6. Conclusions 57

6. Conclusion and Future Work 59

6.1. Conclusion 60

6.2. Future Work 61

Annexes 62

References 71

vi

List of Tables TABLE 1.1 - DIFFERENT IC TEMPERATURE RANGE CLASSES[1] 3

TABLE 2.1- DIMENSIONS OF THE PTAT SENSOR TRANSISTORS 10

TABLE 2.2 - COMPARISON OF EXISTENT ANALOG AND SMART TEMPERATURE SENSORS 15

TABLE 3.1 - SAMPLING PERIODS AND CONVERSION TIME FOR DIFFERENT RESOLUTIONS AND SAMPLING FREQUENCIES 26

TABLE 3.2 - HIGH-LEVEL MODEL PARAMETERS 28

TABLE 4.1 - FRONTEND TRANSISTOR SIZING 35

TABLE 4.2 - COMPARATOR PARAMETERS 36

TABLE 4.3 - TRANSISTOR DIMENSIONS USED IN THE DELAY EQUALIZER BLOCK 37

TABLE 4.4 - PULL-DOWN CONTROL CIRCUIT CHARACTERISTICS 41

TABLE 4.5 - FLIP-FLOP D DIMENSIONS 45

TABLE 4.6 - TRANSISTOR SIZING OF THE 1-BIT DAC 49

TABLE 4.7 - MULTI-PHASE GENERATOR DIMENSIONS 51

TABLE 5.1- POWER CONSUMPTION MEASUREMENTS 57

vii

List of Figures FIGURE 1.1 - SEVERAL APPLICATIONS FOR INTEGRATED TEMPERATURE SENSORS 2

FIGURE 2.1 - THE TWO TYPES OF BIPOLAR TRANSISTORS. (A) NPN. (B) PNP 6

FIGURE 2.2 - A NPN BIPOLAR TRANSISTOR CONNECTED AS A DIODE 6

FIGURE 2.3 - AN ANALOG PTAT VOLTAGE REFERENCE CIRCUIT 8

FIGURE 2.4 - PTAT SENSOR SCHEMATIC 10

FIGURE 2.5- PTAT CIRCUIT LAYOUT 11

FIGURE 2.6 - PTAT CIRCUIT OUTPUT VS. LINEAR REGRESSION 11

FIGURE 2.7 - DIAGRAM OF AN INTEGRATED SMART TEMPERATURE SENSOR [4] 12

FIGURE 2.8 - TOPOLOGY USED TO OBTAIN VPTAT AND VREF [10] 12

FIGURE 2.9 - BIPOLAR FRONT-END VOLTAGE VARIATIONS WITH ABSOLUTE TEMPERATURE [4] 13

FIGURE 2.10 - DIGITAL SENSOR BASED ON TEMPERATURE-DEPENDENT DELAYS OF CMOS INVERTERS [5] 13

FIGURE 2.11 - BLOCK DIAGRAM OF A COMPLETE ΣΔ ADC 14

FIGURE 3.1 - INTEGRATED SMART TEMPERATURE SENSOR ARCHITECTURE 19

FIGURE 3.2 - SENSOR FRONT-END USED IN THE PRESENTED WORK 20

FIGURE 3.3 - WAVEFORMS IN A 1ST ORDER ΣΔ ADC WITH DIFFERENT INPUT VOLTAGES. (A) LOWER ΔVBE. (B) HIGHER ΔVBE21

FIGURE 3.4 - OPAMP-BASED SWITCHED-CAPACITOR ΣΔ MODULATOR 22

FIGURE 3.5 - EVOLUTION OF VO DURING THE CHARGE TRANSFER PHASE 23

FIGURE 3.6 - COMPARATOR-BASED SWITCHED-CAPACITOR ΣΔ MODULATOR 24

FIGURE 3.7 - OPERATION OF THE COMPARATOR-BASED CIRCUIT 24

FIGURE 3.8 - A 4-BIT DIGITAL SYNCHRONOUS BINARY COUNTER 26

FIGURE 3.9 - A 12-BIT SYNCHRONOUS BINARY COUNTER 27

FIGURE 3.10 - COMPARATOR IMPLEMENTED WITH HIGH-LEVEL MODEL 29

FIGURE 3.11 - HIGH LEVEL TRANSIENT SIMULATION 29

FIGURE 3.12 - HIGH LEVEL CIRCUIT OUTPUT VS. RELATIVE ERROR 30

FIGURE 4.1 - IMPLEMENTED ANALOG SENSOR FRONT-END 33

FIGURE 4.2 - VBE VARIATION WITH DIFFERENT BIASING CURRENTS 34

FIGURE 4.3 - ΔVBE VARIATION WITH DIFFERENT BIASING CURRENTS 34

FIGURE 4.4 - ΔVBE AND RESPECTIVE RELATIVE ERROR WITH DIFFERENT BIASING CURRENTS 35

FIGURE 4.5 - COMPARATOR WITH POSITIVE FEEDBACK [18] 36

FIGURE 4.6 - DELAY EQUALIZER BLOCK [18] 37

FIGURE 4.7 - DELAY EQUALIZER INPUT (RED) AND RESPECTIVE OUTPUTS 38

FIGURE 4.8 - LOAD BALANCE CIRCUIT 38

FIGURE 4.9 - CBSC COMPARATOR RESPONSE 39

FIGURE 4.10 - PMOS CURRENT MIRROR WITH POWER DOWN INPUT 39

FIGURE 4.11 - PULL-DOWN SWITCH CONTROL CIRCUIT 40

FIGURE 4.12 - VO PULL-DOWN SIMULATION 41

FIGURE 4.13 - CURRENT SOURCE CONTROLLED BY THE DYNAMIC COMPARATOR 42

FIGURE 4.14 - LATCH COMPARATOR 43

FIGURE 4.15 - LATCH COMPARATOR TESTBENCH SIMULATION 44

FIGURE 4.16 - POSITIVE EDGE-TRIGGERED D FLIP-FLOP 44

FIGURE 4.17 - D FLIP-FLOP LOGIC SIMULATION 45

FIGURE 4.18 - NMOS SWITCH 46

FIGURE 4.19 - NMOS SWITCH SIMULATION 47

FIGURE 4.20 - PMOS SWITCH 47

FIGURE 4.21 - CMOS SWITCH 48

FIGURE 4.22 - IMPLEMENTED 1-BIT D/A CONVERTER 48

FIGURE 4.23 - 1-BIT DAC SIMULATION 49

viii

FIGURE 4.24 - 12-BIT BINARY COUNTER SIMULATION 50

FIGURE 4.25 - MULTI-PHASE GENERATOR 50

FIGURE 4.26 - NON-OVERLAPPING OUTPUTS OF THE PHASE GENERATOR BLOCK 51

FIGURE 4.27 - LAYOUT OF THE TEMPERATURE SENSOR 52

FIGURE 5.1 - FULL SENSOR OUTPUT (BLUE) VS. RELATIVE ERROR (RED) 54

FIGURE 5.2 - ΣΔ ADC RESPONSE TO LINEAR INPUT (BLUE) VS. RELATIVE ERROR (RED) 55

FIGURE 5.3 - CURRENT SWITCHING AT THE SENSOR FRONTEND: VBE (RED); BIASING CURRENT (BLUE) 56

ix

List of Terms

ADC Analog-to-Digital Converter CBSC Comparator-Based Switched Capacitor

VBE Base-Emitter voltage VCE Collector-Emitter voltage VT Thermal voltage IS Saturation current q Electron charge k Boltzmann’s constant IC Integrated Circuit

PTAT Proportional To Absolute Temperature BJT Bipolar Junction Transistor TC Temperature Coefficient

MOSFET Metal-Oxide Semiconductor Field-Effect Transistor CMOS Complementary Metal-Oxide Semiconductor PMOS P-type Metal-Oxide Semiconductor NMOS N-type Metal-Oxide Semiconductor TDC Time-to-Digital Converter ΣΔ Sigma-Delta SC Switched-Capacitor µ Electron Mobility

Vth Transistor Threshold Voltage OpAmp Operational Amplifier

DEM Dynamic Element Matching CDS Correlated Double Sampling CBC Comparator-Based Circuit DAC Digital-to-Analog Converter

1

Capítulo 1

1. Introduction ____________________________________________________

2

1.1. Context and Motivation

Temperature sensors are nowadays used in a wide range of applications, from regular thermometers

to the most advanced monitoring systems. As analog sensors (thermistors, mercury thermometers, or

bimetallic thermometers) make sense in some cases, like thermostats, digital temperature sensors are

more suited to applications with digital processing.

Figure 1.1 – Several applications for integrated temperature sensors

Temperature sensors are, hence, widely applied in measurement, instrumentation and control

systems. Thus, it is fundamental to fabricate sensors in integrated circuit technology with a digital

output. An integrated digital temperature sensor can easily communicate with a microprocessor,

allowing it to collect data and to make decisions providing different types of outputs.

Being temperature an analog physical quantity, the sensor is usually combined with an analog

interface which reflects its variation into the system. If this input is translated into a digital format (e.g.

by means of an analog-to-digital converter), the system is classified as a smart temperature sensor.

The implemented sensor is based on a bipolar junction frontend, which is the key element for sensing

the temperature variation, followed by a first-order ΣΔ analog-to-digital converter (ADC) that produces

a digital bitstream which is, then, converted into a digital word by a digital backend. The circuit is

developed in UMC 130nm CMOS technology, which allows the temperature sensor to be integrated

into VLSI chips, reducing fabrication cost and measuring on-chip temperature directly.

3

1.2. Objectives

The objective of this work is to study and develop a high accuracy smart temperature sensor, using a

comparator-based switched capacitor (CBSC) circuit. The goal is to implement a low-power circuit by

eliminating static power consumption commonly absorbed by the OpAmp used in ΣΔ A/D converters.

This reduces the circuit overall power consumption, area and, therefore, cost. Also, reducing the

supply voltage affects directly the swing and gain of amplifiers. Avoiding its use also prevents the

design of a high-gain amplifier with a low supply voltage.

As referred before, temperature sensors have many applications. Thus, accuracy and precision

requirements vary from application to application. The sensor range is also an important characteristic

to take into account. Temperature range represents the operating range within which the accuracy of

the sensor is guaranteed. Table 1.1 shows different ratings used to classify integrated circuit (IC)

temperature sensors.

Class Lower limit Upper limit

Commercial 0º C +70ºC

Industrial -40ºC +85ºC

Extended -40ºC +125ºC

Military -55ºC +125ºC

Table 1.1 – Different IC temperature range classes[1]

Measurements from -55ºC up to 150ºC were performed in order to achieve an objective wider than the

military range. Power consumption is kept in mind in order to develop a low-power system with a 1.2V

supply voltage.

The layout of the final circuit will also be designed in order to allow on-chip production of the

temperature sensor.

4

1.3. Dissertation Outline

In Chapter 2, it is explained the basics of how to perform temperature sensing in integrated circuits.

Analog and smart temperature sensors, based on different working principles are described, which

represent some of the state-of-the-art sensors.

In Chapter 3 the proposed approach in this work is described. The adopted solution is compared to an

existing topology and its advantages are discussed. In Section 3.2, a high-level model is designed and

its results are shown, in order to validate this approach.

In Chapter 4, it is explained the implementation of the circuit in UMC 130nm technology. Each block is

described, designed and simulated individually and the respective layout is shown in Section 4.9.

In Chapter 5, the results obtained with the implemented circuit are shown. Analysis to the system

linearity, resolution and power consumption is performed.

Finally, in Chapter 6, conclusions and future work are presented.

5

Capítulo 2

2. Temperature Sensing in

Integrated Circuits ____________________________________________________

6

In this chapter, the most common techniques of temperature sensing in CMOS technology are

introduced. In section 2.1, the structure of the bipolar junction transistor is described, as well as the

temperature influence on its behavior and its advantages in integrated temperature sensing. The

difference between smart and analog temperature sensors is explained in Section 2.2, and a

comparison between several state-of-the-art temperature sensors is presented in Section 2.3.

2.1. Bipolar Junction Transistor

In order to create an accurate temperature sensor, the need for an element which behaves linearly

with temperature is absolutely essential. This element should be highly tolerant to process variations

and also present high repeatability at its output.

The PN junction consists in a P-type and an N-type doped silicon regions and not only it is very

common in integrated circuitry, but also its operation mode is well known. The structure of a bipolar

junction transistor (BJT) consists of three terminals which form two junctions among them.

N

N

P

C

B

E

NB

E

C

P

P

(a) (b)

IC

ICIE

IE

IB IB

Figure 2.1 - The two types of bipolar transistors. (a) NPN. (b) PNP

To take advantage of the PN junction of a bipolar transistor its base can be connected to the collector,

resulting in a two-terminal device formed by the emitter and the base/collector. The behavior of the

transistor will, then, become very similar to a diode (PN junction).

E

B

C IC

IEE

C

B VCE

VBEE

IE=IC

C

VBE=VCE

Figure 2.2 - A NPN bipolar transistor connected as a diode

When the VBE voltage is positive, the current flowing through the device is approximately [1]

(2.1)

7

The thermal voltage (VT) is given by

(2.2)

where k is the Boltzmann’s constant (k = 1.38 x 10-23

J/K) and q is the value of the electron charge

(q = 1.60 x 10-19

C).

The saturation current (IS) depends on the diode’s physical parameters and is constant at a given

temperature. However, its value is strongly temperature dependent [2].

The thermal voltage is, as can be seen in Eq. (2.2), directly proportional to the room absolute

temperature. The temperature coefficient (TC) is, then,

(2.3)

Thus, for a variation of 100ºC, its value rises about 8.62 mV. At 27ºC, VT is approximately 25.85 mV.

For values of VBE much greater than VT ( ), IS is negligible facing IC, validating the following

approximation

(2.4)

Under this condition, IC varies exponentially with the voltage drop across the device (VBE) and this

voltage can be expressed by

(2.5)

Given the fact that IS is process and temperature dependent, VBE is not a linear function with the

temperature (T) and, thus, it is not possible to determine the absolute temperature at which the device

is operating by simply analyzing Eq. (2.5). However, if two different currents (IC1 and IC2) are used to

bias two matched bipolar transistors (connected as diodes), the voltage difference at their terminals

will be

(

)

(

)

(2.6)

This method eliminates the dependency on IS. The difference between the two voltage drops is, then,

a linear function with temperature. This result is achieved assuming IS1 = IS2 (matched transistors) and

that the relation between the two collector currents is maintained across the temperature range of

operation of the circuit.

8

2.2. Integrated Temperature Sensors

Mainly, there are two types of temperature sensors in integrated circuits. These categories are

described in the following sections.

2.2.1. Analog Temperature Sensors

Analog temperature sensors create a temperature-dependent voltage reference. In this type of circuits

a PTAT (Proportional To Absolute Temperature) voltage is presented at the output.

The circuit in Figure 2.3 shows a possible topology to measure the room temperature and obtain the

desired behavior [3].

M1 M2

M3M4

M5

RD1 , 1

D2 , K

L.R

VPTAT = I.L.R

I1 I2

Figure 2.3 - An analog PTAT voltage reference circuit

A CMOS current mirror is used to generate equal currents (I1 = I2), regardless of the supply voltage

[3]. In order to promote current flow through the resistor, the voltage drop across D2 (VD2) must be

smaller than the one across D1. There are two ways of creating this condition. The first one consists of

sizing D2 greater than D1 so that the same amount of current flowing through both of the devices

would originate a smaller voltage drop across D2. This happens because the value of the saturation

current is directly proportional to the device junction area [2]. Thus, for the same collector current a

lower VBE will be obtained, according to Eq. (2.5). However, it is also possible to use equal devices

and reduce VD2. If K diodes in parallel are used to implement D2, the current I (on the right branch of

the CMOS current mirror) will flow equally through K devices. The voltage drop across the diodes D1

and D2 can be expressed by

(2.7)

and

(2.8)

9

So, as the current flowing through each of the K devices in parallel is smaller than the current flowing,

on the left branch, through D1, VD2 will also be smaller than VD1. Assuming that the two branches of the

current mirror are matched, ID1=ID2=I. Hence,

(2.9)

Using both Eq. (2.7) and Eq. (2.8) and considering IS1=IS2=IS (because, with this method, all transistors

have the same size), it is possible to rewrite Eq. (2.9) as follows

(

*

(

* ⇔

[ (

* (

*]

(

)⇔

⇔

(2.10)

The current I will, then, be proportional to absolute temperature. However, the temperature coefficient

of the resistor will distort the linearity of the PTAT current. In order to obtain a PTAT voltage (VPTAT),

the current is mirrored by M5, on the right branch of this circuit. The resistor on this branch defines the

voltage at the output of the circuit. This voltage will, then, be given by

(2.11)

where L is a scale factor between the two resistors used in this circuit. Considering I as described in

Eq. (2.10), VPTAT can be expressed by

(2.12)

If two resistors of the same type are used, they will both have the same TC. Thus, the non-linear

behavior of the resistor used to generate the current I will be cancelled by the identical behavior of the

one used to generate the output voltage. The distortion caused by the resistors can, then, be

neglected and the temperature dependency of VPTAT can be assumed as linear, with a TC given by

(2.13)

The value of the scale factor L is used not only to adjust the desired TC of the circuit, but also to

define the operating point of its output voltage.

On an early phase of this work, this circuit was implemented. The goal was to better understand the

designing process of an integrated circuit in this specific 130nm CMOS technology.

10

Figures Figure 2.4 and Figure 2.5 show the implementation of the circuit in 130nm UMC technology.

This circuit follows the same design proposed in [3]. Transistors MSU1:3 implement a startup circuit.

This ensures, at system power-up, that the circuit starts working properly, setting the correct initial

conditions for the current source.

Figure 2.4 - PTAT sensor schematic

To implement this circuit on UMC 130nm technology, the following transistor dimensions were

adopted:

M1, M2, M5 M3, M4 MSU1 MSU2, MSU3

Width [m] 30µ 10µ 600n 200n

Length [m] 3µ 3µ 200n 200n

Table 2.1- Dimensions of the PTAT sensor transistors

The bipolar junction transistors were implemented using vertical npn transistors and the resistors were

implemented by high resistance poly resistors, available in this technology.

The layout of the implemented sensor is presented in Figure 2.5. The connection pads are on the left

side of the layout. The bipolar transistor D1 is placed at the center of the eight D2 transistors to

minimize errors due to manufacturing process variations. The resistors, as well as the PMOS and

NMOS transistors are located above the vertical npn bipolar transistors. The circuit occupies a die

area of 115μm x 156μm = 0.018mm2 and 223μm x 202μm = 0.045mm

2 with pads included.

11

Figure 2.5- PTAT circuit Layout

In order to evaluate the output linearity of this sensor, a simple linear regression was applied to the

results obtained by extracted layout simulation. These results are presented in Figure 2.6.

Figure 2.6 - PTAT circuit output Vs. Linear regression

As can be observed by the results obtained, the output presents a non-linearity of ±1.5% relative to

the respective linear regression. A temperature coefficient 0,96mV/ºC of was obtained. Although this

circuit presents low power consumption, (from 3.2µA at -40ºC to 16.6µA at 125ºC) it cannot be used

as a frontend for the proposed smart temperature sensor due to its non-linearity.

12

2.2.2. Smart Temperature Sensors

Smart temperature sensors provide a digital output, based on a sensor front-end and an analog-to-

digital converter on the same chip. The output (a sequential digital word) depends on the room

temperature at which the device is operating.

Figure 2.7 – Diagram of an integrated smart temperature sensor [4]

There are several ways of implementing the analog front-end of the sensor. Although there are

accurate digital sensors that use inverter delay lines to obtain temperature-dependent delays [5], [6],

most smart temperature sensors make use of bipolar transistors to create a linear ratiometric

difference at the input of the ADC. This difference can be obtained by biasing two matched bipolar

transistors connected as diodes with different collector currents, as shown in Figure 2.8.

Figure 2.8 – Topology used to obtain VPTAT and VREF [10]

Although the variation of VBE1 and VBE2 is non-linear with temperature, the difference ΔVBE has a PTAT

behavior (with a positive TC), as shown in Eq. (2.6). To generate a reference voltage (independent of

room temperature), ΔVBE is amplified and added to VBE1, so that the negative variation of VBE1 with

temperature can be compensated, resulting in a constant voltage, VREF, throughout the circuit’s

temperature range.

(2.18)

13

The PTAT voltage is obtained directly by amplifying the accurate temperature-dependent voltage

difference, ΔVBE, using an operational amplifier (OpAmp). For better understanding, this process is

illustrated in Figure 2.9.

Figure 2.9 – Bipolar front-end voltage variations with absolute temperature [4]

In this case, the inputs of the ADC are VPTAT and VREF. As VREF is constant and VPTAT increases linearly

with temperature, the converter receives an accurate, temperature-dependent, voltage ratio.

The sensor presented in reference [5] bases its temperature sensing on the thermal dependence of

CMOS inverter delay lines.

Figure 2.10 - Digital sensor based on temperature-dependent delays of CMOS inverters [5]

The time-to-digital converter compares the time gap, Δt, between the delayed signal and a

temperature-independent reference signal, transforming an analog quantity (time) into a digital word.

The delay, D, on a balanced CMOS inverter is given by [5]

⁄

⁄ (2.15)

where the electron mobility, µ, and the threshold voltage, Vth, are temperature dependent. As Vth has a

low variation with temperature, the error committed by considering its value constant is minimal and

14

the delay can be expressed as a function of temperature, T-α

(which is affected by the electron

mobility) , and process variation, G(P):

(2.16)

As G(P) depends on process variation and T-α

depends on temperature, calibration at one known

temperature is performed so that a normalized delay can be obtained when the sensor is operating at

different temperatures. Hence,

(

)

(2.17)

After this 1-point calibration the digital word at the time-to-digital converter (TDC) output represents

accurately the temperature at which the device is operating, based on the time difference between a

normalized and a reference delay. The delay reference is obtained by an open-loop delay line locked

to a crystal oscillator which produces a temperature independent delay.

The second stage of a smart temperature sensor is the analog-to-digital converter. Different analog

front-ends require different converters. Analog sensors based on temperature-dependent delay lines

require time-to-digital converters [5], [6], while voltage-output sensors use voltage-based ADCs to

create a digital word. Sigma-Delta (ΣΔ) modulation is the most commonly used technique. The ΣΔ

modulator works at much higher frequencies than the one at which the input signal varies. This is

called oversampling and although it decreases the bandwidth of the converter, it also increases its

resolution. Considering that room temperature has a slow variation, bandwidth is not a restriction to

this type of converter.

A ΣΔ ADC consists in an anti-aliasing filter, a sample-and-hold, followed by the ΣΔ modulator and a

decimation filter.

Figure 2.11 – Block diagram of a complete ΣΔ ADC

The analog signal is passed through a low pass filter in order to reduce the input’s bandwidth to the

band of interest. In cases where the input presents a wide bandwidth, the use of such filter is

imperative, so that the sampling theorem [7] is satisfied and the desired signal is unambiguously

interpreted.

The sample-and-hold circuit provides the ΣΔ modulator enough time to perform the conversion of the

analog input signal into a digital bitstream. As ΣΔ modulators are usually Switched-Capacitor (SC)

15

circuits, the sampling function is performed inherently at the input of the modulator. At the back-end of

the converter, the decimation filter (which consists in a digital low-pass filter followed by a down

sampler) converts the bitstream into a digital word. The low-pass filter removes modulation noise,

which is dominant at high frequency, and the down sampler reduces the sampling frequency to the

desired output rate. Besides, in first-order ΣΔ converters, the decimation process can be performed by

a digital counter [4] which, given a well-defined period, counts the number of times that the modulator

output is at logic level “high”. The output at the back-end of the converter is then, obtained, as a digital

word based on a temperature-dependent bitstream determined by the ΣΔ modulator.

2.3. State-of-the-art

Different applications not only require different types of temperature sensors, but also demand certain

specifications in terms of power consumption, temperature range and accuracy.

Table 2.2 compares some important characteristics of several analog and smart temperature sensors

developed in works up to date.

Sensor Temperature

Range Max. Error

Resolution Power Consumption

TMP36 [8] -40ºC ~ +125ºC ± 2ºC N/A 50µA@2.7V

[5] 0ºC ~ +100ºC ± 1ºC 0.66ºC 1.2mW@1.2V

[9] -40ºC ~+120ºC ± 1ºC 0.625ºC 7 µA@2.2V

(2 samples/s)

[10] -55ºC ~ +125ºC ± 0.1ºC 0.01ºC @ 10 conv/s 0.002ºC @ 1conv/s

75µA@2.7V-5.5V

[11] -70ºC ~+125ºC ± 0.2ºC 0.03ºC 8.3µA@1.2V

[12] -70ºC ~ +130ºC ± 0.25ºC 0.025ºC 25µA@2.5V-5.5V

Table 2.2 - Comparison of existent analog and smart temperature sensors

Analog Devices, Inc. provides a commercialized integrated analog temperature sensor, with a typical

±2ºC inaccuracy over the operating range mentioned above. No calibration is needed and its output

consists in a PTAT voltage based on the base-emitter voltages of two different npn bipolar transistors

(ΔVBE) biased by equal collector currents. Thus, similarly to Eq. (2.6) [8],

(

* (2.14)

were AE,Q1 and AE,Q2 represent the emitter areas of the two BJT. Due to its analog nature, this sensor

can be used not only in fire alarms, thermal protection systems, industrial processes, etc. [8], but can

also be used to control A/D converters, hence integrating digital systems as well.

Regarding the remaining sensors presented in Table 2.2, bipolar transistors are used to implement the

sensor front-end. The PTAT voltage, ΔVBE, is obtained based on the principle referred in Section 2.1,

16

(see Eq. (2.6)) where two matched transistors connected as diodes are biased by different collector

currents. These sensors use ΣΔ modulators to obtain the digital word at the output of the temperature

sensor. As referenced before, this type of modulation is particularly effective at low frequency inputs,

providing a high resolution digital output, required in accurate temperature sensing. In order to reduce

measurement errors, techniques like dynamic element matching (DEM) [10], [11], [12], correlated

double sampling (CDS) [10], [11] and OpAmp chopping circuits [9], [10], [12] were used. Errors at the

sensor level are reduced, as well as the errors associated with the analog-to-digital conversion.

Hence, curvature correction of the non-ideal BJT VBE characteristic is essential, through DEM of the

biasing currents, OpAmp offset reduction and precision layout design. In [11], npn transistors are used

to implement the sensor front-end. The base-emitter voltages are, hence, independent of the

transistors’ current gain, which promotes a reduction on the complexity of the collector current biasing

circuitry.

As sensors implemented in references [9] and [11] present first-order ΣΔ modulators, the ones in

references [10] and [12] make use of second-order ΣΔ modulation to convert temperature into a digital

word. Although the first-order ΣΔ modulator is simpler to implement and presents high stability and a

wide input signal range, a second-order modulator is able to achieve the same output resolution in

fewer clock cycles. Thus, reduced clock frequencies (of about 10 kHz) can be used, which presents an

advantage in terms of the overall power consumption of the sensor [4]. The implementation of such

modulators, however, is more complex and leads to an increase of the circuit area, as they require two

stages of integration, and a more complex decimation filter. Low offset amplifiers are implemented

through chopping and CDS techniques. As switched capacitor circuits are used, errors due to leakage

or incomplete settling are also inherent. In reference [12], these errors are reduced by using a

temperature-dependent clocking scheme. Hence, the sampling frequency is lower at lower

temperatures (to guarantee enough sampling time to the modulator) and higher at higher

temperatures (to reduce leakage-associated errors).

2.4. Conclusions

Different temperature sensing techniques and sensors were presented in this chapter. As a result of

these different implementations, different sensor accuracies and resolutions are obtained.

Highest accuracies are obtained in sensors [10], [11] and [12], with a maximum error of ±0.1ºC, ±0.2ºC

and ±0.25ºC (respectively) at the digital output. This is accomplished not only by using the previously

referred error reducing techniques, but also by calibration at one temperature. Batch calibration and

calibration based on ΔVBE measurement [4] are the two techniques used in these sensors. The sensor

presented in [9] requires 2-point calibration in order to achieve the mentioned accuracy of ±1ºC.

Multiple-point calibration requires, however, more time than 1-point calibration and is, therefore, more

expensive.

17

The resolution of each sensor depends directly on the implemented A/D converter. Highest resolutions

are obtained in [10] and [12]. These sensors present 2nd

order ΣΔ modulators and can achieve

resolutions of 0.002ºC and 0.025ºC (respectively). Sensors [9] and [11] achieve resolutions of 0.625ºC

and 0.03ºC introducing, thus, higher quantization errors. This, however, does not introduce significant

reading errors in [11] because the sensor’s resolution is approximately 7 times higher than its

accuracy. In [9] the quantization errors are not negligible because the sensor’s resolution is of the

same order of its accuracy.

Regarding power consumption, sensors [9] and [11] achieve lower values. The sensor presented in [9]

uses the power down facility to reduce the overall power consumption of the sensor.

18

Capítulo 3

3. Temperature Sensor

Design ____________________________________________________

19

In this chapter the design of an integrated smart temperature sensor is presented. Section 3.1

describes not only the overall topology of the sensor, but also each stage individually. Two possible

implementations of the first-order ΣΔ modulator are presented in Section 3.1.2. Here, the traditional

design of an integrator based on an OpAmp gain stage is compared to a proposed comparator-based

circuit technique. Section 3.2 presents the high-level model of the proposed circuit as well as its

design procedure.

3.1. Integrated Smart Temperature Sensor

The overall architecture of the implemented smart temperature sensor is shown in Figure 3.1.

Figure 3.1 - Integrated Smart Temperature Sensor architecture

The front-end consists of a circuit based on a bipolar junction, which produces at its output a PTAT

voltage difference. A first-order ΣΔ modulator performs the conversion of the input voltage into a

bitstream that, ideally, is unique for a given ΔVBE. The back-end counter finally converts each

bitstream into a digital value that represents the temperature at which the complete sensor is

operating.

3.1.1. Bipolar Junction Front-End

In this work the sensor front-end of the circuit is based on a single npn bipolar transistor, biased

alternately with two different bias currents. Therefore, two different VBE voltages are created and a

PTAT voltage (ΔVBE) is originated at the input of the ΣΔ modulator. Figure 3.2 illustrates the

implemented analog front-end of the proposed sensor.

20

Figure 3.2 - Sensor front-end used in the presented work

This voltage drop is, as in equation (2.6), given by

(3.1)

where p is the ratio between the two alternate biasing currents IC1 and IC2.

The current source on the right remains connected to the collector of the transistor. The current source

on the left is periodically switched on and off throughout the operation of the circuit. Thus, when the

current source on the left is turned off, the collector current is IC1 = I. When both current sources are

turned on, the collector current is given by

(3.2)

The use of a single BJT transistor eliminates errors due to process spread variations. Also, as the

current source with higher value is constantly switched on and off, there is no static current flow in one

of the biasing branches. This reduces significantly the overall power consumption of the circuit.

3.1.2. Sigma-Delta A/D Converter

Given the slow variation of temperature, a narrow bandwidth signal is presented at the npn output.

Thus, a low-speed, high resolution converter will match the requirements of a precise smart

temperature sensor.

In direct ADCs, such as flash ADCs, successive approximation ADCs, algorithmic ADCs or pipeline

ADCs, the range of the input signal is divided in multiple segments and the converter determines in

which of these segments the value of the input signal lies. The segmentation of the input range is

based on the matching of on-chip components, being the accuracy of this type of converters usually

21

limited to about 12 bits [13]. Given their characteristics, direct ADCs are more suitable for high speed,

low resolution conversion.

The ΣΔ ADC is included in the indirect type of ADC converters, which use intermediate steps to

determine its output. This type of ADC performs a conversion of the ratio between the input voltage

and the reference voltage into a time-domain ratio at its output. This output ratio is the fraction of ones

in a bitstream. The lower speed of this indirect converter due to its multiple step conversion results,

however, in an increase of resolution, matching the requirements above mentioned of a precise smart

temperature sensor.

Figure 3.3 shows the diagram of a first-order Sigma-Delta converter, along with the frontend that

provides the analog input.

VthVint Vth

bs 1

0

ΔVBE

1

0

bs 11

0ΔVBE

0

0

0

0

0

0

1

ΔVBE -VREF

ΔVBE

ΔVBE -VREF

ΔVBE

(a) (b)

Vdiff

Vint

Vdiff

Figure 3.3 - Waveforms in a 1st order ΣΔ ADC with different input voltages. (a) Lower ΔVBE. (b) Higher ΔVBE

The difference between the input, ΔVBE, and the modulator output, bs, is integrated. Given the slow

variation of temperature with time, it is fair to represent the output of the analog frontend, ΔVBE, as a

constant over an entire conversion period. Hence, Vint increases linearly, generating zeroes at the

modulator output bs, until it reaches the threshold voltage (Vth) defined in the comparator. The

comparator generates a one in the bitstream, which causes the modulator input to be subtracted by

VREF. This causes the voltage at the input of the integrator to become negative and Vint to decrease

linearly to its initial value. As ΔVBE increases (b), the positive slope of Vint is higher and the negative

slope is lower. This causes Vint to cross the threshold voltage more often and the number of ones in

the bitstream to increase. As the feedback of the modulator forces the output of the integrator back to

its initial value, the average accumulated charge in the integrator is approximately zero. This

guarantees the stability of the entire modulator. Given a total number of clock cycles, NTot, and the

number of cycles at which the bitstream is at the logic value “high”, N1, charge balancing implies that,

22

⇔

(3.3)

which shows that the fraction of ones in the bitstream is equal to the ratio between the input, ΔVBE and

the reference voltage, VREF. This produces a digital-to-analog conversion based on the ratio of ones in

a whole conversion period.

In order to implement the modulator, a switched-capacitor circuit is indicated, as it performs the

sample-and-hold functionality inherently at the integrator input. Given the very low frequency of the

input signal, ΔVBE, an anti-aliasing filter preceding the modulator is not required. Sections 3.1.2.a) and

3.1.2.b) present two possible designs of a ΣΔ modulator.

a) OpAmp-Based Modulator

A typical OpAmp-based switched-capacitor ΣΔ modulator is represented in Figure 3.4.

bs

VBE1,2

CI

VREF

CS

CFΦ1

Φ2

0 1

Vx Vo

VREF

VREF VREF

I(p-1).I

Φ2

DAC

I1 = I

I2 = p.I

Figure 3.4 - OpAmp-Based switched-capacitor ΣΔ Modulator

The collector of the bipolar junction transistor is connected to the sampling capacitor of the modulator.

In this topology, the ΣΔ modulator consists of an OpAmp working as an integrator followed by a latch

comparator. The output of the modulator, bs, is determined by the comparator and the feedback action

is performed by a 1-bit Digital-to-Analog Converter (DAC) which controls the voltage at the feedback

capacitor CF.

The modulator operates in two different phases, Φ1 and Φ2. During phase Φ1, the current I1 generates

the VBE1 voltage in the bipolar junction transistor. The charge, QS, in the sampling capacitor, CS, is

given by

(3.4)

During phase Φ2, the bipolar junction transistor is biased by I2, which creates a different base-emitter

voltage, VBE2. The charge in CS is now,

23

( ) (3.5)

This means that the charge difference in CS is PTAT, as determined in Eq. (3.1).

Assuming that the output of the DAC is VREF (bs = 0) the charge in CF is

(3.6)

This means that the voltage increment, at the output of the integrator will be given by,

(3.7)

On the other hand, if the DAC presents GND at its output (bs = 1), the charge in CF is no longer null,

(3.8)

In this case, the charge transfer to the output of the OpAmp creates a voltage difference given by

(3.9)

This feedback action forces the output voltage of the OpAmp to its initial value, which guarantees the

stability of the modulator, if the system is correctly sized.

The charge transfer from the input of the OpAmp to its output is promoted by the virtual ground

condition at its input node, Vx. As the voltage reaches Vref, the charge that was stored in CS is entirely

transferred onto CI. During the charge transfer the output voltage, Vo, settles exponentially to its

steady-state value as shown in Figure 3.5.

Figure 3.5 - Evolution of Vo during the charge transfer phase

The settling time of the system is determined by the time-constant of the circuit during the charge

transfer phase. The accuracy of the output depends on the accuracy of the OpAmp to force the virtual

ground condition during the charge transfer phase.

OpAmp-based modulators require high gain amplifiers to improve the accuracy of the system output

[17]. However, the tendency of CMOS technologies to reduce dimensions and power consumption

results on a reduction of the intrinsic device gain and signal swing. This affects the design of

operational amplifiers and, although different topologies and techniques have been developed to

contour these issues (multiple stage, cascoding, gain-boost), these designs also face several tradeoffs

(e.g. higher power consumption) and are not always simple to implement.

This thesis presents an alternative technique which replaces the OpAmp in the modulator by a circuit

based on a comparator and a current source. This technique will be explained in Section 3.1.2.b), as

well as its advantages over the use of an operational amplifier.

24

b) CBSC-Based Modulator

Figure 3.6 presents a ΣΔ modulator implemented with a single-ended comparator-based circuit (CBC).

VREF

CS

CF

VREF

Φ1

Φ2

0 1

bs

VREF

CI

VoVx

VREF

Io

Φ2p

DAC

VBE1,2

I(p-1).I

Φ2

I1 = I

I2 = p.I

Figure 3.6 - Comparator-Based switched-capacitor ΣΔ Modulator

The comparator-based circuit consists of a continuous-time comparator controlling a current source at

its output. This module replaces the operational amplifier on the modulator. The behavior of the circuit

during the sampling phase is the same as when using the OpAmp. Figure 3.7 illustrates its working

principle during phase Φ2, which will then be explained below.

VREF

Vo

Φ2

Φ2p

comp

Vx

VOF

Vx0

Figure 3.7 – Operation of the Comparator-Based Circuit

At the beginning of the charge-transfer phase Φ2, a short preset to the output voltage VO is performed.

This phase is identified with Φ2p, and lasts only long enough to set the output node of the comparator

to GND. This preset is performed to ensure that Vx, at the input of the comparator, is set below the

reference voltage VREF. When Φ2p ends, the output node is disconnected from GND and starts to be

charged linearly by the current IO. This voltage ramp is reflected in the input node Vx, through the

capacitor CI. Hence, VX also rises linearly due to the increase of charge on the output node. When Vx

crosses VREF, the comparator output turns to high, switching off the current source. This causes the

25

input and output nodes to maintain their current voltages Vx and VO, respectively. Assuming a

negligible comparator time response, the voltage VOF is defined by the capacitances used in the circuit

and the output voltage is the same as when using an OpAmp in the modulator.

The response time of the dynamic comparator causes a delay between the instant that Vx crosses

VREF and the instant when the current source is shut down. This leads to an error at the output node,

which does not settle exactly at VOF voltage. In references [15] and [16], a technique with a second

current source is used to lower VO and therefore compensate this overshoot effect. These circuits,

however, work at higher sampling frequencies (7,9MHz and 8MHz, respectively), which requires

higher output currents to ensure that the output VO settles at the correct voltage in due time. This

leads to a higher overshoot, and larger inaccuracy of the comparator-based circuit. A second current

source to minimize the error is essential in these cases.

Although this overshoot effect is unavoidable, in circuits working at lower frequencies, lower currents

can be used and still guarantee that the input voltage reaches VREF before the charge-transfer period

ends. A lower current generates slower slopes on both VO and Vx, which reduces the overshoot effect,

minimizing the voltage error due to the comparator delay.

In this comparator-based modulator design, the instant when the input node Vx crosses VREF is

detected by the comparator, instead of forcing the virtual ground condition (Vx = VREF) with an OpAmp.

As the output voltage is, in both designs, defined by the capacitances of the modulator, this

comparator-based circuit can be a more power efficient solution than the OpAmp. The dynamic

comparator is only turned on during a short period of the charge-transfer phase. This is the period

during which the output current source is also on (period between the start of Φ2 and the moment

when Vx crosses VREF). Hence, both the comparator and its output current source only dissipate power

during the time required, enhancing the power efficiency of the circuit.

3.1.3. Digital Block Back-End

At the back-end of the sensor, the digital block converts the output of the modulator into a digital word.

Given the first order of the ΣΔ modulator, the decimation block at its output can be implemented as a

digital counter, as referred before. The serial sequence of ones and zeroes that results from the ΣΔ

modulation is, then, converted into a parallel combination of ones and zeroes that represents the

digital word at the output of the smart temperature sensor. To perform such conversion, the

implementation of a binary synchronous counter is mandatory. This circuit will operate at a much

higher frequency than the modulator conversion rate. Figure 3.8 shows one possible design of this

type of counter using D flip flops and additional logic gates [14].

26

Figure 3.8 - A 4-bit digital synchronous binary counter

The back-end of the counter consists of positive-edge triggered flip flops, which guarantee the

synchronism and the sequential behavior of the circuit. The Carry Out output is implemented, so that

this 4-bit counter can be extended to any desired number of stages. The resolution of an n-bit ADC is

a function of how many parts the maximum signal can be divided into. For an n-bit resolution, the

circuit requires 2n sampling periods to perform one entire conversion. Therefore, the best achievable

resolution is 1 part out of 2n. Table 3.1 shows the number of clock periods and the total time required

to obtain different resolution conversions, at different sampling frequencies.

Resolution 10 bit 12 bit 16 bit 18 bit 19 bit

Sampling Periods

1024 4096 65536 262144 524288

Conversion Time (s)

Fs = 500kHz 2.048m 8.192m 131.072m 524.288m 1.049

Fs = 1MHz 1.024m 4.096m 65.536m 262.144m 524.288m

Table 3.1 – Sampling periods and conversion time for different resolutions and sampling frequencies

27

The different conversion times reflect that it is possible to perform temperature measurements with

sampling frequencies from 500 kHz up to 1MHz, with resolutions up to 19 bit. The longest time

(1.049s) is achieved when performing a 19 bit resolution conversion, at a sampling frequency of

500kHz, which is fairly acceptable in a temperature sensor. Theoretically, frequencies above 1 MHz

would reduce even more the conversion time, allowing an increase of the system resolution. However,

this would increase the dynamic power consumption on the switches, leading to larger errors and

difficulting the design of the modulator itself.

Although a converter operating at FS = 500 kHz presents acceptable conversion times, the lower

frequency leads to an increase of current leakage on the switches, which affects the linearity of the

converter. A frequency of 1 MHz reduces this effect.

A 12-bit converter achieves a maximum resolution of 0.024% of the full scale, which is higher than the

state-of-the-art sensors [5], [9] and [11].

Given these considerations, a 12-bit ADC at a frequency of 1 MHz promotes a good relation between

conversion time, resolution and power consumption.

The counter can be implemented by chaining three 4-bit counters to obtain a 12-bit binary word at its

output, as referred before. The counter in Figure 3.8 is designed with parallel gating. Thus, no

additional circuitry is required between each stage.

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q1

Q2

Q3

Q0

COC

EN

Counter-4

Q1

Q2

Q3

Q0

COC

EN

Counter-4

Q1

Q2

Q3

Q0

COC

EN

Counter-4

bs

clk

Figure 3.9 - A 12-bit synchronous binary counter

The counter is synchronized to a clock signal, which is the same clock to which the output of the ADC

is synchronized. This stage is the back-end of the entire smart temperature sensor, presenting the

digital word at its output.

28

3.2. Model Implementation

In this section, a model of the smart temperature sensor described in Section 3.1 is implemented with

ideal components. The objective of this model is to design a first approach to the presented topology,

validating it by simulation.

3.2.1. High-Level circuit

In the bipolar junction frontend, the biasing currents are implemented with two ideal current sources. In

order to create a relevant difference between the base-emitter voltages on the bipolar junction

transistor, a 300µA and a 10µA current source were used, resulting in a current ratio of 31:1. The

base-emitter voltage difference obtained at the temperature of 150ºC - considered the end-of-scale –

was ΔVBEmax = 134.85mV. This value represents the maximum input voltage of the ΣΔ modulator and

is, therefore, important for its correct dimensioning.

In order to build a stable modulator, a few constraints have to be taken in consideration. The

modulator saturates as the integrator voltage, VO, crosses VREF. In the next cycle, as referred in

Section 3.1.2.a), is forced to its initial value, due to the feedback system. Hence, the variation at the

integrator voltage, , must be negative,

(3.10)

This leads to the following equation:

⇔

(3.11)

This condition needs to be verified throughout the temperature range of the circuit. As ΔVBE increases

with temperature, at the limit of the sensor range equation (3.11) can be represented as,

(3.12)

Other constraint in the system is the reference voltage, which is limited by the supply voltage and

determines the saturation of the system. Thus, at the limit of the sensor range, this condition still

needs to be verified:

(3.13)

Table 3.2 presents the parameters used in this high-level model, obtained considering equations

(3.12) and (3.13).

CI (F) CF (F) CS (F) ΔVBE(150ºC) (V) VDD (V) VREF (V)

1p 1p 4.45p 134.85m 1.2 600m

Table 3.2 - High-level model parameters

29

The comparators, used in the CBC and at the backend of the modulator are implemented with an ideal

high gain voltage-controlled voltage source, a resistor and capacitance at its output, as shown in

Figure 3.10.

Figure 3.10 – Comparator implemented with high-level model

The results obtained using this high-level model, designed with ideal components are shown in the

next section.

3.2.2. Results

The results obtained with the implemented high level model are presented in this section. In Figure

3.11 a part of the transient simulation for the typical temperature of 27ºC is shown.

Figure 3.11 - High level transient simulation

As it can be observed, the modulator behaves as explained in Section b) and depicted in Figure 3.7.

The output node, VO, is set to ground during phase Φ2p. This is reflected in the input node of the

comparator through the capacitor CI, which causes VX to fall below VREF. As this preset phase ends,

VX and VO are charged by the current source until the moment that VX crosses VREF. The current

30

source is, then, shut down by the output of the comparator, which causes VO and VX to maintain their

values until the next integration cycle. The voltage VO is then compared to VREF by the output

comparator. As observed in the simulation above, the output of the modulator is set to “high” only if VO

is higher than VREF. The output of this comparator is the bitstream which represents the temperature at

which the modulator is operating.

To obtain a 12-bit resolution, a number of 4096 sampling periods is necessary, as explained in Table

3.1. A simple counter was implemented in Verilog-A to save the output data from the bitstream in each

simulation, and is described in Annex A. The number of “1”s recorded by this block in a simulation of

4096 periods (4.096ms at a frequency of 1MHz), represents the response of the modulator through an

entire conversion for a given temperature.

Simulations through the entire proposed temperature range (-55 to 150º) were performed. The results

are shown below.

Figure 3.12 - High level circuit output vs. Relative error

Ideally, the number of “1”s at the output of the modulator would increase linearly with the raising of

temperature. However the response of the system is not perfectly linear and this error must be

analyzed. In order to evaluate the system linearity, a simple linear regression was applied to the

simulation results. The obtained result is a linear function which estimates the ideal response of the

modulator. This function is not represented in Figure 3.12 for better reading comprehension. However,

31

the relative error between the results and the computed linear regression is represented in red. This

error is calculated by,

(3.14)

Analyzing Figure 3.12 it is possible to observe the non-linearity of the modulator response with

temperature (in blue). This non-linearity is calculated and limited to ±0.5%, over the entire temperature

range.

Other important factor that needs to be taken into account is the resolution achieved by this modulator.

The resolution represents the minimum variation at the modulator input that is reflected at its output. It

is given by,

(3.15)

where ΔT is the temperature variation and Δoutput is the respective variation of “1”s observed in the

output bitstream. The variation from -40ºC to 150ºC (ΔT=190ºC) promotes a variation from 2572 to

3976 “1s” at the output of the modulator. This represents a difference of Δoutput = 1404. The

resolution of this high-level model is, then,

3.3. Conclusions

In this chapter, the proposed topology of the smart temperature sensor was presented. A high-level

model was implemented to explain the working principle of this circuit and to validate the functioning of

this architecture.

It is possible to design a ΣΔ modulator using a comparator-based circuit, avoiding the use of an

OpAmp, which has static power consumption and requires elevated gain with low offset voltage [4].

The comparator and current source are easier to design and can include power-down inputs,

increasing the power efficiency of the sensor.

The high-level simulations show that an accurate smart sensor can be achieved using this

implementation, as the resolution obtained is 0.135ºC, with an error below ±0.5%.

32

Capítulo 4

4. Implementation in UMC

130nm Technology ____________________________________________________

33

In this chapter, the implementation of the proposed circuit in UMC 130nm technology is presented.

The circuit is based on an analog front-end creating the input voltage for the ΣΔ modulator, which is

implemented with a comparator-based circuit. The back-end of the circuit is a 12-bit binary counter,

presenting a temperature-dependent digital word at its output. From Section 4.1 through 4.8 each of

these blocks is explained and simulated individually. The layout of each block is shown in Section 4.9.

4.1. Bipolar Front-End

As referred in section 3.1.1 the analog front-end of the proposed circuit consists of a single bipolar

junction transistor biased alternately by two different currents. The implemented frontend is

represented in Figure 4.1 and requires two external biasing currents.

Figure 4.1 - Implemented analog sensor front-end

Different currents produce different base-emitter voltages. Simulations with different currents were

performed in order to analyze not only the sensor linearity with temperature, but also its power

consumption. The results with different external biasing currents are presented in Figure 4.2.

34

Figure 4.2 – VBE variation with different biasing currents

Higher currents produce higher base-emitter voltages. However, these voltages are not linear with

temperature, as referred in Eq. (2.4). Figure 4.3 shows the variation of ΔVBE = VBE2 - VBE1 with

temperature for each case presented above.

Figure 4.3 - ΔVBE variation with different biasing currents

The current ratio of 31:1 is maintained in the three cases presented. In order to evaluate the linearity

of ΔVBE with temperature, the error between each voltage and its respective linear regression was

calculated. A lower error represents a higher linearity, which is the main objective when creating a

PTAT voltage at the output of this stage. In Figure 4.4 the obtained errors are shown.

35

Figure 4.4 - ΔVBE and respective relative error with different biasing currents

Higher currents create lower ΔVBE voltages, as can be seen in Figure 4.3. In the remaining tests, with

62:2µA and 31:1µA, similar ΔVBE voltages are obtained, slightly 10mV higher. Analyzing Figure 4.4,

ΔVBE voltages obtained with 62:2µA and 31:1µA present a similar, and clearly more linear, variation

with temperature. The errors achieved facing the linear regression are below ±0.2%, while in the test

with 310:10µA errors between -1% and +2% are obtained.

One other important factor of this stage is its contribution to the overall power consumption of the

smart temperature sensor. The estimated current consumption of this block is given by

Hence, if IC1=1µA and IC2 = 31µA, the average current consumption of this block will be

The results obtained for this block indicate that the lower biasing currents are the best choice to create

a linear PTAT voltage, which is also an advantage towards the low power consumption of the circuit.

Hence, the relation of 31:1µA was chosen to implement the biasing of the analog sensor frontend.

Table 4.1 presents the dimensions used for the frontend PMOS current mirrors.

M1, M2, M3, M4 M5

Width [m] 5µ 20µ

Length [m] 1 µ

Table 4.1 – Frontend transistor sizing

36

4.2. Comparator-based Circuit

The comparator-based circuit which, in this work, replaces the use of an OpAmp is based on a

continuous-time comparator and a current source, as described in Section 3.1.2.b).

4.2.1. Comparator

The schematic of the dynamic comparator used in this work is shown in Figure 4.5.

Figure 4.5 – Comparator with positive feedback [18]

This comparator is based on two NMOS transistors (M1 and M2) working as a pre-amplifier and a

positive feedback PMOS circuit. Transistor M3 works as a latch, switching off the comparator during

the sampling phase in order to reduce power consumption. The comparator sizing, optimized by

simulation, is presented in Table 4.2.

Pre-amp Latch Feedback

Width [m] M1, M2 M3 M4, M5 M6, M7

10µ 5µ 5µ 1µ

Length [m] 120n

Table 4.2 – Comparator parameters

Given the sensitivity of this circuit to parasitic charges, minimum length transistors are used at the

input stage as well as on the feedback circuit to minimize parasitic capacitances. To obtain an

accurate result, symmetry and transistor matching here are mandatory.

37

In order to amplify the output signal of the comparator to a rail-to-rail signal a sequence of buffers is

connected to the output of the comparator, as shown in Figure 4.6.

Figure 4.6 – Delay equalizer block [18]

This circuit consists of two branches of CMOS inverters. One of the branches consists of three inverter

stages, thus inverting the input signal. The branch represented on the bottom works as a buffer, as it

is composed by two inverters. Inverters I6 and I7 force the nodes N1 and N2 to have opposite logical

values, equalizing the two outputs of the comparator. The first stage inverters have smaller

dimensions than the following stages, in order to minimize the capacitance at the comparator output.

Although the channel length is set to the minimum in all transistors (to minimize the overall

propagation delay), the channel width is increased in each stage to improve the load driving

performance throughout the buffer. Table 4.3 shows the parameters used in the referred block.

Stage 1 Stage 2, I6, I7 Stage 3

Width [m] PMOS 3µ 6µ 12µ

NMOS 1µ 2µ 4µ

Length [m] 120n

Table 4.3 – Transistor dimensions used in the delay equalizer block

Figure 4.7 shows the output of the implemented delay equalizer, when an ideal pulse is presented at

its input.

38

Figure 4.7 – Delay equalizer input (red) and respective outputs

As shown in the simulation results, the obtained propagation delay reaches a value of 91.6ps which is

small, given the frequency at which the modulator will operate.

Given the load that the equalizer block produces at one of the outputs of the comparator, a dummy

circuit needs to be connected to the other output. This circuit is shown in Figure 4.8.

Figure 4.8 – Load Balance Circuit

In order to equalize the balance at the two comparator outputs, both PMOS and NMOS dummy

transistors have the same size as the Stage 1 inverters of the delay equalizer block.

To simulate the response of the entire comparator block, a constant reference input is presented at

the Vin,n input of the comparator. An increasing voltage is connected at Vin,p input. As the comparator

will only be turned on during the charge transfer phase, this testbench simulates the conditions under

which the comparator will operate in the modulator.

39

Figure 4.9 – CBSC comparator response

The simulation shown in Figure 4.9 shows the response of the comparator block. As Vin,p crosses the

reference voltage of 600mV, the output Vout,p rises to the logic value “high” as Vout,n falls

simultaneously to “low”. With the circuit sizing shown in Table 4.2 and Table 4.3, a response delay of

8,88ns was achieved. The output comp_out_n of the dynamic comparator will control the current

source, as will be described in the next section.

4.2.2. Current Source

A current mirror, controlled by the output of the comparator is shown in Figure 4.10.

Figure 4.10 – PMOS Current mirror with Power Down input

An external current source of 10μA is used to set the integration current during the charge-transfer

phase. The current mirror is implemented by M1 and M2, which are turned on and off by transistor MPD.

40

This power-down transistor is connected to the output of the comparator block, so that the current

source is shut-down when Vin,p crosses VREF. All transistors use a channel length of 1μm and channel

width of 5μm.

As described in Section 3.1.2.b), to ensure that VX – at the input of the comparator – starts below VREF,

the output node, VO, is preset to “ground” at the beginning of phase Φ2. To avoid the implementation

of an extra phase (represented as Φ2P in Figure 3.7), a quasi-floating-gate circuit was designed to

control the Pull-Down switch. This circuit is depicted in Figure 4.11.

Figure 4.11 - Pull-Down switch control circuit

The gate of the switch is coupled to Φ2 through the capacitor CGate, so that the signal is transferred to

its quasi-floating-gate. As the purpose of this NMOS switch is to connect the output node to ground

during a short period of time, VGate is connected to GND through resistor R. Hence, in a steady-state

condition, the switch is in the cuttoff region. If the CGate capacitance is well dimensioned, as Φ2 rises

from “low” to “high”, VGate reaches a voltage that is higher than the NMOS VTH, turning the pull-down

switch on. After the transition, Φ2 remains constant for half a period – steady-state - and the gate node

discharges, bringing the NMOS switch back to cuttoff. At this time the output node starts to charge

linearly by the current source.

The capacitor is dimensioned so that VGate reaches a value higher than the switch threshold, VTH. The

resistor R value is sized to adjust the CR time-constant of the gate circuit. This time constant needs to

be high enough to grant that the switch is on for long enough to pull the output node to zero. Table 4.4

presents the threshold voltage of the switch (obtained by simulation) and the values used for the

capacitor and resistor used in this block.

41

VTH (Typical) [V] CGate [F] RGate [Ω] Time constant [s]

605m 675f 44.45k 30n

Table 4.4 - Pull-Down control circuit characteristics

These values were adjusted by simulation, to reach the desired behavior of the NMOS switch. These

results are shown in Figure 4.12.

Figure 4.12 - VO pull-down simulation

As can be observed in the figure above, as phase Φ2 rises, the charge injected in the capacitor CGate

boosts the voltage at the node VGate to 1.1V which turns on the NMOS switch. The output node is then

reset to GND, by the current flowing from the current mirror. As VGate falls below the threshold voltage,

the switch re-enters the cuttof region and VO is disconnected from ground, being then charged by IOUT.

This method eliminates the need of a dedicated extra phase (Φ2d) for this purpose, simplifying the

control implementation of the modulator.

The simulation below shows the results obtained for this entire block composed by the dynamic

comparator, current mirror and the output reset circuit.

42

Figure 4.13 - Current source controlled by the dynamic comparator

As shown in Figure 4.13, after VO is preset to ground, the current IOUT starts charging the output node.

This is reflected at the input node of the dynamic comparator through CI. When VX reaches VREF, the

comparator shuts down the current mirror (via its power-down transistor) and VO holds its value. Due

to the delay of 8.88ns between the comparator decision and the moment that current mirror is

disabled, an extra charge is accumulated in the capacitor. This charge is reflected in the settling

voltage of the output node. However, as this delay is minimal comparing to the frequency of 1 MHz at

which the modulator operates, this should not have major impact on the accuracy of the modulator.

4.3. Latch Comparator

As shown in section 3.1.2.b), another comparator block is placed at the output of the ΣΔ modulator.

The goal of this comparator is to decide whether the output of the integrator is higher than VREF after

each integration. Figure 4.14 illustrates the implemented latch comparator.

43

Figure 4.14 – Latch Comparator

While the comparator used in the comparator-based integrator operates dynamically – its output

varies during the time the comparator is on -, this circuit compares the inputs at the instant that the

Latch input is set to “1”.

Transistors M5 to M9 work as a startup circuit, setting equal initial conditions for both comparator

branches. When the Latch input is set to “low”, these PMOS transistors pull the comparator nodes to

VDD. Also, MLatch is off, cutting the current flow through the comparator. This minimizes power

consumption, as the comparator is only turned on during phase Φ1. As Latch is set to “high”, the

startup transistors disconnect the nodes from VDD and MLatch conducts, turning the comparator on.

To better simulate the operation of this latch comparator, a reference voltage of 600mV was

connected to Vin,N and a triangular waveform 0 to 1.2V was connected to Vin,P. This triangular

waveform simulates the integration determined by the comparator and current source. The Latch input

is connected to a 1 MHz clock.

44

Figure 4.15 – Latch comparator testbench simulation

As can be observed in Figure 4.15, the output of the comparator is set to “high” whenever Vin,P (red) is

greater than Vin,N (green). Hence, this comparator can be used to set the output of the integration.

All transistors used in this block are implemented with minimum channel length (120nm) and a width

of 1µm. This comparator, however, has the disadvantage that its output is only valid when the

comparator is on. As the Latch input is set to “low”, the comparator is disabled and Vout,N is connected

to GND. To eliminate this problem, a flip-flop is required at the comparator output.

4.4. D Flip-Flop

Figure 4.16 shows the implemented topology of the D Flip-Flop, used to hold the logic value at the

output of the comparator during a full clock cycle.

Figure 4.16 – Positive edge-triggered D Flip-Flop

45

The presented circuit implements a positive edge-triggered D flip-flop. This block ignores variations at

its D input while working at a constant level and triggers only during the rising edge of the clock input

signal. To simulate the environment in which the flip-flop will operate, a clock input with a frequency of

1 MHz is used. A pulse generator with a higher frequency is set at the D input to simulate variations at

the input of the flip-flop. Figure 4.17 illustrates the simulation results obtained with the described

testbench.

Figure 4.17 - D Flip-Flop Logic Simulation

As can be observed in the simulation, the Q output of the flip-flop assumes the D input logic value as

the rising edge of the clock input occurs. That value is, then, preserved until the next clock rising edge.

Thus, the use of this D flip-flop at the output of the comparator promotes circuit synchronism,

eliminating the dependence of comparator’s output on its Latch input.

The flip-flop was designed with minimum channel length and short channel width to minimize and

power consumption, as described in Table 4.5.

Length [m] WidthNMOS [m] WidthPMOS [m]

120n 160n 480n

Table 4.5 – Flip-Flop D dimensions

4.5. Switches

There are three types of switches implemented in the presented circuit. For increased performance,

NMOS switches were used to connect nodes to GND (Pull-Down) and PMOS switches to implement

46

connections to VDD (Pull-Up). Connections to intermediate voltages (e.g. VREF) were implemented with

CMOS transmission gates in order to decrease the effective resistance when the switch is conducting.

As the accuracy of the switched-capacitor modulator depends on the effectiveness of the charge

transfer in the integration, charge injection in the switches is an effect which needs to be minimized.

Two important parasitic capacitances have to be taken in consideration – the Gate-Source (CGS) and

the Gate-Drain (CGD) capacitances. As the input signal of the switch rises from low to high, two

undesired parasitic currents flow through CGS and CGD, injecting undesired charge on both source and

gate of the switch. To compensate this effect, two dummy transistors are introduced at the input and

output of the switch, as shown in Figure 4.18.

Figure 4.18 - NMOS switch

The source of each dummy transistor is connected to its drain. The transistors are, then, in the cuttof

region having no impact on the operation of the switch. However, each dummy transistor introduces

two extra capacities (CGS and CGD). As the gates of these transistors are connected to a

complementary phase, a current will flow in the opposite direction through the capacitances of the

dummy transistors. In order for these currents compensate the current injected by the main transistor,

the following conditions must be granted,

(4.1)

(4.2)

As the capacitance is proportional to the area of the transistor, each dummy transistor must have half

the size of the main switch transistor. This ensures that the current injected in the drain of M1 is

absorbed in transistor Dummy1 and the current injected in the source of M1 is absorbed in transistor

Dummy2. The simulation presented in Figure 4.19 illustrates the difference between a simple NMOS

switch and an NMOS switch implemented with dummy transistors.

47

Figure 4.19 - NMOS switch simulation

The waves in blue represent the currents injected at the terminals of the switch using dummy

transistors. The waves in red represent the same currents injected in a simple NMOS switch.

Comparing both situations, not only a decrease of the maximum current is noticed, but also a

discharge in the opposite direction can be observed. This means that the currents flowing through the

dummy transistors compensate the current injected through the main transistor, eliminating undesired

charge at the terminals of the switch. Figure 4.20 shows the PMOS Pull-Up switch implementation,

using the same technique.

Figure 4.20 - PMOS switch

The CMOS implementation of the transmission gate is depicted in Figure 4.21.

48

Figure 4.21 - CMOS switch

As this switch consists of a NMOS and a PMOS transistor, dummy transistors of both types are used

to compensate the charge injection effect.

4.6. 1-bit D/A Converter

As explained in section 3.1.2.b), the feedback circuit of this first order ΣΔ modulator consists of a 1-bit

digital-to-analog converter. The feedback promotes system stability, as it provides information at the

input about the output state of the modulator. As depicted in

Figure 3.3, the feedback circuit subtracts VREF from the input every time VOUT reaches the reference

voltage. This subtraction is performed during phase Φ1 and is implemented through CF which is

discharged to ground when VOUT is high. The connection to ground is performed by an NMOS switch

and the connection to the reference voltage is performed by a CMOS switch. The switches are

controlled by a NAND gate connected to a delay equalizer block, as shown in Figure 4.22.

Figure 4.22 - Implemented 1-bit D/A Converter

The simulation results of this block are demonstrated in Figure 4.23. As can be observed, when both

VOUT and Φ1 are high, the feedback node is connected to ground. The charge accumulated in CF is

then discharged, resetting the input node to its initial state and stabilizing the modulator.

49

Figure 4.23 - 1-bit DAC simulation

The dimensions of the NAND gate and switches used in this block are presented in Table 4.6.

NAND SwitchCMOS SwitchNMOS

Width [m] PMOS 15µ 90µ -

NMOS 5µ 30µ 30µ

Length [m] 240n 120n

Table 4.6 - Transistor Sizing of the 1-bit DAC

4.7. 12-bit Binary Counter

The backend of the presented circuit consists of a 12-bit binary counter, to convert the bitstream into a

final digital word. This block consists of three 4-bit binary counters connected in series, as depicted in

Figure 3.9. The implemented topology for each 4-bit counter is shown in Figure 3.8. All transistors

used to implement this counter use minimum channel length of 120nm. The NMOS transistors use a

channel width of 160nm and the PMOS transistors a 480nm width. The obtained results are presented

in Figure 4.24.

50

Figure 4.24 - 12-bit binary counter simulation

This simulation shows the transient response of the counter during an entire conversion period of

4.096ms. The clock frequency is set to 1 MHz. The Enable input is set to high, so that in each clock

cycle the counter is increased by one. This represents the situation where the output of the modulator

would be always at logical value “1” (which should not happen). However, for simulation purposes, this

demonstrates that this binary counter block is working properly, incrementing the output digital word in

each clock cycle.

4.8. Multi-Phase Generator

The implemented non-overlapping phase generator is depicted in Figure 4.25.

Figure 4.25 – Multi-Phase Generator

This block is based on a typical non-overlapping phase generator followed by two delay equalizer

circuits. This delay equalizer circuit is re-used in this block, in order to create two additional non-

overlapping phases (Φ1,N and Φ2,N), required for an effective control of the switched capacitor circuit.

An ideal square wave generator with a frequency of 1 MHz was used to simulate an external clock

input of the circuit. The results obtained are shown in Figure 4.26.

51

Figure 4.26 – Non-overlapping outputs of the phase generator block

Above are represented all four phases that are used to control the switched capacitor circuit. As can

be observed, Φ1 and Φ2 are non-overlapping, as Φ1 rises only after Φ1 is set to GND. Given the fact

that each switch used in this circuit includes dummy transistors to compensate charge injection,

complementary phases are needed to control these components. Hence Φ1,N actuates on the switches

controlled by Φ1 and Φ2,N actuates on the ones controlled by Φ2. The dimensions of the components

in this block are presented in Table 4.7.

I1, I2, I3, NAND1, NAND2 I4, I5

Width [m] PMOS 3µ 3µ

NMOS 1µ 1µ

Length [m] 240n 360n

Table 4.7 - Multi-phase Generator dimensions

4.9. Layout

The layout design is the final step of the circuit implementation. As the die manufacturing process is

not ideal, there are several techniques used to minimize the influence of these manufacturing process

variations. Also, the designed layout can affect the response of the circuit by itself. This has high

importance given the fact that the switched-capacitor circuit operation is based on charge transfer

between several nodes of the circuit. Thus, it is sensitive not only to parasitic charges but also to

current leakage which may occur through parasitic inductances. Resistance between the circuit nodes

52

can be reduced and good connectivity can be ensured using wide metal paths and multiple contacts

connecting different metal layers. Finally, and to ensure good biasing, contacts to the substrate are

placed wherever possible. The layout of the circuit developed in this work is shown in Figure 4.27 and

occupies a die area of 155μm x 55μm = 0.009mm2

Figure 4.27 - Layout of the temperature sensor

53

Capítulo 5

5. Simulation Results ____________________________________________________

54

5.1. Introduction

In this chapter, simulations of the implemented smart temperature sensor are presented and analyzed.

The chapter is divided in three sections. In section 5.2, the full sensor results are discussed. In Section

5.3 the performance of the ΣΔ modulator alone is analyzed. Section 5.4 analyzes the sensor

resolution and, in Section 5.5, results regarding power consumption of the circuit are presented.

5.2. Simulations of the complete sensor

In order to analyze the performance of the smart temperature sensor, a linear regression was applied

to the results obtained over the proposed temperature range. Hence, it is possible to evaluate how

linear the output of the sensor is when submitted to a linear variation in temperature.

Figure 5.1 - Full sensor output (blue) vs. Relative error (red)

In order to easily represent the results of the temperature sensor, Figure 5.1 shows the number of 1s

at the output bitstream of the ΣΔ modulator in one conversion period. This number is more readable

than the digital word, which is the final output of the smart temperature sensor developed. The error

relative to the linear regression applied is calculated through Equation 3.14 and, as can be observed,

there is a non-linearity of the overall sensor throughout the temperature range. The source of this error

will be explained in Section 5.3.

55

5.3. Simulations of the ΣΔ-ADC

To analyze the source of the sensor non-linearity, the ΣΔ-Analog-to-Digital converter is characterized

separately from the analog BJT frontend. Therefore, for the following simulation, the frontend was

replaced by an ideal voltage source, which simulates ΔVBE at the input of the ADC. The results are

presented in Figure 5.2.

Figure 5.2 – ΣΔ ADC response to linear input (blue) vs. Relative error (red)

The voltage range of the input is the same as the ΔVBE created by the real BJT frontend, in order to

simulate the temperature range from -55 to 150ºC. The relative error of the ADC is below ±0.06%,

showing that the non-linearity of the converter is smaller than the one verified in Figure 5.1. This

means that the source of the complete temperature sensor non-linearity comes mostly from the bipolar

frontend and not from the ΣΔ ADC itself.

Although the sensor frontend presents a non-linearity below 0.2%, the abrupt current switching at the

converter input affects directly the precision of the sensor, as it increases the noise at the input of the

ΣΔ modulator. Figure 5.3 illustrates the current at the BJT collector, for a temperature of 27ºC.

56

Figure 5.3 – Current switching at the sensor frontend: VBE (red); Biasing current (Blue)

As can be observed, when the 30µA current mirror is turned off, a peak of 2.8mA is noticed. When the

same current mirror is turned on, a peak of 1mA is also observed. This causes undesired charge

injection into the input capacitor, CS, causing measurement errors in the temperature sensor.

5.4. System Resolution

The system resolution determines how sensitive the sensor is to temperature variations. It is

calculated using Equation (3.15), with the temperature range and the respective output of the sensor.

Performing two consecutive simulations with a temperature variation of 0.22ºC, it is obtained the same

result at the sensor output. This means that the ΣΔ ADC does not have enough resolution to such

small variation at its input. However, variations higher than 0.23ºC are reflected at the output of the

converter. This confirms by simulation the resolution obtained above for the implemented temperature

sensor.

5.5. Power consumption simulations

The power consumption of a smart temperature sensor (as for most integrated circuits) is one of the

most important factors to take into account. Not only due to power per conversion itself, but also (in

temperature sensors particular case) due to circuit self-heating. The goal is to reduce system self-

heating in order to be able to accurately measure temperature.

57

As the sensor operates in a wide temperature range, it makes sense to present the respective power

consumption for the minimum (-55ºC), typical (27ºC) and maximum (150ºC) operating temperature.

Table 5.1 shows the power consumption of each block separately, as well as the overall power

consumption of the implemented sensor.

Current consumption [A]

Min Typ Max

Phase Generator 2.52µ 2.86µ 8.16µ

Bipolar Frontend 15.62µ 15.95µ 16.04µ

CBC Comparator 79.01µ 80.51µ 84.98µ

CBC Current Source 11.22µ 11.26µ 11.41µ

Delay equalizer Blocks (x5) 1.717µ 2.32µ 10.09µ

Output Latch Comparator 37.34n 54.05n 377.2n

Switches 413.3p 1.25n 3.8n

D Flip-Flop 30.75n 43.17n 143.7n

Additional Logic 1.44n 1.771n 3.25n

12-bit Binary Counter 367n 479.2n 1.02µ

Total 112.1µ 114.9µ 135.7µ

Table 5.1- Power consumption measurements

Analyzing these measurements, it can be noticed an increase in current consumption with

temperature. The blocks that most contribute for this discrepancy are the five delay equalizer blocks

used in the circuit and the comparator used in the comparator-based circuit. The sensor power

consumption varies, thus, from 112.1µA to a maximum of 135.7µA with a 1.2V supply voltage.

5.6. Conclusions

In the present chapter the results obtained for the implemented temperature sensor were presented.

Applying a linear regression to the results obtained for the smart temperature sensor, it is noticed a

slight non-linearity between +2% and -1.5%. However, this non-linearity is not noticed when submitting

the ΣΔ ADC to the same temperature conditions, but with a linear input voltage instead of the bipolar

frontend. The abrupt transition noticed when the current switching occurs causes undesired charge

injection at the input of the analog-to-digital converter.

Testing the ΣΔ ADC alone, the non-linearity is reduced to ±0.06%, relative to the same linear

regression analysis method. This result confirms that the non-linearity of the system is originated by

the analog frontend and reflects the consistency of this proposed comparator-based ΣΔ modulator

topology. The obtained resolution for the sensor is 0.23ºC, which means that variations inferior to that

58

value are unnoticed by the sensor. The 12-bit resolution requires a conversion time of 4.096ms and

consumes a minimum of 112.1µA at -55ºC and a maximum of 135.7µA, which occurs when the

system is operating at 150ºC.

59

Capítulo 6

6. Conclusion and Future

Work ____________________________________________________

60

6.1. Conclusion

The objective of this work was to design a low power smart temperature sensor using a comparator-

based ΣΔ modulator, in 130nm CMOS technology.

A study of the state-of-the-art temperature sensors was performed, in order to understand the

advantages of each type of sensor and the impact that each topology has on power consumption,

accuracy and resolution.

A PTAT circuit was developed and implemented in 130nm CMOS technology. This sensor produces a

proportional-to-absolute-temperature voltage at its output and can work as an analog frontend for a

smart temperature sensor. It presents, however, a non-linearity of ±1.5% which prevents it to be used

as an analog frontend for this work. A different circuit, using a single BJT biased by two different

currents is implemented in order to obtain a higher precision sensor frontend. This circuit has the

advantage of reducing power consumption and errors due to manufacturing process variations. Its

non-linearity is below 0.2%, representing a substantial improvement comparing to the previous circuit.

Regarding the overall smart temperature sensor, a study about the proposed topology was performed

on Chapter 3. The comparator-based circuit working principle as an integrator is explained and

integrated on a high-level model of the smart temperature sensor. The objective is to present and

validate the circuit model before implementing it. Based on the results obtained for the high-level

model, the circuit was designed accordingly, in order to obtain good results in terms of resolution,

power consumption and accuracy.

The sensor operates in a scale range from -55 to 150ºC. As in any analog-to-digital converter, the

design of the ΣΔ ADC was performed based on the maximum input voltage temperature at which the

sensor can operate. This establishes the maximum value of the sensor temperature range. The lower

limit of the implemented sensor is defined due to a strong non-linearity at the output of the sensor

below that temperature. Analyzing Table 1.1 in Section 1.2, this obtained range is wider than the

military range. The temperature range objective established at the beginning of this work has been

well achieved.

The obtained resolution for this sensor is 0.23ºC. A non-linearity of +2% to -1.5% is noticed throughout

the temperature range. This non-linearity is originated due to undesired charge injection at the input of

the ADC and affects directly the sensors’ accuracy, hence limiting the variety of applications in which it

can be used. For high precision applications, where good performance is mandatory, a sensor with

improved accuracy is required.

61

Although the achieved accuracy of the implemented smart temperature sensor was below expected,

nowadays power consumption may have the same importance as accuracy. In some cases, like

battery supplied applications or autonomous systems, more importance at all. The implemented

sensor consumes typically 114.9μA in a 4.046ms conversion time. Given the fact that temperature is

considered a very low frequency input, this smart temperature sensor can be integrated on such types

of applications as long as it is not constantly operating and elevated accuracy is not required.

The introduced technique of implementing a ΣΔ analog-to-digital converter using a comparator-based

circuit presents several advantages when compared to the typical OpAmp-based topology. The typical

offset error present in circuits using operational amplifiers usually requires offset compensation

techniques. Avoiding the implementation of an OpAmp the design of the modulator is simplified and no

offset compensation circuit is required. The low operating frequency of the modulator, 1MHz,

guarantees that the error introduced by the comparator delay is minimal. Also, the latch controlled

dynamic comparator is only switched on during the necessary period of time, presenting no static

power consumption. These advantages contribute to a low power ΣΔ ADC with high linearity and

resolution.

Based on the results obtained and presented in this thesis, it is possible to conclude that the

implementation of a smart temperature sensor in 130nm technology has been successfully achieved

presenting, nevertheless, some performance limitations.

6.2. Future Work

Regarding the analog frontend, an improved current generator should be studied. The frontend

implemented in this work is based on simple current mirrors, which prove to be unsuitable for an

accurate input to the ΣΔ ADC. The current switching causes undesired charge injection, originating a

non-linearity of the overall circuit.

Also, this circuit depends on external current sources and biasing voltage, VREF. Accurate current

sources should be implemented to bias not only the sensor frontend, but also the comparator-based

circuit. A temperature-independent voltage should be implemented using a CMOS bandgap reference

voltage.

A power-down system was not implemented. Because there is the need to enable and disable this

circuit externally (e.g. by CPU control), a power-down circuit should be designed and integrated in this

sensor.

62

Annexes

____________________________________________________

63

Annex A – Verilog-A implementation for the bitstream data counter

64

Annex B - High-Level Circuit

65

Annex C - Sensor Frontend

Annex D - Multi-Phase Generator

Annex E - Delay Equalizer Block

66

Annex F- Dynamic CBC Comparator with positive feedback

Annex G - CBC Comparator Load Balance

Annex H - CBC Current Mirror

67

Annex I - 1-Bit DAC

Annex J - Output Latch Comparator

68

Annex K - Output D Flip-Flop

Annex L - 4-Bit Binary Counter

69

Annex M - 12-Bit Binary Counter

Annex N - NMOS Switch with dummy transistors

Annex O - PMOS Switch with dummy transistors

Annex P - CMOS Switch with dummy transistors

70

Annex Q - Complete Temperature Sensor Schematic

71

References

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72

[1] K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems.

Singapore: McGraw-Hill, 1994

[2] A.S. Sedra and K.C. Smith, Microelectronic Circuits, 5th ed., New York: Oxford University

Press, 2004

[3] R.J. Baker, CMOS Circuit Design Layout and Simulation - 2nd Edition, Wiley-IEEE, 2004,

p.625

[4] M.A.P.Pertijs and J.H. Huijsing, Precision Temperature Sensors in CMOS Technology,

Springer, 2006

[5] Kyoungho Woo; Meninger, S.; Xanthopoulos, T.; Crain, E.; Dongwan Ha; Donhee Ham; ,

"Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring," Solid-

State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International , vol.,

no., pp.68-69,69a, 8-12 Feb. 2009

[6] Poki Chen; Chun-Chi Chen; Yu-Han Peng; Kai-Ming Wang; Yu-Shin Wang; , "A Time-Domain

SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of −0.4°C ∼

+0.6°C Over a 0°C to 90°C Range," Solid-State Circuits, IEEE Journal of , vol.45, no.3, pp.600-609,

March 2010

[7] H.P. Hsu, Analog and Digital Communications – 2nd Edition, McGraw-Hill, 2003

[8] “TMP data sheet,” Analog Devices, Inc., Nov. 2010, www.analog.com

[9] Bakker, A.; Huijsing, J.H.; , "Micropower CMOS temperature sensor with digital output," Solid-

State Circuits, IEEE Journal of , vol.31, no.7, pp.933-937, Jul 1996

[10] Pertijs, M.A.P.; Makinwa, K.A.A.; Huijsing, J.H.; , "A CMOS smart temperature sensor with a

3σ inaccuracy of ±0.1°C from -55°C to 125°C," Solid-State Circuits, IEEE Journal of , vol.40, no.12,

pp. 2805- 2815, Dec. 2005

[11] Sebastiano, F.; Breems, L.J.; Makinwa, K.A.A.; Drago, S.; Leenaerts, D.M.W.; Nauta, B.; , "A

1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from

−70°C to 125°C," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE

International , vol., no., pp.312-313, 7-11 Feb. 2010

[12] Aita, A.L.; Pertijs, M.; Makinwa, K.; Huijsing, J.H.; , "A CMOS smart temperature sensor with a

batch-calibrated inaccuracy of ±0.25°C (3σ) from −70°C to 130°C," Solid-State Circuits Conference -

Digest of Technical Papers, 2009. ISSCC 2009. IEEE International , vol., no., pp.342-343,343a, 8-12

Feb. 2009

[13] van de Plassche, R.J., CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,

2nd

Ed., Boston: Kluwer Academic Publishers, 2003

[14] Mano, M.M.; Kime, C.R.; Logic And Computer Design Fundamentals, 3rd

Ed., New Jersey:

Prentice Hall, 2004

[15] Sepke, T.; Fiorenza, J.K.; Sodini, C.G.; Holloway, P.; Lee, H.-S.; , “Comparator-based

switched-capacitor circuits for scaled CMOS technologies”, Proc. IEEE Int. Solid-State Circuits

Conference, pp. 220–221, 2006

[16] Momeni, M.; Prelog, D.; Horvat, B.; Glesner, M.; “Comparator-Based Switched-Capacitor

Delta-Sigma Modulation”, Contemporary Engineering Sciences Vol. 1, no.1, pp. 1-13, 2008

73

[17] Momeni, M.; Prelog, D.; Horvat, B.; Glesner, M.; “Cascade delta-sigma modulator with

pseudo-differential comparator-based switched-capacitor gain stage”, Analog Integrated Circuits and

Signal Processing, pp. 51:201-206, 2007

[18] Martins, M. A.; Un, K.F.; Mak, P.I.; Martins, R.P.; “SC Biquad Filter with Hybrid Utilization of

OpAmp and Comparator-Based Circuit”, Circuits and Systems (ISCAS), Proceedings of 2010 IEEE

International Symposium on, vol., no., pp. 1276, 1279, May 30 2010 - June 2 2010