TEF 2021: The Road Ahead Next Generation Optical Interfaces

Ethernet Alliance

TEF 2021: The Road Ahead

Next Generation Optical Interfaces

2

The Ethernet AllianceGlobal Community of End Users, System Vendors, Component Suppliers & Academia

Our Mission

• To promote industry awareness, acceptance and

advancement of technology and products based on, or

dependent upon, both existing and emerging IEEE 802

Ethernet standards and their management.

• To accelerate industry adoption and remove barriers to

market entry by providing a cohesive, market-responsive,

industry voice.

• Provide resources to establish and demonstrate multi-

vendor interoperability.

Ethernet Alliance Strategy

3

● Facilitate interoperability testing

○ Industry Plug Fests supporting

member and technology initiatives

● Interoperability Assurance

○ PoE Certification Program

● Collaborative Interaction with

other Industry Organizations

○ Multiple SIGs, Applications and MSAs

○ Industry Consensus Building

● Global Outreach

○ Worldwide Membership

●Thought Leadership

○ EA Hosts Technology Exploration

Forums (TEFs)

○ Technology and Standards

incubation

●Promotion of Ethernet

○ Industry Analysts

○ Education

○ Marketing

■Trade shows & Panel Presentations

■White Papers, Blogs & Social Media

Expanding the Ethernet Ecosystem, Supporting Ethernet Development

NEXT GENERATION OPTICAL INTERFACESPanelists

Scott Schube, Intel “Scaling Bandwidth with Optical Integration”

Matt Traverso, Cisco Systems “Scaling Architecture for Next Gen Optical Links”

David Lewis, Lumentum “Performance Photonics Enabling next Generation Interfaces”

Xinyuan Wang, Huawei “Observations on the Rate of Beyond 400GbE, 800GbE an/or

1.6TbE”

Scaling Bandwidth with Optical Integration

5

Scott Schube, Intel

Scaling Bandwidth With Optical IntegrationScott Schube

Intel Silicon Photonics Products Division

Ethernet Alliance TEF, January 2021

Ethernet Alliance TEF, January 2021Silicon Photonics Product Division

• Cost, cost, cost• Cloud expectation of cost/bit parity or better from Day 1 for a new generation

• Power• Supply scale

Optics Bandwidth Scaling Requirements

7




But also:• Availability timing and risk• Backwards compatibility

• across 2 or even 3 speed/technology generations

• Support for various network architectures• E.g. sufficient switch radix

• Configuration/application flexibility• E.g. ability to support multiple reaches, different mixes of interfaces in common platform

• Support for multiple suppliers/sources• For availability + security of supply across multiple optics types


8




But also:• Availability timing and risk• Backwards compatibility

• across 2 or even 3 speed/technology generations

• Support for various network architectures• E.g. sufficient switch radix

• Configuration/application flexibility• E.g. ability to support multiple reaches, different mixes of interfaces in common platform

• Support for multiple suppliers/sources• For availability + security of supply across multiple optics types


9

Any next-generation technology or approach need to be evaluated on all of these


• More channels• Fibers• Wavelengths

• Higher baud rate / channel

• Advanced modulation formats (e.g. PAM4, QAM)

Optics Bandwidth Scaling Options

10


• More channels• Fibers

+ Lower baud rate = easier on device technology- Packaging cost/complexity, fiber cost

• Wavelengths+ Lower baud rate, lower fiber cost- Packaging cost/complexity, link budget

• Higher baud rate / channel+ Fewer channels = simpler packaging- Performance feasibility and yield, cost/complexity, lower

switch radix, backwards compatibility challenges

• Advanced modulation formats (e.g. PAM4, QAM)+ Lower baud rate- Performance feasibility and yield, cost/complexity, lower

switch radix, backwards compatibility challenges, higher performance FEC required w/ higher latency


11


• More channels• Fibers

+ Lower baud rate = easier on device technology- Packaging cost/complexity, fiber cost

• Wavelengths+ Lower baud rate, lower fiber cost- Packaging cost/complexity, link budget

• Higher baud rate / channel+ Fewer channels = simpler packaging- Performance feasibility and yield, cost/complexity, lower

switch radix, backwards compatibility challenges

• Advanced modulation formats (e.g. PAM4, QAM)+ Lower baud rate- Performance feasibility and yield, cost/complexity, lower

switch radix, backwards compatibility challenges, higher performance FEC required w/ higher latency


12

Traditionally, the optics

imperative has been to

serialize wherever

possible, because of

optical packaging

challenges/cost


Integration Changes the Game

For high-yield process technology, cost per channel drops with the

integration of more channels

13

Source: Internal Intel analysis and estimates; your mileage may vary

Integration changes the tradeoff between optics options, enabling “scale out” as well as “scale up”


Example: 16x100G Silicon Photonics Integrated Circuit

• 16-channel (1.6Tbps, 16x100G / 4x400G DR4+) PSM transmitter PIC

• On-die integrated lasers

• 112G ring-resonator modulators

• Mode-converters and V-grooves for cost-effective high-volume packaging

• Fully integrated Tx optics enables wafer-level test

• Supports redundant lasers if needed

14

• Suitable for 2x400G products starting to be deployed in the market this year

• Monolithically-integrated 8-channel WDM demonstrated to enable 2x400G FR4/LR4 on two fiber pairs for maximum interoperability, or 800G on single duplex fiber for maximum fiber efficiency (see right)

Example: 8x100G Silicon Photonics Integrated Circuit

Silicon Photonics Product Division Ethernet Alliance TEF, January 2021 15

System Level Optical Integration: Co-Packaged Optics• Co-packaged optics targeted to provide both lower power and

cost/bit• Demonstrated Intel 1.6T CPO optics and 12.8T switch system with CPO

shown here as an example

• Support for interoperability and backwards compatibility depends on implementation• To be most useful, need to support standard optical interfaces (e.g. FR4,

DR4, DR1/FR1) and electrical interfaces (e.g. XSR)

• Support for multi-sourcing and configuration flexibility also depends on implementation. A socketed/replaceable engine approach enables

• Multiple supplier sources – can mix and match silicon and optics• Multiple technologies can coexist within this envelope (e.g. remote vs.

integrated laser) for maximum innovation flexibility and options

• “Configure at manufacture” flexibility to support different types of interfaces in the same platform

• Reworkability in system manufacturing

Silicon Photonics Product Division Ethernet Alliance TEF, January 2021

Very Quick Note on Coherent

• As noted by many, coherent optics is getting more attractive for certain applications as its maturity goes up and cost and power comes down

• In addition to the two “marquee” challenges/goals for coherent to penetrate into shorter, less fiber-constrained data center applications (cost and power competitiveness: ultimate intercept for high-BW links likely, timing TBD), other issues that may constrain or delay coherent deployment in non-greenfield data center applications include

• Interoperability with current generations

• Backwards compatibility with prior generations

• Compatibility with network architectures and radix

• Coherent optics are coming into data center networks – but when and how far down?

16


Implications for Next-Generation Optics

• With integrated optics, “scaling out” by adding more lanes is an increasingly attractive solution to scale bandwidth

• E.g. for 25T and 51T, adding more lanes of 100G (4x100G > 8x100G > 16x100G or 32x100G)

• Most cost-effective (especially if leveraging high levels of integration)

• Less technologically risky (100G/lane starting to be deployed in the market now), can get to market faster

• Can preserve compatibility and interoperability with 400G infrastructure (Nx400G breakout)

• Preserves switch radix (Nx100G or Nx400G breakout) for full network connectivity

• Channel “scale out” can be combined with lane speed “scale up” to enable even higher bandwidths for 100T+ once 200G/lane is ready (e.g. 8x200G 1.6T, 32x200G 6.4T CPO, etc.)

• Integration at the system level with co-packaged optics integration promises further benefits in power and cost

17

Silicon Photonics Product Division Ethernet Alliance TEF, January 2021 18

Thank You

[email protected]

Scaling Architecture for Next Gen Optical Links

20

Matt Traverso, Cisco Systems

matt traversoSpecial thanks to Cisco development team – many many contributorsJanuary 28, 2021

Scaling Architecture for Next Gen Optical Link

© 2020 Cisco and/or its affiliates. All rights reserved.22

• Scaling to the next gen optical link requires careful optimization of the communication blocks

Digital Communication Fundamentals

channel

Carrier

SourceSourceEncode

ChannelEncode

DigitalModulator

SinkSourceDecode

ChannelDecode

DigitalDemodulator

Ref. Carrier


• High speed optical Ethernet partitions the communications stack

• Digital modulator beings at Serializer in SerDes and extends thru the optical modulator

• Laser provides the carrier frequency

• Digital demodulator beings at detector and extends to the Deserializer which includes a CDR

• Clock & Data Recovery performs the decision and provides clock for parallel digital output

High Speed Optical Ethernet

channel

Carrier

SourceSourceEncode

ChannelEncode

DigitalModulator

SinkSourceDecode

ChannelDecode

DigitalDemodulator

TXPMD

MACPCSPMA

MACPCSPMA

RXPMD

ASIC

SerD

es

SerD

es

Digital

SerD

es

DRV

TIA Detector

Laser+

Modulator


100 Gbps/λ Electro-Optical System

• Industry-first integrated linear CMOS TIA transceiver SoC for 100 Gbps/λ

• K. R. Lakshmikumar et al., "A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s / lambda PAM-4 Optical Links," in IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3180-3190, Nov. 2019, doi: 10.1109/JSSC.2019.2939652.

• Segmented MZI driver to achieve linear PAM-4 transmission

• Lowest power 100 Gbps/λ electro-optical system

10km

Golden

Eye

4x25 Gbps

4x25 Gbps

IntegratedLinear TIA

Segmented MZI Driver

Optical ICElectrical IC

ADCCDR

PAMDecoder

PAMEncoder

Serializer

HOSTSERDES

World’s

First


Cisco Silicon Photonics Optics PDK

Segmented PAM-4 MZI

400um

ER=1

0 d

B

100Gbps PAM-4 Eye

PDK Element In Production

Impact / Benefit

100G Modulator ✔ Golden Eye

Integrated Ge PD ✔

Fiber Coupler ✔ Wide band & low loss

Silicon & Nitride Waveguides

✔ Low loss & multiple layers

VOA ✔

1:2 Switch ✔ Low power & low loss

Fully qualified 300mm Silicon Photonic process in volume production at North American foundry


Optical Coupling

Silicon nitridenanotapers

TM

TE

Edge coupler – “prong coupler”:

• Mode matched to SMF for <1dB coupling loss

• Supports entire CWDM band & beyond

• Qualified & in production on 100G Single l

• Tolerant to dicing – see ref:•R. S. Tummidi and M. Webster, "Multilayer Silicon Nitride-Based

Coupler Integrated into a Silicon Photonics Platform with <1 dB

Coupling Loss to a Standard SMF over O, S, C and L Optical

Bands," 2020 Optical Fiber Communications Conference and

Exhibition (OFC)

Measured Data

https://ieeexplore.ieee.org/abstract/document/9083115


Optical Receiver

100G-LR1-20

100GBASE-DR1100GBASE-LR1

100GBASE-FR1

Measured Module Data

S. Rauch, D. Lee, A. Vert, L. Jiang and B. Min, "Reliability Failure

Modes of an Integrated Ge Photodiode for Si Photonics," 2020

Optical Fiber Communications Conference and Exhibition (OFC),

San Diego, CA, USA, 2020, pp. 1-3

Qualified Integrated Detector


QSFP28 100G-DR/FR/LR

28

1 l

53Gbaud PAM4

Transmission Results(Live demo at OFC)

2km 10km

Silicon Photonics IC

Elec IC CeramicLaser

Fiber Array


• Scaling number of lasers

• Scaling number of lanes

Scaling 100G/Lambda →More lanes

TXPMD

MACPCSPMA

MACPCSPMA

RXPMD

ASIC

SerD

es

SerD

es

Digital

SerD

es

DRV

TIA Detector

Laser+

Modulator

4x 100Gbps per l

Fiber Array aligned & attached to Chip on Chip Assembly


Challenges in Scaling w/ Parallel

• Careful design of parallel lanes required to minimize Crosstalk

LinearIntegrated

TIA

ADCCDR

LinearIntegrated

TIA

ADCCDR

Detector

Crosstalk

𝑆𝑁𝑅1 =𝑆

𝑁1𝑆𝑁𝑅2 =𝐺 ∙ 𝑆

𝐺 ∙ 𝑁1 + 𝑁2

++ G

N2 N1

S

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Nec

essa

ry S

NR

imp

rove

men

t [d

B]

SNR Degradation [dB]

Necessary SNR Improvement of one source in case of SNR Degradation through another source


Challenges in scaling w/ Rate

Electrical Channel suffers from Frequency Dependent loss• Using PAM4 a ~17.5dB channel loss is approximated for

112G VSR length

• Using PAM2 the loss would be >30dB

Optical Channel• The fiber insertion loss does not change with data rate

• Components (Driver/Modulator/TIA) introduce bandwidth dependent loss

– Electrical channel within optical packaging also has BW dependent loss

freq

S21

DRV Mod PD TIAdigital… …digital


• Next generation optical components necessary to scale link rates

• Focusing on component BW to increase baud rate is critical

• Careful integration with multi-channel implementations is necessary to maintain link budget

Summary

Performance Photonics Enabling next Generation Interfaces

34

David Lewis, Lumentum

Performance photonics enabling

next-generation interfaces

January 28th, 2021

David Lewis

© 2021 Lumentum Operations LLC 36

Outline

▪ Possible changes in component performance in the next few years:– DML (Directly Modulated Laser) 25 GBd (today) to 50 GBd

– EML (Externally Modulated Laser) 50 GBd (today) to 100 GBd

– Coherent Components 64 – 96 GBd (today) to 128 GBd

▪ These components will enable Ethernet PMDs beyond 400 Gb/s, for example:– 8 x 50 GBd DML for 800 Gb/s interface

– 4 x 100 GBd EML for 800 Gb/s interface

– 8 x 100 GBd EML for 1600 Gb/s interface

– 128 GBd with DP-16QAM for 800ZR interface


Leading wafer fab infrastructure

North America EMEA APAC

San Jose, California USA• Gallium Arsenide

• Indium Phosphide

• Lithium Niobate

• Planar waveguides

• Flagship products

- Pump lasers

- VCSELs

- ROADMs

- Modulators

Caswell, UK• Indium Phosphide


- Coherent components

- Tunable lasers

- Photonic integrated circuits

Sagamihara, Japan• Indium Phosphide


- Data center laser chips DMLs

- PAM4 EMLs


1971: Room Temperature CW Operation of GaAlAs Lasers

1973: First to realize CW operation of DFB lasers at room temperature

1974: First operation of BH lasers

1975: First operation of DFB lasers under current-injection

1978: First operation of 1.3μm BH lasers

1979; First MP of 1.3μm lasers

1982: MP of 1.3μm BH-lasers for TAT-8 submarine systems

1985: First demonstration of high-speed properties by MQW lasers

1987: Proposal & demonstration of MD-MQW lasers with fr up to 30GHz

1989: Ultrahigh-speed 1.55μm lasers with 17GHz–BW & 16Gb/s modulation

1990: First MP of 2.5Gb/s 1.55µm MQW-DFB lasers

1991: Proposal & demonstration of innovative EML

1992: Record 16λ-WDM 10Gb/s DFB lasers

1994: Record-ultralow threshold current of 1.3μm MQW-DFB lasers with 0.5mA

1995: First demonstration of 40Gb/s EML, proposal and operation of GaInNAs lasers

1996: First MP of innovative 2.5Gb/s 640km EA-DFB lasers

1999: First MP of 10Gb/s-40km EML

2002: First MP of Uncooled 10Gb/s DFB lasers, First MP of 10Gb/s APDs w/GB of 120GHz

2003: First demonstration of uncooled 10Gb/s DFB-LD beyond 115°C2004: First MP of 40Gb/s EML

2007: First demonstration of uncooled 10Gb/s-80km EML up to 85°C2008: First demonstration of 1.3um CWDM 4ch 25Gb/s uncooled EML for 100GbE

2010: First MP of LAN-WDM 25Gb/s EML for 100G CFP-LR4

2011: First demonstration of 25Gb/s LISEL and LIPD

2014 : First demonstration of 1.3μm uncooled 50Gb/s DFB-LD beyond 80°C

2015: First MP of 1.3μm uncooled 25Gb/s DML for 100G-CWDM4

2016: First demonstration of 1.3μm 100G-PAM4 (53Gbaud) EML with 10km transmission

2016: First demonstration of 1.3μm uncooled 25Gb/s DFB-LD beyond 120°C

2018: First uncooled operation of 53-Gbaud PAM4 (106-Gb/s) EML from 25°C to 85 °C2018: First 53-Gbaud PAM4 (106-Gb/s) operation of 1.3-mm DML from 25°C to 80°C

Sagamihara Fab ~50 Years of Innovation in Optical Communications Technology

BH structure origin

DFB technology origin

10G-DML foundation

25G-EML foundation


Datacom Optics for 800G and Beyond

Lumentum is the market leader for datacom lasers:▪ Scale and performance leader

▪ Pioneer in uncooled, self-hermetic lasers

▪ Continued investment in our laser technology

Lasers for 800G and beyond:▪ 200G EML: Enabling high performance, low power consumption for 2km PAM4 modules

▪ 100G DML: Lower power, lower cost, smaller footprint than EML

▪ 100G VCSEL: Leverage high-volume 3D sensing manufacture foundry for leading performance with

the industry’s best cost structure and massive production capacity

▪ CW lasers for SiPh: Based on Lumentum’s EML chip leadership

▪ CW lasers for CPO: Families of lasers covering 20mW to over 400mW

DMLVCSEL EML CW laser

DML Status


DML Leadership

Design features:

▪ InGaAlAs MQW active layer for reliable high temperature operation

▪ Ridge waveguide structure for manufacturability with high yield

▪ Corrugation Pitch Modulated (CPM) grating and shorter cavity for higher bandwidth - 25G x 4λ

▪ Sophisticated cavity design for wide temperature operation, high reliability

▪ Self-hermetic chip for GR-468 damp heat environments

▪ Grating-pitch designs for CWDM(HL13BF) and LAN-WDM(HL13BE)

▪ PAM4 DMLs

HL13BF DFB Laser

p-Electrode

n-

Electrode

Ridge-Waveguide

n-Electrode

TLD=50ºC, If=60mA


26 Gbaud

DML vs EA-DFB PAM4 Eye Comparison

53 Gbaud

▪ Choice defines power consumption, dispersion tolerance, and cost

▪ Lumentum EMLs have historically provided the most cost and power efficient solution for leading edge interface rates

▪ Lumentum DMLs provide power and cost reduction path as ecosystem matures at a given rate


50 GBd (100 Gb/s PAM4) DML Progress

Presented by N. Sasada et al., ECOC2018 Th3F.3 (2018)

EML Status


EML Leadership

30 years of EML technology expertise dating back to Hitachi▪ Leadership position in high-speed EMLs since 2.5G and 10G era ▪ World’s first uncooled EML, now GR-468 self-hermetic devices in production

Best support for the 200G/400G PAM4 module applications▪ 1.3um LAN-WDM/CWDM wavelengths, cooled LAN-WDM and uncooled 28GBaud/53Gbaud PAM4▪ Bare chip for cost effective design and COC for quicker evaluation and production usage

Design features▪ Butt-joint structure for designing LD and EA independently▪ Buried Heterostructure with semi-insulating InP layer for high speed ▪ High temperature operation for low power consumption TEC, or “coolerless”▪ Optimized p-i-n structure in EA modulator for higher extinction ratio

n-InP sub.EA

modulator

DFB laser

WG

p-electrode

SI-InP Layer

n-electrode

MQW layer

DFB laserEA modulator


HL13B6: 53Gbaud uncooled EML performance snapshot

▪ Basic design is based on HL13B5 with high reliability and high productivity. – Achieved high BW of 42GHz and high Po at 85C compared to HL13B5

– MQW structure is optimized to achieve low TDECQ over the temperature range

HL13B6-b HL13B5

20C 70C 85C 85C

with

equalizer

(5tap)

Vpp (V) 1.2 1.2 1.2 1.2

Vmid (V) -2.5 -1.3 -1.1 -0.4

OuterER

(dB)3.5 4.6 6.2 10.4

PoAve.

(dBm)10.5 7.1 4.2 2.0

TDECQ

(dB)2.2 2.2 2.6 unmeasurable

IF=100mA

-15

-12

-9

-6

-3

0

3

0 10 20 30 40 50

S21

(dB)

Frequency (GHz)

Fig. S21 @85C

:HL13B5

:HL13B6

42 GHz @ 85C


100 GBd EML Progress

Ref: K. Adachi et al, Mo.2.B.6, ECOC2020

InP PIC and Coherent Components


InP Optical Devices Technology for Moving Networks Forward Faster

NLL-Tunable

ILMZ

MZ-SOA

Receiver PIC

NLL-Tunable

ILMZ

MZ-SOA

Receiver PIC

Intra DC

5G-

Wireless

ILMZ

DML

EML

PD/APD

High-Power DFB

DML

EML

PD/APD

High-Power DFB


Coherent InP PIC Trends

TL

MZ

Rx

100kHz LW, 17dBm fibre, 100ch

▪ Reduced power dissipation

▪ High temperature operation

▪ 50kHz LW, 18dBm fibre

▪ 120ch operation

64-96 Gbd dual-IQ fold-MZ with SOA

(40GHz BW)

64Gbd dual-IQ Rx with VOA

(45GHz BW)

▪ 128Gbd (70GHz BW)


▪ High temperature operation / Uncooled

▪ Reduced Vpi / Driverless

▪ 128Gbd

▪ Smaller chips for lower cost

Today Next

ILMZ 25Gb/s NRZ-ILMZ

Hermetic die

▪ 100Gbd PAM4 (60GHz BW)

▪ 1300nm PICs as capable as 1500nm

▪ Smaller chips for lower cost


Coherent InP OSA Trends

HB-CDM

TROSA

ROSA

64Gbd, 96Gbd

(OIF IA class 40 & 60)

▪ 128Gbd and beyond (OIF IA class 80)‒ Very high-speed RF transition & interconnections

▪ Increased thermal dissipation

43Gbd, 64Gbaud

32Gbd

▪ 64Gbaud

▪ 96Gbd and beyond‒ Very high-speed RF transition & interconnections


▪ 128Gbd and beyond‒ Very high-speed RF transition & interconnections

▪ Improved responsivity

Today Next


Summary

▪ The components for the next speed are coming:– DML chips for the module industry

– EML chips for the module industry

– InP PICs for coherent transmission

– InP packaged components for coherent transmission

▪ Timeframe is aligned with other components:– Switch / SerDes / DSP silicon

Thank you

Observations on the Rate of Beyond 400GbE,

800GbE an/or 1.6TbE

54

Xinyuan Wang, Huawei

Observations on the Rate of Beyond 400GbE,

800GbE and/or 1.6TbE

Xinyuan Wang, Huawei Technologies

Advanced Technology Drives 800GbE and 1.6TbE Standard

Eth

ern

et

Sta

nd

ard

1995

100M

1000M

1998

10GbE

25GbE

400

/200GbE

100

/40GbE

20102002

X4 Lan

Lower Co

es/FEC

mplexity

PAM4/Co

High Order

herent

Modulation

~2.5-3X $/bit

~2X $/bit

~1X $/bit

<1X $/bit

Forecasting IEEE 802.3 Beyond 400GbE

➢ Optical/Electrical Innovation to increase per

lane rate with low cost and power

➢ Advanced technology forhigher reliability and

density of optical module

Estimated cost data based on 1M ports shipped

2017 2025？

SiP/CPO/

Higher RateFEC

Modulation

1.6TbE

/800GbE200GbE

Ratified Year

50

/100GbE

5

6

DCN Application: IM-DD for 2km, 500m, 100/50m?

100Gb/s PAM4• More comprehensive discussion at 802.3cu

• Ratified in Jan 2021

• Modulation, Channel/Link Parameter

• SNR, BER, Low Latency FEC

50Gb/s PAM4

• First adopted at 802.3bs with ratified in late 2017

200Gb/s PAM#

200Gb/s per optical lane is expected with following challenge.

➢ X4 for 800GbE, 2X rate from 400GbE!

➢ X8 for 1.6TbE is a sweet point, maximum reach?

➢ As AI, HPC, URLLC, AR/VR applications emerge, lower latency is desired

◆ ~100ns latency for 2-Way KP4 FEC of 400GbE

◆ Similar FEC latency to enable 2X/4X

throughput for Beyond 400GbE

5

7

Carrier Network Application: PnP Coherent for 10km+ Fatter Pipe will drive lower Capital expenditures (CAPEX) and Operating expenses (OPEX)

comparing to L2 Link Aggregation without Hashing efficiency issue.

➢ 400GbE→1.6TbE with 4X can benefit more than 800GbE.

Supporting compatible upgrade to currently deployed network to Beyond 400GbE with

following considerations：➢ Operate over Duplex SMF with 10 and 40km reach, compatible with current fiber link infrastructure

➢ 80km is also suggested, possible coverage down to 40km reach with cost and power advantage

➢ Plug and Play optical module, avoiding field engineering, configuration, debug and test

➢ For 800Gbps solution, suggest to investigate 16QAM feasibility

Access/

Aggregate

Core/

M etro

DC10km 40km 80km

Fixed IP Network 60% 30% 10%

Mobile Backhaul Network 45% 45% 10%

5

8

To Achieve Flexible Solution of Beyond 400GbE

5

9

Based on 200Gb/s per lane, 800GbE and 1.6TbE should be a family standard.

1TbE with X5/X10 lanes will impact off-the-shelf module form factor and ASIC

architecture, not recommended.

At lease to support 100Gb/s SerDes based AUI interface.

Logic layer, PCS/FEC/PMA architecture, should support future optical

evolution.

Balance on cost, power and performance

Friendly support Breakout

Copyright©2018 Huawei Technologies Co., Ltd.

All Rights Reserved.

The information in this document may contain predictive

statements including, without limitation, statements regarding

the future financial and operating results, future product

portfolio, new technology, etc. There are a number of factors that

could cause actual results and developments to differ materially

from those expressed or implied in the predictive statements.

Therefore, such information is provided for reference purpose

only and constitutes neither an offer nor an acceptance. Huawei

may change the information at any time without notice.

把数字世界带入每个人、每个家庭、

每个组织，构建万物互联的智能世界。

Bring digital to every person, home, and organization for a fully connected, intelligent world.

Thank you.

Q & A

61

Scott SchubeIntel

Matt TraversoCisco Systems

David LewisLumentum

Xinyuan WangHuawei

Mark NowellCisco Systems

62

Join Us Tomorrow

Friday, January 29th

Panel discussion – Test & Measurement: Planning for PerformanceModerator – David J. Rodgers, Ethernet Alliance Events Chair and Teledyne LeCroy

Panelists –

John Calvin, Keysight Technologies – “Validation Methods for Emerging 106Gbps Electrical and Optical Specifications relating to IEEE P802.3cu/P802.3ck”

Steve Rumsby, Spirent – “Recommended Design Practices for the Next Generation Ethernet Rate”

Francois Robitaille, EXFO – ” Full Compliance Validation of Next-Gen Transceivers”

If you have any questions or comments, please email [email protected]

For our TEF 2021 on-demand content go to

www.ethernetalliance.org

www.ethernetalliance.org 63

mailto:[email protected]

Reference Only

64


100G-xR (single l 100G) – Block Diagram

QSFP 100G• Same hardware/software for 500m (DR), 2km (FR),

10km (LR), 20km (LR1-20)

Elec IC• Custom 16nm CMOS IC

• Flip-Chip’d onto SiPho

• Driver & TIA integrated

Silicon Photonics• Integrated Modulator & Photodiode

• Integrated optical coupling features

• Acts as substrate for Elec IC

Laser• Single Laser – DC power supply

MicroController

QSFP28 module

MUX, TX DSP

& Encoding

SerDes4x 25Gbps

optical TX path

DeMUX, Equalization,

RX DSP,Decoding

SerDes4x 25Gbps

optical RX path

1x100GADC

SPI interface

1x 100GTIA

1x 100GDriver

Elec IC

Silicon Photonics

100GModulator

100GPhotodiode

Laser

Power Supplies RefClk

ASI

C /

Ho

st

4x 25GbpsNRZ

65

TEF 2021: The Road Ahead Next Generation Optical Interfaces

Documents

Transcript of TEF 2021: The Road Ahead Next Generation Optical Interfaces