Technology Mapping. Perform the final gate selection from a particular library Two basic approaches...
Transcript of Technology Mapping. Perform the final gate selection from a particular library Two basic approaches...
![Page 1: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/1.jpg)
Technology Mapping
![Page 2: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/2.jpg)
Technology Mapping
• Perform the final gate selection from a particular library
• Two basic approaches
1. ruled based technique
2. graph covering technique
![Page 3: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/3.jpg)
Technology Mapping
• Create subject graph
– transform a given graph to a subject graph using only gates in the base function
![Page 4: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/4.jpg)
Technology Mapping
• choice of base function
– functionally complete
ex: AND-OR-NOT
NOR-NOT
NAND-NOT
– the decision of base function influences the number of patterns needed to represent the library
ex: to represent a cell f=(ab+cd)’
if base function (NAND,NOR,INV)
- 3 NAND gate, 1 INV
- 3 NOR gate, 4 INV
- .........
if base function (NAND,INV)
- one pattern only
![Page 5: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/5.jpg)
Technology Mapping
– the granularity of the base function affects the optimization potential
ex: f=abcd+efgh+ijkl+mnop
4-input nand gates
=> one mapping
2-input nand gates
=> 18 mappings
A fine resolution base-function allows for more cover and thus better quality
![Page 6: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/6.jpg)
Graph Covering (Mapping)
• DAG covering is NP-hard
• Heuristic to solve the problem (tree covering)
1. Partition the subject graph into trees
2. Cover each tree optimally (Dynamic
Programming)
![Page 7: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/7.jpg)
Graph Covering (Mapping)
Step 2:
Library
Subject graph
Bottom-up
For each nodes
. find all matching which
rooted at v
. select the best matching
which has the least cost
inv(2) nand2(3)
AOI21(4)
![Page 8: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/8.jpg)
Graph Covering (Mapping)
Step 1:
(a) Graph => tree
weak points:• loss of global view due to the step of partition into trees• cover cross bounding is not allowed• xor type gate can not be explored
![Page 9: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/9.jpg)
Graph Covering (Mapping)
(b) – only primary output is selected as root
– the mapping starts at a primary output
– mapping continues until either a primary input is encountered or until another internal node that already mapped is encounter which is an output of a cell
– select the most critical output first (mapping without interruption)
![Page 10: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/10.jpg)
Technology Mapping Minimizing Area under Delay Constraint
• Minimize area subject to constraints on signals arrival times at the output.
Two steps:
(1) Compute delay function (arrival time-area
trade off curve) at all nodes bottom up
(2) Generate the mapping solution based on
the delay function and required time at
each nodes top down
![Page 11: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/11.jpg)
Technology Mapping Minimizing Area under Delay Constraint
Step 1: (post-order traversal)
1. At each node, compute the area as a function of arrival time.
Delay function computation:
Let Gate G (a mapping) have inputs A,B
a) select a point from delay function of one input (A)
b) look for a point on the delay function of the other node(B) with “less delay” & ”minimum area”
c) combine these two points
arrival time(G) = arrival time(A) +
delay(y)
area(G) = area(A) + area(B) + gate(g)
![Page 12: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/12.jpg)
Generating the delay curve for a given match
c’
b’
d’
a’
c
b
a
e
d
area
area
delay
delay
gate delay = 1/2
gate area = 1/2
D
C
B A
![Page 13: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/13.jpg)
Lower bound merging of delay curves
e
bd
a
cb
a
e
d
area
area
delay
delaydelay curve due to
match g1
C
B A
area
delayg1 g2
merged delay curve due to g1 & g2
/* point c becomes inferior point */.
![Page 14: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/14.jpg)
Technology Mapping Minimizing Area under Delay Constraint
2. Lower bound merge process
– delete inferior points
inferior point p* = (t*,n*)
if there exists a point p = (t,a),
t > t* and a* > a
Step 2:
Timing recalculation (shift the delay curve)
Step 3:
According to the delay function and required
time, select mappings. (preorder traversal)
![Page 15: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/15.jpg)
Technology Mapping
for FPGA
![Page 16: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/16.jpg)
Technology Mapping for FPGA
Interconnection Resources
I/O CellLogic Block
Fig.1.1- A Conceptual FPGA.
FPGA : Field Programmable Gate Arrays
![Page 17: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/17.jpg)
Technology Mapping for FPGA
Look-up Table
sDQ
R
X
YABCD
Inputs
Outputs
Note: = User-programmed Multiplexor
XC2000 CLB
![Page 18: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/18.jpg)
Technology Mapping for FPGA
ef
gh
c
da b
(a+b)’(c’e+cf)+(a+b)(d’g+dh)
Figure 3.19- Act-1 Logic Block.
![Page 19: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/19.jpg)
Technology Mapping for FPGA
Traditional Logic Synthesis Tools:
Logic description
Decomposition process
Technology mapping
A mapped logic description ( a general graph)
literal counts as criterionf1=x1 | x2 | x3 | x4 | x5 | x6
f2= x1 x2’ x3’ x4’ x5’| x1’ x2 x3’ x4’ x5’
...| x1 x2 x3 x4 x5
gate library(For a 5-input RAM cell,
22 gates are needed.)5
![Page 20: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/20.jpg)
Technology Mapping for FPGA
Some Features of the FPGA:
(1) Configurable function units and interconnections.
(2) Function units are implemented using lookup tables. ( Number of literals are not so important any more
Ex: f1 = abcdef
f2 = abcde + b’d + ab’c + bcd’)
(3) Restricted interconnections.
![Page 21: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/21.jpg)
Technology Mapping For FPGA 1. Decomposition
F G
gf
xy
a b c d
k=3
![Page 22: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/22.jpg)
Technology Mapping For FPGA
2. Covering
k=5
a) With forced merge, 2 LUTs
b) Without forced merge, 3 LUTs
![Page 23: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/23.jpg)
Technology Mapping For FPGA
a) Without replicated logic, 3 LUTs
b) With replicated logic, 2 LUTs
![Page 24: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/24.jpg)
MIS-PGA
1. SIS standard script optimization
2. Decomposition so that each intermediate node with input less that K(input constraint of a logic cell)
– Roth-Karp decomposition
– partition
• kernel extraction
f = ciki+ri
cost(ki) =
• and-or decomposition
f = ab+bc+cd
=> g = bc+cd
f = ab+g
f
sup( ) sup( )k ri i
![Page 25: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/25.jpg)
Unate Covering
A covering problem where the coefficients of the matix is 0 or 1 and row i is covered if column Aj is selected and Aij = 1 .
(ie. select a set of Ai so that all row ais are covered)
A1 A2 A3
a1 1 1
a2 1 1
a3 1 1
c = { A1, A3 } or c = { A2, A3 }
![Page 26: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/26.jpg)
Binate Covering
A covering problem where the coefficient of the matrix can be -1, 0, 1 and row ai is covered if column Aj is selected and aij=1 or Aj is NOT selected and aij=-1.
A1 A2 A3
a1 1 1
a2 1 1
a3 1 1
a4 -1
c = { A1,A3 }
![Page 27: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/27.jpg)
Covering
• Covering
– find all supernode(i) for each node i
– Supernode(i) : a cluster that rooted at i and some nodes in the transitive fan-in of i. The constraint is that it has a maximum of m inputs.
supernode
![Page 28: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/28.jpg)
Covering
Use maxflow to find supernodes :
1
Because we are going to find node cut set,
For each node i: Different construction of network will result in different cut-set.
![Page 29: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/29.jpg)
Binate Covering
n1
n2 n3
n4 n5
n6
n7
S1
S2
S3
S4
S5
Covering constraint: Every intermediate node should be included in at least one selected FPGA nodeImplication constraint: If a supernode is chosen, each input to the supernode must be chosen.Output constraint: For every primary output, one supernode rooted at the outputs should be selected.
![Page 30: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/30.jpg)
Example
n1
n2 n3
n4 n5
n6
n7
S1
S2
S3
S4
S5
![Page 31: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/31.jpg)
Binate Covering
(一 ) Covering constraint
For every intermediate node, we construct
a row.
The column index is the node of supernode
If ni intermediate node is covered by
supernode Sj, then Mij = 1
Example :
S1 S2 S3 S4
n1 1
n2 1
n3 1 1
n4 1
![Page 32: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/32.jpg)
Binate Covering
(二 ) Implication constraint:
For every input j to the supernode Si
one row has to be added.
entry under Mj Si = -1 and
all supernode Sja has j as output Mj Sja = 1
![Page 33: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/33.jpg)
Example
Si ...... Sj1....Sj2
j1 -1 1
j2 -1 1Si
j1
Si... Sja.. Sjb...
j -1 1 1
Si
Sja Sjb
j2
j
![Page 34: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/34.jpg)
Binate Covering
(三 ) Output constraint:
For every primary output, we should
create a row so that one supernode
rooted at the output will be selected.
S1 S2
primary output
Si ..... Sj
O1 1 1
![Page 35: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/35.jpg)
Optimal Technology
Mapping for Delay Optimization
![Page 36: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/36.jpg)
Optimal Technology Mapping for Delay Optimization – Flow -Map
• Unit delay model (one LUT = one unit delay)
• Minimize the level of output node
• Two-step algorithm of flow-map• Labeling phase (from input to
output)• Mapping phase (from output to
input)
![Page 37: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/37.jpg)
Flow –Map : Two-Step Algorithm
• Labeling phase (from input to output)
• Mapping phase (from output to input)
![Page 38: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/38.jpg)
,),(: ),( XyandXxEyxxXXn
Definition
XxxlXXh :)( max),(
![Page 39: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/39.jpg)
1),(min)( ),(
XXhtlfeasibleKisXX
The Minimum Level of an LUT Rooted at t
The partial network The highest 3-feasible cut Determining l(t)
![Page 40: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/40.jpg)
1)()(:1 ptlorptlemma L
No Known Polynomial Algorithm for Minimum Height K-feasible Cut
The highest 3-feasible cut
)(tl ),(min),(
XXhfeasibleKisXX
+ 1
![Page 41: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/41.jpg)
Transformation of Graph
t is the node to be processed:
1. Let p be the maximum label of the nodes in Nt
2. Collapse all the nodes in Nt with level = p, together with t, into the new sink
3. Node cut transformation4. Check if there is a k-feasible cut
• If yes, node t can be packed with the nodes in and l(t) = p
• If no, {{Nt – t}, {t}} is such a cut and the l(t) = p + 1
t
Xt
![Page 42: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/42.jpg)
Example of Transformation of Graph
![Page 43: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/43.jpg)
Flow –Map : Two-Step Algorithm
• Labeling phase (from input to output)
• Mapping phase (from output to input)
![Page 44: Technology Mapping. Perform the final gate selection from a particular library Two basic approaches 1. ruled based technique 2. graph covering technique.](https://reader035.fdocuments.us/reader035/viewer/2022070307/551a4a78550346545e8b5382/html5/thumbnails/44.jpg)
Mapping phase
1. Let L contain all PO nodes. Process nodes in L one by one.
2. For a node v in L, is the minimum height K-feasible cut that computed in the labeling phase. Generate an LUT for it.
3. Put all inputs of this LUT to L.
4. Continue steps 2 and 3 until L becomes empty
),( XvXv