Technology Leadership in the Mobility Era Bohr_Intel.pdf · Tri-Gate provides steepest...

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Technology Leadership

in the Mobility Era

Mark Bohr Intel Corporation

July 9, 2012

SEMI/Gartner Market Symposium

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1

10

100

1000

10000

0.001

0.01

0.1

1

10

1970 1980 1990 2000 2010 2020 2030

nmMicron0.7x every

2 years45nm

22nm32nm

Transistor Scaling

Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor

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0.0001

0.001

0.01

0.1

1

2.0

um

1.5

um

1.0

um

.70

um

.50

um

.35

um

.25

um

.18

um

.13

um

90 n

m

65 n

m

45 n

m

32 n

m

22 n

m

14 n

m

Rel

ativ

e

Technology Generation

Gate Delay (CV/I)

SwitchingEnergy(CV2)

Transistor Performance and Power

Classical transistor scaling provided improvements in performance and active power (switching energy)

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0.0001

0.001

0.01

0.1

1

2.0

um

1.5

um

1.0

um

.70

um

.50

um

.35

um

.25

um

.18

um

.13

um

90 n

m

65 n

m

45 n

m

32 n

m

22 n

m

14 n

m

Rel

ativ

e


Gate Delay (CV/I)

LeakageCurrent

(IOFF)



… but at the expense of increased leakage current

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Non-Classical Scaling

Strained Silicon

High-k Metal Gate

Tri-Gate

90 nm 65 nm 45 nm 32 nm 22 nm 2003 2005 2007 2009 2011

Scaling now requires innovations in transistor structure and materials

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0.0001

0.001

0.01

0.1

1

2.0

um

1.5

um

1.0

um

.70

um

.50

um

.35

um

.25

um

.18

um

.13

um

90 n

m

65 n

m

45 n

m

32 n

m

22 n

m

14 n

m

Rel

ativ

e


Gate Delay (CV/I)


LeakageCurrent

(IOFF)


Transistor scaling now focuses on reducing leakage

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0.0001

0.001

0.01

0.1

1

2.0

um

1.5

um

1.0

um

.70

um

.50

um

.35

um

.25

um

.18

um

.13

um

90 n

m

65 n

m

45 n

m

32 n

m

22 n

m

14 n

m

Rel

ativ

e


Gate Delay (CV/I)


LeakageCurrent

(IOFF)


… and continues to provide improvements in performance and power

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Transistor Performance vs. Leakage

32nm 45nm 1x

0.1x

0.01x

0.001x

65nm 22nm

Low

er T

rans

isto

r Lea

kage

Higher Transistor Performance (Switching Speed)

Transistors now improving on both performance and leakage vectors

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32nm 45nm 1x

0.1x

0.01x

0.001x

65nm 22nm

Low

er T

rans

isto

r Lea

kage


Laptop UltrabookTM

Tablet

Pocket Device

Server

Desktop

Wider range of transistors to support a wider range of products

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Intel Technology Roadmap

32 nm 22 nm 14 nm

Name: P1268 P1269 P1270 P1271 P1272 P1273

Products: CPU SoC CPU SoC CPU SoC

Intel develops both CPU and SOC versions of each generation

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32 nm 22 nm 14 nm

Name: P1268 P1269 P1270 P1271 P1272 P1273


Intel develops both CPU and SOC versions of each generation

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Low Power Smartphone Products

Medfield Phone 32 nm Atom Medfield SoC 432 million transistors, 64 mm2

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32 nm SoC Technology

Intel Developer Forum, Sep. 2009

32 nm Atom Medfield SoC 432 million transistors, 64 mm2

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32 nm SoC Technology 32 nm SoC transistors range from high performance to low power

Intel Developer Forum, Sep. 2009

Low

er L

eaka

ge

Higher Performance

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32 nm 22 nm 14 nm

Name: P1268 P1269 P1270 P1271 P1272 P1273


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Gates Fins

32 nm Planar Transistors

22 nm Tri-Gate Transistors

22 nm generation introduces revolutionary 3-D Tri-Gate transistors

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1E-05

0.0001

0.001

0.01

0.1

1

10

0.0 0.2 0.4 0.6 0.8 1.0

Tri-Gate<80

mV/dec

Gate Voltage (V)

Channel Current

(normalized)

Planar~100

mV/dec

Fully Depleted Device

Tri-Gate transistors are fully depleted devices offering a steeper sub-threshold slope

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1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.6 -0.2 0.2 0.6 1.0

Driv

e C

urre

nt (

A/u

m)

VGS (V)

0.80V

SS ~69mV/decDIBL ~46 mV/V

SS ~72mV/decDIBL ~50 mV/V

NMOSPMOS

0.05V

0.80V

0.05V

Lg=26nm

C. Auth, 2012 VLSI

22 nm Tri-Gate I-V Curves

Tri-Gate provides steepest sub-threshold slope and best short channel (DIBL) values of any technology in manufacturing

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0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.5 0.6 0.7 0.8 0.9 1.0 1.1

22 nm Tri-Gate

32 nmPlanar

-0.2 V

Operating Voltage (V)

Transistor Gate Delay (normalized)

37% Faster

Performance/Power Benefits

Tri-Gate provides an unprecedented 37% speed up at low voltage or 50% active power reduction at same performance

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Reduced Channel Doping

Fully depleted Tri-Gate structure allows for reduced channel doping, providing improved performance and reduced variability

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22 nm Tri-Gate Transistors

Gate Contact

34 nm Fin Height

90 nm Gate Pitch

34 nm Fin Height

8nm Fin

Width

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22 nm Interconnects

Minimum pitch scaled ~0.7x from 32 nm for 2x transistor density

Layer Pitch TM 14 um M8 360 nm M7 320 nm M6 240 nm M5 160 nm M4 112 nm M3 80 nm M2 80 nm M1 90 nm

M8 M7 M6 M5 M4 M3 M2 M1

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0.01

0.1

1

10

180nm130nm 90nm 65nm 45nm 32nm 22nm

SR

AM

Cel

l Siz

e (u

m2 )

Technology Node

0.092 um2

0.5x per generation

SRAM Cells

0.092 um2 and 0.108 um2 SRAM cells optimized for density and power/performance

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162Mb SRAM array 0.108 um2 cell size

>1800 dies

-10C 95C

E. Karl, 2012 ISSCC

SRAM Array VMIN

0.60V medium active VMIN for low power applications

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22 nm Ivy Bridge Processor

4 Cores + Integrated Graphics 1.4 Billion Transistors, 160 mm2

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22 nm Defect Density Trend

Defect Density(cm-2)

2007 2008 2009 2010 2011 2012 2013

~2 year

22 nm defect density now at low levels for volume manufacturing

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22 nm Manufacturing Fabs

D1C Oregon

Fab 12 Arizona Fab 32 Arizona Fab 28 Israel

D1D Oregon

In production 2Q‘12

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32 nm 22 nm 14 nm

Name: P1268 P1269 P1270 P1271 P1272 P1273


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CPU vs. SoC Technology Comparison

CPU (P1270) SoC (P1271) Similarities Tri-Gate Structure Same Same Tight Transistor Pitch Same Same Dense SRAM Cell Same Same Lower Level Interconnects Same Same Fab Process Equipment Same Same

Differences Logic Transistors High Speed Low Leakage I/O Transistors Std Voltage Std and High Voltage Upper Level Interconnects High Speed Dense Precision Passives None R, C and L

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8-11 Layer Stacks

Metal I/O Trans Voltage

1.8V Thick Gate

1.2V Low Power

Passives

Precision Resistor

MIM Capacitor

High Q Inductor

Logic Transistor

Std Performance

Low Power

High Performance

Ultra Low Power

Embedded Memory

High Dense SRAM

Low Voltage SRAM

High Speed SRAM

HD OTP e-Fuse

3.3V Thick Gate

22 nm SoC Technology Features

22 nm SoC technology offers a rich menu of feature options

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32nm 45nm 1x

0.1x

0.01x

0.001x

65nm 22nm

Low

er T

rans

isto

r Lea

kage


22 nm SoC technology offers a wide range of transistors

High Perf.

Std Perf.

Low Power

Ultra Low Power

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22 nm SoC Interconnect Options

Range of SoC interconnect options for low cost or high density

Layer A B C TM 14 14 14 um M10 - - 360 nm M9 - 360 360 nm M8 360 240 160 nm M7 240 160 108 nm M6 160 108 80 nm M5 108 80 80 nm M4 80 80 80 nm M3 80 80 80 nm M2 80 80 80 nm M1 90 90 90 nm

TM

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GrapheneIII-V 3-D

MaterialsSynthesis

Dense Memory

EUV

Interconnects NanowiresPhotonics

Innovation Enabled Technology Pipeline

Future options subject to change

32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 2009 2011 2013 2015+

Manufacturing Development Research

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Advantage of an Integrated Device Manufacturer

Packaging Masks

Process

Design Tools

Product

Manufacturing

Design for Manufacturing Co-Optimized Process+Product

Rapid Yield Learning Early Product Ramp

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Conclusion

• Transistor scaling continues to provide improvements in performance, power and cost, but now with greater focus on active and leakage power reduction

• Scaling no longer follows a “traditional’” path and requires continued innovations in materials and structures

• A highly integrated approach is needed to successfully bring innovative technologies from the research phase to high volume manufacturing

• Low power System-on-Chip technologies are increasingly important to support the wide range of features needed on mobile computing devices

Technology Leadership in the Mobility Era Bohr_Intel.pdf · Tri-Gate provides steepest...

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