Technion - Israel institute of technologydepartment of Electrical Engineering

High speed digital systems laboratory

40Gbit Signal Generator for Ethernet

Annual ProjectPart A - Final presentation

& Part B – Midterm presentation

Mentor : Dr. Bar-On DavidDevelopers : Atila Fuad and Ben-Elazar Doron

May 24, 2011

40Gbit SG Agenda

Project Overview –Reminder Frame structure Part A Summary Part B – Block Diagram Next Steps Risks Gantt Chart

40Gbit SGBackground - Reminder

• Debugging a modern communication chip requires the ability to generate high sped L1 & L2 Ethernet signals on all ports of the chip.

• High speed Ethernet signals (41.25 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.

40Gbit SGProject Objectives - Reminder

The Target is to generate 40Gbps Ethernet channelSplit into two semesters:

Project A – Winter Sem. 2010/11:• 10Gbps Traffic.• generate hard coded patterns.

Project B – Spring Sem. 2011:• Continuation of Project A.• Generating 40Gbps Traffic.• GUI Software for Frame Stream Definition.

40Gbit SGEthernet MAC Frame Structure

IEEE 802.3

64 – 1518 Bytes

• Preamble – Exists due to historical reasons , contains the constant pattern 0x55 [optional].

• SFD - Marks the start of the frame, and must contain the value 0xD5.

• Destination Address - The LSB determines if the address is an individual/ unicast (0) or group/multicast (1) address.

It’s the first field that must always be provided.

40Gbit SGEthernet MAC Frame Structure

IEEE 802.3

64 – 1518 Bytes

• Source Address – Must always be provided by the client because it’s not modified by the Ethernet MAC.

• Length/Type – If the decimal value of this field is 1536 or greater it’s interpreted as a Type field (Indicates if it’s a VLAN frame or PAUSE/MAC ctrl frame).

Otherwise it’s interpreted as a Length field and represents the number of bytes in the following Data field.

40Gbit SGEthernet MAC Frame Structure

IEEE 802.3

64 – 1518 Bytes

• Data – Varies from 0-1500 Bytes, must always be provided.

• Pad – Used to ensure that the frame length is at least 64 bytes in length, and required for successful CSMA/CD

operation.

• CRC-32-Calculated over the destination address,source address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC). If an incorrect FCS value is received it indicates that the received frame is bad.

40Gbit SGPart A Requirements

• Transmit Ethernet MAC frame according to IEEE 802.3 standard using FPGA

• Establish 10Gbps link between Stratix-IV board and IXIA link-partner.

• Establish a link using SFP+ module connected by fiber cable to LP.

• Receive by IXIA valid frames that were transmitted by Stratix-IV board.

• Programming design blocks using the coming software tools:• Quartus 10.2 Design Tool• Altera USB Programming Tool• The Mega Core Functions • Altera SignalTap tool

• Hardware Programming Language: VERILOG & VHDL

40Gbit SG Part A System Hardware

Components • The Stratix IV GT HTG-S4Gx-PCIE Board with 10Gbps SFP+ modules• Link Partner – IXIA• PC with the above software tools (for design programming).• SFP+ Modules• Altera USB Programming Cable• Fiber Optic Cable

40Gbit SG Part A Block Diagram

MDIO Conf

FRAME Gen & Control Module

Clock and PLLs

ALTGX

40Gbit SG Part A Proof Of Concept

40Gbit SG Part A Proof Of Concept

40Gbit SG Part A Proof Of Concept

40Gbit SGSystem Block Diagram

Final 40Gps Signal Generator

40Gbit SG Part B FPGA & System Block Diagram

System Controller FSM

CLOCK

Frame Data Frame Data

CRC

Part A with AEL2006

Destination Address

Source Address

Type/Length

Part A with AEL2006

Part A with AEL2005

Part A with AEL2005

IFG

40G QSFP Optical Module

40Gbit SGGUI – High Level

• To transmit deferent frames patterns • To transmit error frames for validation• Friendly GUI and simple for users• Simple to develop for future developers• Requests flexible and RTL design

40Gbit SGNext Steps

• Activating and Transmitting using both SFP+ Modules which are connected to the AEL2005 Chips on board the FMC Module.

• Activating and Transmitting using both SFP+ Modules which are connected to the AEL2006 Chips on S4G-PCIE board.

• Transmitting valid frames in parallel by the 4 SFP+ Modules in 10G link.

• Learning about 40 Gigabit Ethernet architecture and standards .

• Planning 40G module using 4 modules (10G) of project A .

• Planning the 40Gbit Frame Generator module according to Part A .

• Get 40Gbit link using all four SFP+ Module.

• Transmitting valid frame on 40G link .

40Gbit SGRisks

• Have one board • No link partner for 40G yet• Different PHYs (AEL2005 vs AEL2006)• Lack of technical support to a development

board

40Gbit SGGant Chart

Task Duratio

nStart Date

Finish Date

Project B presentation 1 25.5 25.5Activating second AEL2005 6 26.5 31.5Activating AEL2006 30 1.6 30.6Transmitting by 4 SFP+ Modules in parallell 15 1.7 15.7Learning 40G architecture & standards 75 15.5 31.7Planning 40G link by 4 10G modules 30 15.6 15.7Planning 40G Frame Generator 20 1.8 20.8Planning System GUI 30 15.7 15.8Get 40Gbit link 40 21.8 30.9Implementing System GUI 60 16.8 15.10Transmitting valid frame on 40G 30 1.10 30.10

Gant Chart

40Gbit SG

Questions ?

Thank you …