Technical Feasibility of Bit multiplexing in 400GbE...

HUAWEI TECHNOLOGIES CO., LTD. IEEE 802.3 400 GbE Study Group

Technical Feasibility of Bit

multiplexing in

400GbE PMA

Xinyuan Wang, Tongtong Wang, Wenbin Yang

HUAWEI TECHNOLOGIES CO., LTD.

Supporters

Peter Stassar, Huawei

Ali Ghiasi, Independent

Chris Cole, Finisar

Edward Nakamoto, Spirent


Motivation To present an improvement proposal to the 400GE PCS as presented in

November 2013 in Dallas (in gustlin_400_01_1113), based on 10-bit

blocks, probably precluding protocol-agnostic optical modules.

An improved PCS/PMA architecture will be considered

On the basis of Bit-mux instead of muxing on the basis of 10-bit blocks

Supporting interoperation with CDAUI-n.

Enabling a protocol-agnostic optical module for usage in both Ethernet and OTN

applications.

Increasing broad market potential

Generic RS-FEC in PCS/PMA sub-layer

Correcting burst errors introduced by DFE in RX side of CDAUI or gearbox;

Keeping RS-FEC symbol integrity for MTTFPA when lane width change;

Fulfilling 1E-13 BER objective;


Background: Presentation “A 400GE PCS

Option”, Dallas November 2013

http://www.ieee802.org/3/400GSG/public/13_11/gustlin_400_02a_1113.pdf

Is it possible to define an alternative

option for 400GE, using bit-mux/demux in

the PMA and satisfying the requirement

for RS-FEC symbol integrity?


How to Address Burst Error Spreading into

Multiple errors?

In 802.3 bj concerns were raised that a

single burst error spreads into multiple error

symbols by bit-mux/demux in single RS-FEC.

Refer to “gustlin_02_0911”

Potential solution of 400GE bit-mux in optical module:

By interleaving four parallel RS-FEC one burst error can

be broken into multiple short burst errors to different RS-

FECs.

Each RS-FEC corrects short burst errors as in 802.3bj.

The advantages of this method will be quantified and

compared with symbol mux scheme.

10bit symbol

802.3bj

RS FEC

Encode

Bit Mux

4:1

100Gbps lanes

Bit Demux

1:4

10bit symbol

802.3bj

RS FEC

Encode

802.3bj

RS FEC

Encode

802.3bj

RS FEC

Encode

802.3bj

RS FEC

Decode

802.3bj

RS FEC

Decode

802.3bj

RS FEC

Decode

802.3bj

RS FEC

Decode

400GbE

100GbE


Improved PCS/PMA Architecture with Bit Mux

Use different muxing in PMAs. PMA in PCS is

16:16 or 16:8 with symbol-mux/demux and PMA

[16:4], PMA[16:8] or PMA[8:4] in module is bit-

mux/demux.

Grouping FEC lanes from 4 different RS-FECs and

do bit-mux/demux in optical module.

Gives loose constraint in layout design of CDAUI

interface .

No specific lane sequence and skew constraint in

each bit-mux/demux group.

If burst error happens in each group, it breaks to

shorter errors, then distributing to different sub RS-

FEC codewords.

MAC/RS

400G PCS

The same color

lanes from sub-

FECs distribute to

different Mux/Demux

group.

PMD

Medium

MDI

2nd

stage PMA[16:4/8]

or PMA[8:4] in module

1st stage

PMA[16:16] in PCS

Optical Module

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes from different sub-FEC

Bit muxBit mux Bit muxBit mux Bit mux Bit muxBit mux Bit mux


FEC Lanes Alignment and Reorder

No lanes ordering constraint for bit-demuxing in each multiplexed group.

Use alignment and reorder mechanism in RX side across all lanes as in 100GE.

The same color

lanes from sub-

FECs distribute to

different Mux/

Demux group.

PMD

Medium

MDI

PMA[16:4]

PMA[16:16]

Optical Module

Each bit mux block based on 4 electrical lanes from different FEC

MAC/RS

400G PCS

PMD

Medium

MDI

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Bit Demux Bit DemuxBit Demux Bit Demux

Alignment Lock & Deskew

15 3 711 2 61014 812 0 4

Lane0Lane1

Lane2Lane3

Lane4Lane5

Lane6Lane7

Lane8Lane9Lane10

Lane11

Lane12Lane13

Lane14Lane15

Reorder

Optical

Module

MAC/RS

400G PCS

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Bit mux Bit muxBit mux Bit mux

Lane01

23

45

67

89

1011

1213

1415

04

812

15

913

26

10

14

1511

73

5 913 1


Analysis of Error Spreading Beyond Symbols

This is an example of cross lane

multiplexing on CDAUI-8 and

4X100Gbps PMD. Same

mechanism is useful in CDAUI-

16 with 8X50Gbps PMD.

Use symbol mux in 1st Stage

PMA for better performance

against burst error on CDAUI

interface.

Burst error from gearbox

distributes to different sub-FEC

blocks by 2nd Stage PMA, which

keeps system MTTFPA as in

802.3bj.

TXLane A

(From FEC_0)

Lane B

(From FEC_1)

Skew on CDAUI-8

Lane C

(From FEC_2)

Lane D

(From FEC_3)

22

11

00

22

11

00

RX

Symbol Mux(2:1)

Alignment Marker Lock and Symbol Demux

2

1

0

2

1

0

2

1

0

2

1

0

Reorder

0.00.00.10.10.20.20.30.30.40.4

0.90.90.80.80.70.70.60.60.50.5

1.00.01.10.11.20.21.30.31.40.4

0.91.90.81.80.71.70.61.60.51.5

1.01.01.11.11.21.21.31.31.41.4

1.91.91.81.81.71.71.61.61.51.5

100Gbps data stream

00 0 0

11 1 1

22 2 2

0

0

1

1

2

0

0

1

1

2

0

0

1

1

2

0

0

1

1

2

1

2

0

1

0

2

1

1

0

0

Lane A

(To FEC_0)

Lane B

(To FEC_1)

Lane C

(To FEC_2)

Lane D

(To FEC_3)

Symbol

Bit

FEC Orthogonal bit Multiplex in Gearbox

(8:4)

PCS

PCS

FEC Orthogonal bit De-multiplex in Gearbox

(8:4)

Symbol Mux(2:1)

0.00.00.10.10.20.20.30.30.40.4

0.90.90.80.80.70.70.60.60.50.5

1.00.01.10.11.20.21.30.31.40.4

0.91.90.81.80.71.70.61.60.51.5

1.01.01.11.11.21.21.31.31.41.4

1.91.91.81.81.71.71.61.61.51.5

2nd

Stage

PMA

CDAUI-8

1st

Stage

PMA


Feasibility of Implementing CDAUI Layout

Require less than 4 signal layers for partial SerDes crisscrossing

interconnection in CDAUI interface between chip and optical module;

Usually PCS/PMA chip and connector are placed near each other for

shorter trace of high speed SerDes, one layer signal routing is impractical

in most designs, even with no routing constraints.

Mature hardware design examples of multi-lanes SerDes interface with

specific ordering:

X4/8/16/32 PCI Express

Courtesy: PCI Express System Architecture

XAUI


Generic Rules for Effect of Burst Errors on

Multi-FECs

Burst Error Length

(bits)

Maximum Error

Symbols

in one sub-FEC

No Bit Mux/Demux

1 1

2 to m+1 2

m+2 to 2*m+1 3

Bit Mux/Demux 2:1

1 to 2 1

3 to 2*m+2 2

2*m+3 to 4*m+2 3

Bit Mux/Demux 4:1

1 to 4 1

5 to 4*m+4 2

4*m+5 to 8*m+4 3

The table shows the number of error symbols caused by burst error in worst case.

Less error symbols occur if burst error happens within symbol boundary.

*m is symbol size.


Summary

A PCS/PMA architecture on the basis of FOM(FEC Orthogonal Multiplexing) is

proposed for 400GE.

Taking advantage of multiple parallel FEC blocks;

Supporting protocol agnostic optical module with less complexities and shorter

verification & test time;

Supporting both Ethernet and OTN applications for broad market potential;

Routing requirements from hardware route group for CDAUI is a loose

constraint and easy to implement, simpler than XAUI.

Both CDAUI and gearbox may have burst errors:

By using bit demux in gearbox burst errors are spread to different sub FECs;

RS-FEC has good performance against burst errors on CDAUI SerDes interface;

This solution can keep system MTTFPA performance as in 802.3bj.


Further Work

Investigate Burst Error model of various PMDs in 400GE;

• Different DFE architecture in PAMn/NRZ gearbox and CDAUI

interface may influence the error probability and pattern.

CDAUI-n interoperation based on FOM;

MTTFPA analysis for different random/burst error model:

• Bit Mux 4/2/1 with CDAUI-n options;

• Evaluation based on BER objective 1E-13;

Thank you www.huawei.com


Technical Feasibility of Bit multiplexing in 400GbE...

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