Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.
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Transcript of Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.
![Page 1: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/1.jpg)
Team MUX
Adam Burton Mark ColomboDavid Moore Daniel Toler
![Page 2: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/2.jpg)
Introduction
• Overview• (3) 16 Bit Master-Slave Rising edge registers
using transmission gates • ALU comprised of 5 functional blocks– Adder/Subtractor– And– Or– Shift– Multiplier
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Team MUX- ALU Block
`
A - 16
B - 16
Control - 3
Out - 16
Cout - 1
8 -1
MU
X
16
16
16
3
16
16Bit Adder
16Bit OR
16Bit AND
16Bit Multiplier
16Bit Shift
3
116
Output Register Value
![Page 4: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/4.jpg)
Adder/Subtractor Bitslice
• In our Adder/Subtractor we had two bit slices with different inverting stages. This was so we could take advantage of the inversion property to cut down on the number of inverters in the carry path.
To MUXX
Y
ZA
BSubSignal
Cin Cout
1Bit Adder (Mirror)
To next bit slice
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Shifter Bitslice
Bundled with other Bitslices
X
Shift Amount
Z1Z2Z3Z4
A
B0B1
1 bit shifter (Passgate Logic)
• We used passgate logic because the reduced output swing was not an issue, and we could save area.
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Passc2c1c0=001 A0=0>1 Out0=0>1
A0
CLK
A0
Out0Out0
Functionality Plots
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ANDC2c1c0=110 A0=1>0 B0=0 Out0=1>0
A0
CLK
Out0Out0
A0
Functionality Plots
![Page 8: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/8.jpg)
SUBc2c1c0=011 A0=1 B0=1 Out0=0
A0,B0
CLK
A0,B0
Out0Out0
Functionality Plots
![Page 9: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/9.jpg)
Innovation
Sizing Strategy What to size How to size it
Design Trade-OffsArbitrary Function – 16 bit multiplier
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Sizing
Not on Critical Path Sized to conserve areaOn Critical Path Sized for Delay
Attempted Logical Effort Calculations Result – Tapered Path for reduced delay Optimized further through simulation
Buffers between registers and ALU
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Trade-Offs
Considered Carry Look-ahead Adder Additional area and power Small benefit to delay
Supply Voltage Higher Better Delay, More Power Lower Worse Delay, Less Power Decided on Delay due to being squared in metric,
used 5V
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Innovation in Multiplier
To produce a 16-bit output, need 8-bit multiplier
Team MUX Multiplier is 16 bitsDespite limited output width, offers more
flexibility
![Page 13: Team MUX Adam BurtonMark Colombo David MooreDaniel Toler.](https://reader036.fdocuments.us/reader036/viewer/2022062322/56649e685503460f94b63f40/html5/thumbnails/13.jpg)
Multiplier Attributes
The multiplier is a basic array-based multiplier.
Delay through the multiplierPower consumption of the multiplier
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Results
Worst case delay analyzed 0x7FFF + 0x0001 Caused all bits to flip Period: 7ns Frequency: 143 MHz
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Results
Area measurementCounted up widthsExcluded buffers and multiplier Width: 4.2115*10^-3 m
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Results
Energy calculationCycle through all functions with alternating
inputIntegrated instantaneous power over period
of operationEnergy: 2.3426*10^-9 J
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Results
Final Metric D^2*A*EMetric: 4.846*10-28 s^2*m*J
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Conclusion
Meets or exceeds all specificationsImplements all functionsLow metric valueMultiplier is a valuable, common function
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Questions?