Tassadaq Hussain · 4 Bus Architectures Bus Architecture Control/Status Address Data Multi-Layer...
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Tassadaq Hussain
Transcript of Tassadaq Hussain · 4 Bus Architectures Bus Architecture Control/Status Address Data Multi-Layer...
Tassadaq Hussain
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MPSoC : MPSoC : Multiprocessor System-on-
Chip
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The era of System On Chip.
The first revolution was to embed more and more electronic devices in the same silicon die.
One main challenge was the way to interconnect all these devices efficiently.
The Bus interconnect structure was used for long time.
The industrial and academic communities faced a new challenge when the number of processing cores became two numerous for sharing a single communication medium.
A new interconnection scheme based on the Network Telecom Fabrics, the Network On Chip was born.
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Bus Architectures
Bus Architecture Control/Status Address Data
Multi-Layer Bus Crossbar Network on Chip
Network on chip or network on a chip (NoC or NOC) is a communication subsystem on an integrated circuit (commonly called a "chip"), typically between intellectual property (IP) cores in a system on a chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs.
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Multi Processors System-on-Chip (MPSoCs)
MPSoC combines several embedded processors, memories and specialized circuitry (accelerators, I/Os) interconnected through a dedicated infrastructure to provide a complete integrated system. Contrary to SoCs, MPSoCs include two or more master processors managing the application process, achieving higher performances.
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SoC to MPSoC
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Parallel task processing in time and space
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Example data flow graph with spatial clustering (parallelization)
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General Structure of MPSoC
Power ManagementPower Management
Dynamic Voltage and Frequency Scaling(DVFS): Dynamic Voltage and Frequency Scaling(DVFS):
Each PE includes a DVFS device. The power optimization consists in adapting the voltage and frequency of each PE in order to balance power consumption and performance.
In more advanced MPSoCs, a set of sensors integrated within each PE provides information about consumption, temperature, performance or any other metric needed to manage the DVFS.
Architecture taxonomy
Heterogeneous MPSoC
Programming MPSoC
Homogeneous MPSoC
“Reconfigurable Hardwarein Multiprocessor Systems”
Abstraction levels System Design
![Intelligent On/Off Dynamic Link Management for On-Chip ...on-chip interconnection network (NoC).Recent data from Intel’s Teraflop NoC prototype [7], suggests that link power consumption](https://static.fdocuments.us/doc/165x107/604c9078b6bb9b4ac622c4f2/intelligent-onoff-dynamic-link-management-for-on-chip-on-chip-interconnection.jpg)
