Tackling High-Speed Serial Designs - Keysight · •Clean Signal Stimulus ... 250 ps glitch trigger...
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Tackling High-Speed Serial Designs Page 1 Tackling High-Speed Serial Designs Sept. 2008 Page 1 Tackling High-Speed Serial Designs Copyright © 2008 Agilent Technologies Page 2 Tackling High-Speed Serial Designs Sept. 2008 Agenda • Today’s Seminar • Tackling High-Speed Serial Designs • New Solutions • Resources
Transcript of Tackling High-Speed Serial Designs - Keysight · •Clean Signal Stimulus ... 250 ps glitch trigger...
Tackling High-Speed Serial Designs Page 1
Tackling High-Speed Serial Designs
Sept. 2008Page 1
Tackling High-SpeedSerial Designs
Copyright © 2008 Agilent Technologies
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Tackling High-Speed Serial Designs
Sept. 2008
Agenda
• Today’s Seminar
• Tackling High-Speed Serial Designs
• New Solutions
• Resources
Tackling High-Speed Serial Designs Page 2
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Today’s Seminar Schedule
Characterizing Your PLL-based Designs To Manage System Jitter11:15 am
Break/Demo Fair10:00 am
A Design of Experiments for Gigabit Serial Backplane Channels3:15 pm
Lunch/Demo Fair12:15 pm
TDR, S-Parameters & Differential Measurements2:15 pmEfficient FPGA Transceiver-based Channel Modeling Using ADS1:15 pm
Successfully Negotiating The PCI EXPRESS® 2.0 Super Highway Towards Full Compliance
10:15 am
Wrap Up/Demo Fair4:15 pm
How to Solve DDR Parametric and Protocol Measurement Challenges
9:00 amTackling High-Speed Serial Designs8:30 am
SessionTime
PCI EXPRESS is a registered trademark of the PCI-SIG
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Agenda
• Today’s Seminar
• Tackling High-Speed Serial Designs
• New Solutions
• Resources
Tackling High-Speed Serial Designs Page 3
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Challenges in Serial Design Today
• Higher Data Rates Are Causing SI Problems:• Need interconnect analysis to prevent layout
problems• Need measurement-based modeling for more
accurate simulations• Need high quality probes and fixtures
• FPGAs Are Commonplace:• Can’t use a Reference Design without some
analysis• Harder to simulate the overall performance• Need to characterize the I/O buffers
• Standards Evolve Every 2-3 Years:• Leveraging existing designs gets harder• Measurement requirements get tighter• Need to buy new equipment each time
2.5 Gb/s5 Gb/s
8 Gb/s
2003 2008
2006 2010
2007 2012
PCI Express
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Gigabit Systems Are Point-to-Point Networks
• Clean Signal Stimulus• Spread Spectrum Clocking• Interconnect/Package Modeling
• Calibrated Jitter Injection• De-emphasized Signal Injection• Interconnect/Package Modeling
• Channel Modeling• Jitter Analysis
• Clock Phase Noise/Jitter
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Development Challenges
Management Concerns:CostScheduleRiskResourcesProcessInfrastructure
Designer Concerns:SpecificationsCapabilitiesVersatilityUtilizationUsabilityCost
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Development Process Needs
• Accurate Models• Accurate
Simulations• Hardware &
Software Correlation
Interconnect Design
SystemDesign
Active SignalAnalysis
ComplianceTest
• Accurate Models & Simulations
• Accurate Design Analysis
• Hardware & SoftwareCorrelation
• Accurate Design Analysis
• Test & Analysis Capability
• Measurement Automation
• Increased Team Effectiveness
• Measurement Automation
• Test & Analysis Capability
Sim
ulate
Measure
Model
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Solution: Better Design Analysis & Debug
Quantify Impedance Issues
Make Better MeasurementsWith Quality Probing
Understand Jitter
Develop an SI Expert/Lab
InfiniiMaxSoft Touch
TDR
ScopesJ-BERT
Paper
Paper
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Solution: More Predictive Design
Develop Interconnect Models
Simulate With Interconnects
Create More AccurateModels And Simulations
Do Jitter Stress Testing
Hardware/Software CorrelationBefore Layout
Spice, ADS
TDR
VNA/PLTSADS
J-BERT, SSA-J
ADSCkt/Sys/EM
Paper
Paper
Paper
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Probing Methods for Differential Signals
• InfiniiMax Active Differential Probes• 13 GHz Solder-in, Socket, Browser,
SMA, ZIF• Differential or Single-ended• Real-time Scope, DCA-J & BERT
• SoftTouch Logic Probes:• No PCB layout modification required• No remaining stubs or sockets• 16800/16900 Logic Analyzers
• DDR2/3 BGA Probes:• Command & Data signals• Scopes & Logic Analyzers
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Interconnect Modeling & Simulation
• Differential Measurements:• TDR for first order model• VNA for higher accuracy• PLTS for automated calibration
& differential measurements
• Simulation:• Incorporate measured data Into
ADS• Optimize model for measured
vs. simulated correlation• Virtual probing to assess hard
to measure signals• EM analysis of layout
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Digital Jitter is Composed of Several Mechanisms
TotalJitter (TJ)
DeterministicJitter (DJ)
RandomJitter (RJ)
PeriodicJitter (PJ)
Data Dependent Jitter (DDJ)
Inter-symbol Interference (ISI)
Duty Cycle Distortion (DCD)
Sub Rate Jitter(SRJ)
Uncorrelated PJ
Data-Correlated Data-Uncorrelated
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Jitter Tools Optimized For Specific Tasks
90000A Real-Time Scope• 13 GHz BW• Software Clock
Recovery• Clock & Data Meas.• Cycle-to-cycle Jitter• Estimates TJ• RJ/DJ Decomposition
86100C DCA-J Sampling Scope• 18+ GHz BW• Hardware Clock
Recovery• Clock & Data Meas.• Estimates TJ• RJ/DJ Decomposition• Low RJ/Phase Noise
Meas.
N4903A J-BERT
• 12.5 GHz BW• Hardware Clock
Recovery• Clock & Data Meas.• Fast TJ Meas.• RJ/DJ Decomposition• Jitter Tolerance Meas.• Calibrated Jitter Source
E5052B/E5001A SSA-J• 7+ GHz BW• Clock Meas. only• Low RJ/PJ Meas.• Phase Noise Meas.
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Agenda
• Today’s Seminar
• Tackling High-Speed Serial Designs
• New Solutions
• Resources
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DSO/DSA90000A 13 GHz Oscilloscopes
NEW:• 2.5 to 13 GHz models: 4 channels @ 20 or 40
GSa/s, up to 1 Gpts/channel, 250 ps glitch trigger• N5393B PCI Express 2.0 Compliance App• U7232A DisplayPort Compliance App.• W2631/2/3/4 DDR2/3 BGA Probes• N5425A ZIF RoHS Probe tip• N5436A Protocol Viewer Software• U7238A MIPI D-PHY Compliance Test Software
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86100C DCA-J
NEW:• 86108A Precision Waveform Analyzer
(Precision time base, 13 Gb/s CDR, >33 GHz channel input pair)
• Rev. 8: High Jitter meas, TWDP meas., TDR S-parameter display (Mag/Group Delay), Jitter Transfer, LXI compatible
• 86100CU-400 PLL and Jitter Spectrum Measurement Software (86108A or 83496B)
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N4903A J-BERT
NEW:• Jitter Pattern Generator only options• Increased Jitter Injection Ranges for DisplayPort,
SATA & PCI Express• Internal CDR options• SATA RSG Solution• N4916A De-Emphasis Signal Converter• N4917A Optical Receiver Stress Test Solution
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E5052B Signal Source Analyzer
NEW:• E5052B model:
• 100 MHz offset, lower close-in phase-noise, wider capture range
• Baseband and AM noise measurements • E5053A microwave down converter for up to
26.5 GHz measurements
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16800/16900 Logic Analyzer Systems
NEW:• W2631/2/3/4/5/6 DDR2/3 BGA Probes• B4655A FPGA Debug for Xilinx• B4656A FPGA Debug for Altera• 16902B 6-Slot Modular Mainframe• N4851A MIPI D-PHY Acquisition Probe• N4861A MIPI D-PHY Stimulus Probe
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E2960 Protocol Analysis Tools
NEW:• E2960B PCI Express 2.0 Protocol Analysis Tools
• Protocol Analyzer• Mid-bus Probe• LTSSM Exerciser
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N1930B PLTS
NEW (version 4.5):• Eye Mask Test like DCA-J• Automated Eye and Jitter Measurement • N-port De-embedding• Analysis only version (no control of
instruments)• Powerful PNA calibration algorithms now
supported
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E9010/1/2L SI Designer ADS Simulation Tools
NEW (ADS 2008 Update 1 & 2):• ADS Transient-Convolution Simulator (“HF SPICE
plus Convolution”) -- 3x speedup• Batch Simulation automates sweeps around multiple
sets of measured, simulated, or modeled data• Improved IBIS 4.2 support• EM Speed, capacity, and analysis improvements• PCI Express and DDR Design Guides• Jitter Analysis/Decomposition, BER/bathtub curves
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Web Resources
Signal Integrity Application Infowww.agilent.com/find/si
High-Speed Bus/Serial Interconnect App. Infowww.agilent.com/find/serial_info
Jitter Master Application Infowww.agilent.com/find/jittermaster
SI/Jitter eSeminarswww.agilent.com/find/sigint
Discussion Forumswww.agilent.com/find/forums New!
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Signal Integrity & Jitter Tools
SI Solutions Brochure (5988-5405EN)
Jitter Solutions Brochure(5988-9592EN)
5988-6915EN 5988-9350EN
Digital Jitter Poster(5989-0830EN)
eSeminars(available on CD)
